drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <cpu_func.h>
  14 #include <env.h>
  15 #include <log.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <netdev.h>
  19 #include <miiphy.h>
  20 #include <asm/cache.h>
  21 #include <linux/errno.h>
  22 #include <asm/io.h>
  23
  24 #ifdef CONFIG_DM_ETH
  25 #include <clk.h>
  26 #include <dm.h>
  27 #include <linux/mii.h>
  28 #include <asm/gpio.h>
  29 #endif
  30
  31 #include "sh_eth.h"
  32
  33 #ifndef CONFIG_SH_ETHER_USE_PORT
  34 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  35 #endif
  36 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  37 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  38 #endif
  39
  40 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  41         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  42 #define flush_cache_wback(addr, len)    \
  43                 flush_dcache_range((unsigned long)addr, \
  44                 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  45 #else
  46 #define flush_cache_wback(...)
  47 #endif
  48
  49 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  50 #define invalidate_cache(addr, len)             \
  51         {       \
  52                 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;  \
  53                 unsigned long start, end;       \
  54                 \
  55                 start = (unsigned long)addr;    \
  56                 end = start + len;              \
  57                 start &= ~(line_size - 1);      \
  58                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  59                 \
  60                 invalidate_dcache_range(start, end);    \
  61         }
  62 #else
  63 #define invalidate_cache(...)
  64 #endif
  65
  66 #define TIMEOUT_CNT 1000
  67
  68 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  69 {
  70         int ret = 0, timeout;
  71         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  72
  73         if (!packet || len > 0xffff) {
  74                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  75                 ret = -EINVAL;
  76                 goto err;
  77         }
  78
  79         /* packet must be a 4 byte boundary */
  80         if ((uintptr_t)packet & 3) {
  81                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  82                                 , __func__);
  83                 ret = -EFAULT;
  84                 goto err;
  85         }
  86
  87         /* Update tx descriptor */
  88         flush_cache_wback(packet, len);
  89         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  90         port_info->tx_desc_cur->td1 = len << 16;
  91         /* Must preserve the end of descriptor list indication */
  92         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  93                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  94         else
  95                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  96
  97         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  98
  99         /* Restart the transmitter if disabled */
 100         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
 101                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
 102
 103         /* Wait until packet is transmitted */
 104         timeout = TIMEOUT_CNT;
 105         do {
 106                 invalidate_cache(port_info->tx_desc_cur,
 107                                  sizeof(struct tx_desc_s));
 108                 udelay(100);
 109         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 110
 111         if (timeout < 0) {
 112                 printf(SHETHER_NAME ": transmit timeout\n");
 113                 ret = -ETIMEDOUT;
 114                 goto err;
 115         }
 116
 117         port_info->tx_desc_cur++;
 118         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 119                 port_info->tx_desc_cur = port_info->tx_desc_base;
 120
 121 err:
 122         return ret;
 123 }
 124
 125 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 126 {
 127         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 128
 129         /* Check if the rx descriptor is ready */
 130         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 131         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 132                 return -EINVAL;
 133
 134         /* Check for errors */
 135         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 136                 return -EINVAL;
 137
 138         return port_info->rx_desc_cur->rd1 & 0xffff;
 139 }
 140
 141 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 142 {
 143         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 144
 145         /* Make current descriptor available again */
 146         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 147                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 148         else
 149                 port_info->rx_desc_cur->rd0 = RD_RACT;
 150
 151         flush_cache_wback(port_info->rx_desc_cur,
 152                           sizeof(struct rx_desc_s));
 153
 154         /* Point to the next descriptor */
 155         port_info->rx_desc_cur++;
 156         if (port_info->rx_desc_cur >=
 157             port_info->rx_desc_base + NUM_RX_DESC)
 158                 port_info->rx_desc_cur = port_info->rx_desc_base;
 159 }
 160
 161 static int sh_eth_reset(struct sh_eth_dev *eth)
 162 {
 163         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 164 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 165         int ret = 0, i;
 166
 167         /* Start e-dmac transmitter and receiver */
 168         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 169
 170         /* Perform a software reset and wait for it to complete */
 171         sh_eth_write(port_info, EDMR_SRST, EDMR);
 172         for (i = 0; i < TIMEOUT_CNT; i++) {
 173                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 174                         break;
 175                 udelay(1000);
 176         }
 177
 178         if (i == TIMEOUT_CNT) {
 179                 printf(SHETHER_NAME  ": Software reset timeout\n");
 180                 ret = -EIO;
 181         }
 182
 183         return ret;
 184 #else
 185         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 186         mdelay(3);
 187         sh_eth_write(port_info,
 188                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 189
 190         return 0;
 191 #endif
 192 }
 193
 194 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 195 {
 196         int i, ret = 0;
 197         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 198         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 199         struct tx_desc_s *cur_tx_desc;
 200
 201         /*
 202          * Allocate rx descriptors. They must be aligned to size of struct
 203          * tx_desc_s.
 204          */
 205         port_info->tx_desc_alloc =
 206                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 207         if (!port_info->tx_desc_alloc) {
 208                 printf(SHETHER_NAME ": memalign failed\n");
 209                 ret = -ENOMEM;
 210                 goto err;
 211         }
 212
 213         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 214
 215         /* Make sure we use a P2 address (non-cacheable) */
 216         port_info->tx_desc_base =
 217                 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
 218         port_info->tx_desc_cur = port_info->tx_desc_base;
 219
 220         /* Initialize all descriptors */
 221         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 222              cur_tx_desc++, i++) {
 223                 cur_tx_desc->td0 = 0x00;
 224                 cur_tx_desc->td1 = 0x00;
 225                 cur_tx_desc->td2 = 0x00;
 226         }
 227
 228         /* Mark the end of the descriptors */
 229         cur_tx_desc--;
 230         cur_tx_desc->td0 |= TD_TDLE;
 231
 232         /*
 233          * Point the controller to the tx descriptor list. Must use physical
 234          * addresses
 235          */
 236         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 237 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 238         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 239         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 240         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 241 #endif
 242
 243 err:
 244         return ret;
 245 }
 246
 247 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 248 {
 249         int i, ret = 0;
 250         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 251         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 252         struct rx_desc_s *cur_rx_desc;
 253         u8 *rx_buf;
 254
 255         /*
 256          * Allocate rx descriptors. They must be aligned to size of struct
 257          * rx_desc_s.
 258          */
 259         port_info->rx_desc_alloc =
 260                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 261         if (!port_info->rx_desc_alloc) {
 262                 printf(SHETHER_NAME ": memalign failed\n");
 263                 ret = -ENOMEM;
 264                 goto err;
 265         }
 266
 267         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 268
 269         /* Make sure we use a P2 address (non-cacheable) */
 270         port_info->rx_desc_base =
 271                 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 272
 273         port_info->rx_desc_cur = port_info->rx_desc_base;
 274
 275         /*
 276          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 277          * aligned and in P2 area.
 278          */
 279         port_info->rx_buf_alloc =
 280                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 281         if (!port_info->rx_buf_alloc) {
 282                 printf(SHETHER_NAME ": alloc failed\n");
 283                 ret = -ENOMEM;
 284                 goto err_buf_alloc;
 285         }
 286
 287         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 288
 289         /* Initialize all descriptors */
 290         for (cur_rx_desc = port_info->rx_desc_base,
 291              rx_buf = port_info->rx_buf_base, i = 0;
 292              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 293                 cur_rx_desc->rd0 = RD_RACT;
 294                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 295                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 296         }
 297
 298         /* Mark the end of the descriptors */
 299         cur_rx_desc--;
 300         cur_rx_desc->rd0 |= RD_RDLE;
 301
 302         /* Point the controller to the rx descriptor list */
 303         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 304 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 305         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 306         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 307         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 308 #endif
 309
 310         return ret;
 311
 312 err_buf_alloc:
 313         free(port_info->rx_desc_alloc);
 314         port_info->rx_desc_alloc = NULL;
 315
 316 err:
 317         return ret;
 318 }
 319
 320 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 321 {
 322         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 323
 324         if (port_info->tx_desc_alloc) {
 325                 free(port_info->tx_desc_alloc);
 326                 port_info->tx_desc_alloc = NULL;
 327         }
 328 }
 329
 330 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 331 {
 332         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 333
 334         if (port_info->rx_desc_alloc) {
 335                 free(port_info->rx_desc_alloc);
 336                 port_info->rx_desc_alloc = NULL;
 337         }
 338
 339         if (port_info->rx_buf_alloc) {
 340                 free(port_info->rx_buf_alloc);
 341                 port_info->rx_buf_alloc = NULL;
 342         }
 343 }
 344
 345 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 346 {
 347         int ret = 0;
 348
 349         ret = sh_eth_tx_desc_init(eth);
 350         if (ret)
 351                 goto err_tx_init;
 352
 353         ret = sh_eth_rx_desc_init(eth);
 354         if (ret)
 355                 goto err_rx_init;
 356
 357         return ret;
 358 err_rx_init:
 359         sh_eth_tx_desc_free(eth);
 360
 361 err_tx_init:
 362         return ret;
 363 }
 364
 365 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 366                                 unsigned char *mac)
 367 {
 368         u32 val;
 369
 370         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 371         sh_eth_write(port_info, val, MAHR);
 372
 373         val = (mac[4] << 8) | mac[5];
 374         sh_eth_write(port_info, val, MALR);
 375 }
 376
 377 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 378 {
 379         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 380         unsigned long edmr;
 381
 382         /* Configure e-dmac registers */
 383         edmr = sh_eth_read(port_info, EDMR);
 384         edmr &= ~EMDR_DESC_R;
 385         edmr |= EMDR_DESC | EDMR_EL;
 386 #if defined(CONFIG_R8A77980)
 387         edmr |= EDMR_NBST;
 388 #endif
 389         sh_eth_write(port_info, edmr, EDMR);
 390
 391         sh_eth_write(port_info, 0, EESIPR);
 392         sh_eth_write(port_info, 0, TRSCER);
 393         sh_eth_write(port_info, 0, TFTR);
 394         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 395         sh_eth_write(port_info, RMCR_RST, RMCR);
 396 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 397         sh_eth_write(port_info, 0, RPADIR);
 398 #endif
 399         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 400
 401         /* Configure e-mac registers */
 402         sh_eth_write(port_info, 0, ECSIPR);
 403
 404         /* Set Mac address */
 405         sh_eth_write_hwaddr(port_info, mac);
 406
 407         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 408 #if defined(SH_ETH_TYPE_GETHER)
 409         sh_eth_write(port_info, 0, PIPR);
 410 #endif
 411 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 412         sh_eth_write(port_info, APR_AP, APR);
 413         sh_eth_write(port_info, MPR_MP, MPR);
 414         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 415 #endif
 416
 417 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 418         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 419 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 420         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 421 #endif
 422 }
 423
 424 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 425 {
 426         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 427         struct phy_device *phy = port_info->phydev;
 428         int ret = 0;
 429         u32 val = 0;
 430
 431         /* Set the transfer speed */
 432         if (phy->speed == 100) {
 433                 printf(SHETHER_NAME ": 100Base/");
 434 #if defined(SH_ETH_TYPE_GETHER)
 435                 sh_eth_write(port_info, GECMR_100B, GECMR);
 436 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 437                 sh_eth_write(port_info, 1, RTRATE);
 438 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 439                 val = ECMR_RTM;
 440 #endif
 441         } else if (phy->speed == 10) {
 442                 printf(SHETHER_NAME ": 10Base/");
 443 #if defined(SH_ETH_TYPE_GETHER)
 444                 sh_eth_write(port_info, GECMR_10B, GECMR);
 445 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 446                 sh_eth_write(port_info, 0, RTRATE);
 447 #endif
 448         }
 449 #if defined(SH_ETH_TYPE_GETHER)
 450         else if (phy->speed == 1000) {
 451                 printf(SHETHER_NAME ": 1000Base/");
 452                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 453         }
 454 #endif
 455
 456         /* Check if full duplex mode is supported by the phy */
 457         if (phy->duplex) {
 458                 printf("Full\n");
 459                 sh_eth_write(port_info,
 460                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 461                              ECMR);
 462         } else {
 463                 printf("Half\n");
 464                 sh_eth_write(port_info,
 465                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 466                              ECMR);
 467         }
 468
 469         return ret;
 470 }
 471
 472 static void sh_eth_start(struct sh_eth_dev *eth)
 473 {
 474         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 475
 476         /*
 477          * Enable the e-dmac receiver only. The transmitter will be enabled when
 478          * we have something to transmit
 479          */
 480         sh_eth_write(port_info, EDRRR_R, EDRRR);
 481 }
 482
 483 static void sh_eth_stop(struct sh_eth_dev *eth)
 484 {
 485         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 486
 487         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 488 }
 489
 490 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 491 {
 492         int ret = 0;
 493
 494         ret = sh_eth_reset(eth);
 495         if (ret)
 496                 return ret;
 497
 498         ret = sh_eth_desc_init(eth);
 499         if (ret)
 500                 return ret;
 501
 502         sh_eth_mac_regs_config(eth, mac);
 503
 504         return 0;
 505 }
 506
 507 static int sh_eth_start_common(struct sh_eth_dev *eth)
 508 {
 509         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 510         int ret;
 511
 512         ret = phy_startup(port_info->phydev);
 513         if (ret) {
 514                 printf(SHETHER_NAME ": phy startup failure\n");
 515                 return ret;
 516         }
 517
 518         ret = sh_eth_phy_regs_config(eth);
 519         if (ret)
 520                 return ret;
 521
 522         sh_eth_start(eth);
 523
 524         return 0;
 525 }
 526
 527 #ifndef CONFIG_DM_ETH
 528 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
 529 {
 530         int ret = 0;
 531         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 532         struct eth_device *dev = port_info->dev;
 533         struct phy_device *phydev;
 534
 535         phydev = phy_connect(
 536                         miiphy_get_dev_by_name(dev->name),
 537                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 538         port_info->phydev = phydev;
 539         phy_config(phydev);
 540
 541         return ret;
 542 }
 543
 544 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
 545 {
 546         struct sh_eth_dev *eth = dev->priv;
 547
 548         return sh_eth_send_common(eth, packet, len);
 549 }
 550
 551 static int sh_eth_recv_common(struct sh_eth_dev *eth)
 552 {
 553         int len = 0;
 554         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 555         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 556
 557         len = sh_eth_recv_start(eth);
 558         if (len > 0) {
 559                 invalidate_cache(packet, len);
 560                 net_process_received_packet(packet, len);
 561                 sh_eth_recv_finish(eth);
 562         } else
 563                 len = 0;
 564
 565         /* Restart the receiver if disabled */
 566         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 567                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 568
 569         return len;
 570 }
 571
 572 static int sh_eth_recv_legacy(struct eth_device *dev)
 573 {
 574         struct sh_eth_dev *eth = dev->priv;
 575
 576         return sh_eth_recv_common(eth);
 577 }
 578
 579 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
 580 {
 581         struct sh_eth_dev *eth = dev->priv;
 582         int ret;
 583
 584         ret = sh_eth_init_common(eth, dev->enetaddr);
 585         if (ret)
 586                 return ret;
 587
 588         ret = sh_eth_phy_config_legacy(eth);
 589         if (ret) {
 590                 printf(SHETHER_NAME ": phy config timeout\n");
 591                 goto err_start;
 592         }
 593
 594         ret = sh_eth_start_common(eth);
 595         if (ret)
 596                 goto err_start;
 597
 598         return 0;
 599
 600 err_start:
 601         sh_eth_tx_desc_free(eth);
 602         sh_eth_rx_desc_free(eth);
 603         return ret;
 604 }
 605
 606 void sh_eth_halt_legacy(struct eth_device *dev)
 607 {
 608         struct sh_eth_dev *eth = dev->priv;
 609
 610         sh_eth_stop(eth);
 611 }
 612
 613 int sh_eth_initialize(bd_t *bd)
 614 {
 615         int ret = 0;
 616         struct sh_eth_dev *eth = NULL;
 617         struct eth_device *dev = NULL;
 618         struct mii_dev *mdiodev;
 619
 620         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 621         if (!eth) {
 622                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 623                 ret = -ENOMEM;
 624                 goto err;
 625         }
 626
 627         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 628         if (!dev) {
 629                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 630                 ret = -ENOMEM;
 631                 goto err;
 632         }
 633         memset(dev, 0, sizeof(struct eth_device));
 634         memset(eth, 0, sizeof(struct sh_eth_dev));
 635
 636         eth->port = CONFIG_SH_ETHER_USE_PORT;
 637         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 638         eth->port_info[eth->port].iobase =
 639                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 640
 641         dev->priv = (void *)eth;
 642         dev->iobase = 0;
 643         dev->init = sh_eth_init_legacy;
 644         dev->halt = sh_eth_halt_legacy;
 645         dev->send = sh_eth_send_legacy;
 646         dev->recv = sh_eth_recv_legacy;
 647         eth->port_info[eth->port].dev = dev;
 648
 649         strcpy(dev->name, SHETHER_NAME);
 650
 651         /* Register Device to EtherNet subsystem  */
 652         eth_register(dev);
 653
 654         bb_miiphy_buses[0].priv = eth;
 655         mdiodev = mdio_alloc();
 656         if (!mdiodev)
 657                 return -ENOMEM;
 658         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 659         mdiodev->read = bb_miiphy_read;
 660         mdiodev->write = bb_miiphy_write;
 661
 662         ret = mdio_register(mdiodev);
 663         if (ret < 0)
 664                 return ret;
 665
 666         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 667                 puts("Please set MAC address\n");
 668
 669         return ret;
 670
 671 err:
 672         if (dev)
 673                 free(dev);
 674
 675         if (eth)
 676                 free(eth);
 677
 678         printf(SHETHER_NAME ": Failed\n");
 679         return ret;
 680 }
 681
 682 #else /* CONFIG_DM_ETH */
 683
 684 struct sh_ether_priv {
 685         struct sh_eth_dev       shdev;
 686
 687         struct mii_dev          *bus;
 688         phys_addr_t             iobase;
 689         struct clk              clk;
 690         struct gpio_desc        reset_gpio;
 691 };
 692
 693 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 694 {
 695         struct sh_ether_priv *priv = dev_get_priv(dev);
 696         struct sh_eth_dev *eth = &priv->shdev;
 697
 698         return sh_eth_send_common(eth, packet, len);
 699 }
 700
 701 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 702 {
 703         struct sh_ether_priv *priv = dev_get_priv(dev);
 704         struct sh_eth_dev *eth = &priv->shdev;
 705         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 706         uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
 707         int len;
 708
 709         len = sh_eth_recv_start(eth);
 710         if (len > 0) {
 711                 invalidate_cache(packet, len);
 712                 *packetp = packet;
 713
 714                 return len;
 715         } else {
 716                 len = 0;
 717
 718                 /* Restart the receiver if disabled */
 719                 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 720                         sh_eth_write(port_info, EDRRR_R, EDRRR);
 721
 722                 return -EAGAIN;
 723         }
 724 }
 725
 726 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 727 {
 728         struct sh_ether_priv *priv = dev_get_priv(dev);
 729         struct sh_eth_dev *eth = &priv->shdev;
 730         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 731
 732         sh_eth_recv_finish(eth);
 733
 734         /* Restart the receiver if disabled */
 735         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 736                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 737
 738         return 0;
 739 }
 740
 741 static int sh_ether_write_hwaddr(struct udevice *dev)
 742 {
 743         struct sh_ether_priv *priv = dev_get_priv(dev);
 744         struct sh_eth_dev *eth = &priv->shdev;
 745         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 746         struct eth_pdata *pdata = dev_get_platdata(dev);
 747
 748         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 749
 750         return 0;
 751 }
 752
 753 static int sh_eth_phy_config(struct udevice *dev)
 754 {
 755         struct sh_ether_priv *priv = dev_get_priv(dev);
 756         struct eth_pdata *pdata = dev_get_platdata(dev);
 757         struct sh_eth_dev *eth = &priv->shdev;
 758         int ret = 0;
 759         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 760         struct phy_device *phydev;
 761         int mask = 0xffffffff;
 762
 763         phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
 764         if (!phydev)
 765                 return -ENODEV;
 766
 767         phy_connect_dev(phydev, dev);
 768
 769         port_info->phydev = phydev;
 770         phy_config(phydev);
 771
 772         return ret;
 773 }
 774
 775 static int sh_ether_start(struct udevice *dev)
 776 {
 777         struct sh_ether_priv *priv = dev_get_priv(dev);
 778         struct eth_pdata *pdata = dev_get_platdata(dev);
 779         struct sh_eth_dev *eth = &priv->shdev;
 780         int ret;
 781
 782         ret = sh_eth_init_common(eth, pdata->enetaddr);
 783         if (ret)
 784                 return ret;
 785
 786         ret = sh_eth_start_common(eth);
 787         if (ret)
 788                 goto err_start;
 789
 790         return 0;
 791
 792 err_start:
 793         sh_eth_tx_desc_free(eth);
 794         sh_eth_rx_desc_free(eth);
 795         return ret;
 796 }
 797
 798 static void sh_ether_stop(struct udevice *dev)
 799 {
 800         struct sh_ether_priv *priv = dev_get_priv(dev);
 801         struct sh_eth_dev *eth = &priv->shdev;
 802         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 803
 804         phy_shutdown(port_info->phydev);
 805         sh_eth_stop(&priv->shdev);
 806 }
 807
 808 static int sh_ether_probe(struct udevice *udev)
 809 {
 810         struct eth_pdata *pdata = dev_get_platdata(udev);
 811         struct sh_ether_priv *priv = dev_get_priv(udev);
 812         struct sh_eth_dev *eth = &priv->shdev;
 813         struct ofnode_phandle_args phandle_args;
 814         struct mii_dev *mdiodev;
 815         int ret;
 816
 817         priv->iobase = pdata->iobase;
 818
 819 #if CONFIG_IS_ENABLED(CLK)
 820         ret = clk_get_by_index(udev, 0, &priv->clk);
 821         if (ret < 0)
 822                 return ret;
 823 #endif
 824
 825         ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
 826         if (!ret) {
 827                 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
 828                                            &priv->reset_gpio, GPIOD_IS_OUT);
 829         }
 830
 831         if (!dm_gpio_is_valid(&priv->reset_gpio)) {
 832                 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
 833                                      GPIOD_IS_OUT);
 834         }
 835
 836         mdiodev = mdio_alloc();
 837         if (!mdiodev) {
 838                 ret = -ENOMEM;
 839                 return ret;
 840         }
 841
 842         mdiodev->read = bb_miiphy_read;
 843         mdiodev->write = bb_miiphy_write;
 844         bb_miiphy_buses[0].priv = eth;
 845         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 846
 847         ret = mdio_register(mdiodev);
 848         if (ret < 0)
 849                 goto err_mdio_register;
 850
 851         priv->bus = miiphy_get_dev_by_name(udev->name);
 852
 853         eth->port = CONFIG_SH_ETHER_USE_PORT;
 854         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 855         eth->port_info[eth->port].iobase =
 856                 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 857
 858 #if CONFIG_IS_ENABLED(CLK)
 859         ret = clk_enable(&priv->clk);
 860         if (ret)
 861                 goto err_mdio_register;
 862 #endif
 863
 864         ret = sh_eth_init_common(eth, pdata->enetaddr);
 865         if (ret)
 866                 goto err_phy_config;
 867
 868         ret = sh_eth_phy_config(udev);
 869         if (ret) {
 870                 printf(SHETHER_NAME ": phy config timeout\n");
 871                 goto err_phy_config;
 872         }
 873
 874         return 0;
 875
 876 err_phy_config:
 877 #if CONFIG_IS_ENABLED(CLK)
 878         clk_disable(&priv->clk);
 879 #endif
 880 err_mdio_register:
 881         mdio_free(mdiodev);
 882         return ret;
 883 }
 884
 885 static int sh_ether_remove(struct udevice *udev)
 886 {
 887         struct sh_ether_priv *priv = dev_get_priv(udev);
 888         struct sh_eth_dev *eth = &priv->shdev;
 889         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 890
 891 #if CONFIG_IS_ENABLED(CLK)
 892         clk_disable(&priv->clk);
 893 #endif
 894         free(port_info->phydev);
 895         mdio_unregister(priv->bus);
 896         mdio_free(priv->bus);
 897
 898         if (dm_gpio_is_valid(&priv->reset_gpio))
 899                 dm_gpio_free(udev, &priv->reset_gpio);
 900
 901         return 0;
 902 }
 903
 904 static const struct eth_ops sh_ether_ops = {
 905         .start                  = sh_ether_start,
 906         .send                   = sh_ether_send,
 907         .recv                   = sh_ether_recv,
 908         .free_pkt               = sh_ether_free_pkt,
 909         .stop                   = sh_ether_stop,
 910         .write_hwaddr           = sh_ether_write_hwaddr,
 911 };
 912
 913 int sh_ether_ofdata_to_platdata(struct udevice *dev)
 914 {
 915         struct eth_pdata *pdata = dev_get_platdata(dev);
 916         const char *phy_mode;
 917         const fdt32_t *cell;
 918         int ret = 0;
 919
 920         pdata->iobase = devfdt_get_addr(dev);
 921         pdata->phy_interface = -1;
 922         phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 923                                NULL);
 924         if (phy_mode)
 925                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 926         if (pdata->phy_interface == -1) {
 927                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 928                 return -EINVAL;
 929         }
 930
 931         pdata->max_speed = 1000;
 932         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 933         if (cell)
 934                 pdata->max_speed = fdt32_to_cpu(*cell);
 935
 936         sprintf(bb_miiphy_buses[0].name, dev->name);
 937
 938         return ret;
 939 }
 940
 941 static const struct udevice_id sh_ether_ids[] = {
 942         { .compatible = "renesas,ether-r7s72100" },
 943         { .compatible = "renesas,ether-r8a7790" },
 944         { .compatible = "renesas,ether-r8a7791" },
 945         { .compatible = "renesas,ether-r8a7793" },
 946         { .compatible = "renesas,ether-r8a7794" },
 947         { .compatible = "renesas,gether-r8a77980" },
 948         { }
 949 };
 950
 951 U_BOOT_DRIVER(eth_sh_ether) = {
 952         .name           = "sh_ether",
 953         .id             = UCLASS_ETH,
 954         .of_match       = sh_ether_ids,
 955         .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
 956         .probe          = sh_ether_probe,
 957         .remove         = sh_ether_remove,
 958         .ops            = &sh_ether_ops,
 959         .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
 960         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 961         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 962 };
 963 #endif
 964
 965 /******* for bb_miiphy *******/
 966 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 967 {
 968         return 0;
 969 }
 970
 971 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 972 {
 973         struct sh_eth_dev *eth = bus->priv;
 974         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 975
 976         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 977
 978         return 0;
 979 }
 980
 981 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 982 {
 983         struct sh_eth_dev *eth = bus->priv;
 984         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 985
 986         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 987
 988         return 0;
 989 }
 990
 991 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 992 {
 993         struct sh_eth_dev *eth = bus->priv;
 994         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 995
 996         if (v)
 997                 sh_eth_write(port_info,
 998                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 999         else
1000                 sh_eth_write(port_info,
1001                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
1002
1003         return 0;
1004 }
1005
1006 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1007 {
1008         struct sh_eth_dev *eth = bus->priv;
1009         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1010
1011         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1012
1013         return 0;
1014 }
1015
1016 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1017 {
1018         struct sh_eth_dev *eth = bus->priv;
1019         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1020
1021         if (v)
1022                 sh_eth_write(port_info,
1023                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1024         else
1025                 sh_eth_write(port_info,
1026                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1027
1028         return 0;
1029 }
1030
1031 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1032 {
1033         udelay(10);
1034
1035         return 0;
1036 }
1037
1038 struct bb_miiphy_bus bb_miiphy_buses[] = {
1039         {
1040                 .name           = "sh_eth",
1041                 .init           = sh_eth_bb_init,
1042                 .mdio_active    = sh_eth_bb_mdio_active,
1043                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
1044                 .set_mdio       = sh_eth_bb_set_mdio,
1045                 .get_mdio       = sh_eth_bb_get_mdio,
1046                 .set_mdc        = sh_eth_bb_set_mdc,
1047                 .delay          = sh_eth_bb_delay,
1048         }
1049 };
1050
1051 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);