drivers/net/rtl8169.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rtl8169.c : U-Boot driver for the RealTek RTL8169
   4  *
   5  * Masami Komiya (mkomiya@sonare.it)
   6  *
   7  * Most part is taken from r8169.c of etherboot
   8  *
   9  */
  10
  11 /**************************************************************************
  12 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
  13 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
  14 *
  15 *    Portions of this code based on:
  16 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
  17 *               for Linux kernel 2.4.x.
  18 *
  19 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
  20 *         See Linux Driver for full information
  21 *
  22 *    Linux Driver Version 1.27a, 10.02.2002
  23 *
  24 *    Thanks to:
  25 *       Jean Chen of RealTek Semiconductor Corp. for
  26 *       providing the evaluation NIC used to develop
  27 *       this driver.  RealTek's support for Etherboot
  28 *       is appreciated.
  29 *
  30 *    REVISION HISTORY:
  31 *    ================
  32 *
  33 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
  34 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
  35 *
  36 *    Indent Options: indent -kr -i8
  37 ***************************************************************************/
  38 /*
  39  * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
  40  * Modified to use le32_to_cpu and cpu_to_le32 properly
  41  */
  42 #include <common.h>
  43 #include <dm.h>
  44 #include <errno.h>
  45 #include <malloc.h>
  46 #include <memalign.h>
  47 #include <net.h>
  48 #ifndef CONFIG_DM_ETH
  49 #include <netdev.h>
  50 #endif
  51 #include <asm/io.h>
  52 #include <pci.h>
  53
  54 #undef DEBUG_RTL8169
  55 #undef DEBUG_RTL8169_TX
  56 #undef DEBUG_RTL8169_RX
  57
  58 #define drv_version "v1.5"
  59 #define drv_date "01-17-2004"
  60
  61 static unsigned long ioaddr;
  62
  63 /* Condensed operations for readability. */
  64 #define currticks()     get_timer(0)
  65
  66 /* media options */
  67 #define MAX_UNITS 8
  68 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  69
  70 /* MAC address length*/
  71 #define MAC_ADDR_LEN    6
  72
  73 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
  74 #define MAX_ETH_FRAME_SIZE      1536
  75
  76 #define TX_FIFO_THRESH 256      /* In bytes */
  77
  78 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
  79 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  80 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  82 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
  83 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  84
  85 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
  86 #ifdef CONFIG_SYS_RX_ETH_BUFFER
  87   #define NUM_RX_DESC   CONFIG_SYS_RX_ETH_BUFFER
  88 #else
  89   #define NUM_RX_DESC   4       /* Number of Rx descriptor registers */
  90 #endif
  91 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  92 #define RX_BUF_LEN      8192
  93
  94 #define RTL_MIN_IO_SIZE 0x80
  95 #define TX_TIMEOUT  (6*HZ)
  96
  97 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
  98 #define RTL_W8(reg, val8)       writeb((val8), ioaddr + (reg))
  99 #define RTL_W16(reg, val16)     writew((val16), ioaddr + (reg))
 100 #define RTL_W32(reg, val32)     writel((val32), ioaddr + (reg))
 101 #define RTL_R8(reg)             readb(ioaddr + (reg))
 102 #define RTL_R16(reg)            readw(ioaddr + (reg))
 103 #define RTL_R32(reg)            readl(ioaddr + (reg))
 104
 105 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
 106         (pci_addr_t)(unsigned long)a)
 107 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
 108         (phys_addr_t)a)
 109
 110 enum RTL8169_registers {
 111         MAC0 = 0,               /* Ethernet hardware address. */
 112         MAR0 = 8,               /* Multicast filter. */
 113         TxDescStartAddrLow = 0x20,
 114         TxDescStartAddrHigh = 0x24,
 115         TxHDescStartAddrLow = 0x28,
 116         TxHDescStartAddrHigh = 0x2c,
 117         FLASH = 0x30,
 118         ERSR = 0x36,
 119         ChipCmd = 0x37,
 120         TxPoll = 0x38,
 121         IntrMask = 0x3C,
 122         IntrStatus = 0x3E,
 123         TxConfig = 0x40,
 124         RxConfig = 0x44,
 125         RxMissed = 0x4C,
 126         Cfg9346 = 0x50,
 127         Config0 = 0x51,
 128         Config1 = 0x52,
 129         Config2 = 0x53,
 130         Config3 = 0x54,
 131         Config4 = 0x55,
 132         Config5 = 0x56,
 133         MultiIntr = 0x5C,
 134         PHYAR = 0x60,
 135         TBICSR = 0x64,
 136         TBI_ANAR = 0x68,
 137         TBI_LPAR = 0x6A,
 138         PHYstatus = 0x6C,
 139         RxMaxSize = 0xDA,
 140         CPlusCmd = 0xE0,
 141         RxDescStartAddrLow = 0xE4,
 142         RxDescStartAddrHigh = 0xE8,
 143         EarlyTxThres = 0xEC,
 144         FuncEvent = 0xF0,
 145         FuncEventMask = 0xF4,
 146         FuncPresetState = 0xF8,
 147         FuncForceEvent = 0xFC,
 148 };
 149
 150 enum RTL8169_register_content {
 151         /*InterruptStatusBits */
 152         SYSErr = 0x8000,
 153         PCSTimeout = 0x4000,
 154         SWInt = 0x0100,
 155         TxDescUnavail = 0x80,
 156         RxFIFOOver = 0x40,
 157         RxUnderrun = 0x20,
 158         RxOverflow = 0x10,
 159         TxErr = 0x08,
 160         TxOK = 0x04,
 161         RxErr = 0x02,
 162         RxOK = 0x01,
 163
 164         /*RxStatusDesc */
 165         RxRES = 0x00200000,
 166         RxCRC = 0x00080000,
 167         RxRUNT = 0x00100000,
 168         RxRWT = 0x00400000,
 169
 170         /*ChipCmdBits */
 171         CmdReset = 0x10,
 172         CmdRxEnb = 0x08,
 173         CmdTxEnb = 0x04,
 174         RxBufEmpty = 0x01,
 175
 176         /*Cfg9346Bits */
 177         Cfg9346_Lock = 0x00,
 178         Cfg9346_Unlock = 0xC0,
 179
 180         /*rx_mode_bits */
 181         AcceptErr = 0x20,
 182         AcceptRunt = 0x10,
 183         AcceptBroadcast = 0x08,
 184         AcceptMulticast = 0x04,
 185         AcceptMyPhys = 0x02,
 186         AcceptAllPhys = 0x01,
 187
 188         /*RxConfigBits */
 189         RxCfgFIFOShift = 13,
 190         RxCfgDMAShift = 8,
 191
 192         /*TxConfigBits */
 193         TxInterFrameGapShift = 24,
 194         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 195
 196         /*rtl8169_PHYstatus */
 197         TBI_Enable = 0x80,
 198         TxFlowCtrl = 0x40,
 199         RxFlowCtrl = 0x20,
 200         _1000bpsF = 0x10,
 201         _100bps = 0x08,
 202         _10bps = 0x04,
 203         LinkStatus = 0x02,
 204         FullDup = 0x01,
 205
 206         /*GIGABIT_PHY_registers */
 207         PHY_CTRL_REG = 0,
 208         PHY_STAT_REG = 1,
 209         PHY_AUTO_NEGO_REG = 4,
 210         PHY_1000_CTRL_REG = 9,
 211
 212         /*GIGABIT_PHY_REG_BIT */
 213         PHY_Restart_Auto_Nego = 0x0200,
 214         PHY_Enable_Auto_Nego = 0x1000,
 215
 216         /* PHY_STAT_REG = 1; */
 217         PHY_Auto_Nego_Comp = 0x0020,
 218
 219         /* PHY_AUTO_NEGO_REG = 4; */
 220         PHY_Cap_10_Half = 0x0020,
 221         PHY_Cap_10_Full = 0x0040,
 222         PHY_Cap_100_Half = 0x0080,
 223         PHY_Cap_100_Full = 0x0100,
 224
 225         /* PHY_1000_CTRL_REG = 9; */
 226         PHY_Cap_1000_Full = 0x0200,
 227
 228         PHY_Cap_Null = 0x0,
 229
 230         /*_MediaType*/
 231         _10_Half = 0x01,
 232         _10_Full = 0x02,
 233         _100_Half = 0x04,
 234         _100_Full = 0x08,
 235         _1000_Full = 0x10,
 236
 237         /*_TBICSRBit*/
 238         TBILinkOK = 0x02000000,
 239 };
 240
 241 static struct {
 242         const char *name;
 243         u8 version;             /* depend on RTL8169 docs */
 244         u32 RxConfigMask;       /* should clear the bits supported by this chip */
 245 } rtl_chip_info[] = {
 246         {"RTL-8169", 0x00, 0xff7e1880,},
 247         {"RTL-8169", 0x04, 0xff7e1880,},
 248         {"RTL-8169", 0x00, 0xff7e1880,},
 249         {"RTL-8169s/8110s",     0x02, 0xff7e1880,},
 250         {"RTL-8169s/8110s",     0x04, 0xff7e1880,},
 251         {"RTL-8169sb/8110sb",   0x10, 0xff7e1880,},
 252         {"RTL-8169sc/8110sc",   0x18, 0xff7e1880,},
 253         {"RTL-8168b/8111sb",    0x30, 0xff7e1880,},
 254         {"RTL-8168b/8111sb",    0x38, 0xff7e1880,},
 255         {"RTL-8168d/8111d",     0x28, 0xff7e1880,},
 256         {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
 257         {"RTL-8168/8111g",      0x4c, 0xff7e1880,},
 258         {"RTL-8101e",           0x34, 0xff7e1880,},
 259         {"RTL-8100e",           0x32, 0xff7e1880,},
 260         {"RTL-8168h/8111h",     0x54, 0xff7e1880,},
 261 };
 262
 263 enum _DescStatusBit {
 264         OWNbit = 0x80000000,
 265         EORbit = 0x40000000,
 266         FSbit = 0x20000000,
 267         LSbit = 0x10000000,
 268 };
 269
 270 struct TxDesc {
 271         u32 status;
 272         u32 vlan_tag;
 273         u32 buf_addr;
 274         u32 buf_Haddr;
 275 };
 276
 277 struct RxDesc {
 278         u32 status;
 279         u32 vlan_tag;
 280         u32 buf_addr;
 281         u32 buf_Haddr;
 282 };
 283
 284 static unsigned char rxdata[RX_BUF_LEN];
 285
 286 #define RTL8169_DESC_SIZE 16
 287
 288 #if ARCH_DMA_MINALIGN > 256
 289 #  define RTL8169_ALIGN ARCH_DMA_MINALIGN
 290 #else
 291 #  define RTL8169_ALIGN 256
 292 #endif
 293
 294 /*
 295  * Warn if the cache-line size is larger than the descriptor size. In such
 296  * cases the driver will likely fail because the CPU needs to flush the cache
 297  * when requeuing RX buffers, therefore descriptors written by the hardware
 298  * may be discarded.
 299  *
 300  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
 301  * the driver to allocate descriptors from a pool of non-cached memory.
 302  */
 303 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 304 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
 305         !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
 306 #warning cache-line size is larger than descriptor size
 307 #endif
 308 #endif
 309
 310 /*
 311  * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
 312  * descriptors point to a part of this buffer.
 313  */
 314 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 315
 316 /*
 317  * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
 318  * descriptors point to a part of this buffer.
 319  */
 320 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 321
 322 struct rtl8169_private {
 323         ulong iobase;
 324         void *mmio_addr;        /* memory map physical address */
 325         int chipset;
 326         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
 327         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
 328         unsigned long dirty_tx;
 329         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
 330         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
 331         unsigned char *RxBufferRings;   /* Index of Rx Buffer  */
 332         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
 333         unsigned char *Tx_skbuff[NUM_TX_DESC];
 334 } tpx;
 335
 336 static struct rtl8169_private *tpc;
 337
 338 static const unsigned int rtl8169_rx_config =
 339     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 340
 341 static struct pci_device_id supported[] = {
 342         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
 343         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
 344         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
 345         {}
 346 };
 347
 348 void mdio_write(int RegAddr, int value)
 349 {
 350         int i;
 351
 352         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 353         udelay(1000);
 354
 355         for (i = 2000; i > 0; i--) {
 356                 /* Check if the RTL8169 has completed writing to the specified MII register */
 357                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
 358                         break;
 359                 } else {
 360                         udelay(100);
 361                 }
 362         }
 363 }
 364
 365 int mdio_read(int RegAddr)
 366 {
 367         int i, value = -1;
 368
 369         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 370         udelay(1000);
 371
 372         for (i = 2000; i > 0; i--) {
 373                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
 374                 if (RTL_R32(PHYAR) & 0x80000000) {
 375                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 376                         break;
 377                 } else {
 378                         udelay(100);
 379                 }
 380         }
 381         return value;
 382 }
 383
 384 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
 385 {
 386         int i;
 387         u32 tmp;
 388
 389 #ifdef DEBUG_RTL8169
 390         printf ("%s\n", __FUNCTION__);
 391 #endif
 392         ioaddr = dev_iobase;
 393
 394         /* Soft reset the chip. */
 395         RTL_W8(ChipCmd, CmdReset);
 396
 397         /* Check that the chip has finished the reset. */
 398         for (i = 1000; i > 0; i--)
 399                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 400                         break;
 401                 else
 402                         udelay(10);
 403
 404         /* identify chip attached to board */
 405         tmp = RTL_R32(TxConfig);
 406         tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
 407
 408         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
 409                 if (tmp == rtl_chip_info[i].version) {
 410                         tpc->chipset = i;
 411                         goto match;
 412                 }
 413         }
 414
 415         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
 416         printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
 417                name);
 418         printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
 419         tpc->chipset = 0;
 420
 421 match:
 422         return 0;
 423 }
 424
 425 /*
 426  * TX and RX descriptors are 16 bytes. This causes problems with the cache
 427  * maintenance on CPUs where the cache-line size exceeds the size of these
 428  * descriptors. What will happen is that when the driver receives a packet
 429  * it will be immediately requeued for the hardware to reuse. The CPU will
 430  * therefore need to flush the cache-line containing the descriptor, which
 431  * will cause all other descriptors in the same cache-line to be flushed
 432  * along with it. If one of those descriptors had been written to by the
 433  * device those changes (and the associated packet) will be lost.
 434  *
 435  * To work around this, we make use of non-cached memory if available. If
 436  * descriptors are mapped uncached there's no need to manually flush them
 437  * or invalidate them.
 438  *
 439  * Note that this only applies to descriptors. The packet data buffers do
 440  * not have the same constraints since they are 1536 bytes large, so they
 441  * are unlikely to share cache-lines.
 442  */
 443 static void *rtl_alloc_descs(unsigned int num)
 444 {
 445         size_t size = num * RTL8169_DESC_SIZE;
 446
 447 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 448         return (void *)noncached_alloc(size, RTL8169_ALIGN);
 449 #else
 450         return memalign(RTL8169_ALIGN, size);
 451 #endif
 452 }
 453
 454 /*
 455  * Cache maintenance functions. These are simple wrappers around the more
 456  * general purpose flush_cache() and invalidate_dcache_range() functions.
 457  */
 458
 459 static void rtl_inval_rx_desc(struct RxDesc *desc)
 460 {
 461 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 462         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 463         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 464
 465         invalidate_dcache_range(start, end);
 466 #endif
 467 }
 468
 469 static void rtl_flush_rx_desc(struct RxDesc *desc)
 470 {
 471 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 472         flush_cache((unsigned long)desc, sizeof(*desc));
 473 #endif
 474 }
 475
 476 static void rtl_inval_tx_desc(struct TxDesc *desc)
 477 {
 478 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 479         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 480         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 481
 482         invalidate_dcache_range(start, end);
 483 #endif
 484 }
 485
 486 static void rtl_flush_tx_desc(struct TxDesc *desc)
 487 {
 488 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 489         flush_cache((unsigned long)desc, sizeof(*desc));
 490 #endif
 491 }
 492
 493 static void rtl_inval_buffer(void *buf, size_t size)
 494 {
 495         unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
 496         unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
 497
 498         invalidate_dcache_range(start, end);
 499 }
 500
 501 static void rtl_flush_buffer(void *buf, size_t size)
 502 {
 503         flush_cache((unsigned long)buf, size);
 504 }
 505
 506 /**************************************************************************
 507 RECV - Receive a frame
 508 ***************************************************************************/
 509 #ifdef CONFIG_DM_ETH
 510 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
 511                            uchar **packetp)
 512 #else
 513 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
 514                            uchar **packetp)
 515 #endif
 516 {
 517         /* return true if there's an ethernet packet ready to read */
 518         /* nic->packet should contain data on return */
 519         /* nic->packetlen should contain length of data */
 520         int cur_rx;
 521         int length = 0;
 522
 523 #ifdef DEBUG_RTL8169_RX
 524         printf ("%s\n", __FUNCTION__);
 525 #endif
 526         ioaddr = dev_iobase;
 527
 528         cur_rx = tpc->cur_rx;
 529
 530         rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
 531
 532         if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
 533                 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 534                         length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
 535                                                 status) & 0x00001FFF) - 4;
 536
 537                         rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
 538                         memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 539
 540                         if (cur_rx == NUM_RX_DESC - 1)
 541                                 tpc->RxDescArray[cur_rx].status =
 542                                         cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 543                         else
 544                                 tpc->RxDescArray[cur_rx].status =
 545                                         cpu_to_le32(OWNbit + RX_BUF_SIZE);
 546 #ifdef CONFIG_DM_ETH
 547                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 548                                 dm_pci_mem_to_phys(dev,
 549                                         (pci_addr_t)(unsigned long)
 550                                         tpc->RxBufferRing[cur_rx]));
 551 #else
 552                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 553                                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
 554                                 tpc->RxBufferRing[cur_rx]));
 555 #endif
 556                         rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
 557 #ifdef CONFIG_DM_ETH
 558                         *packetp = rxdata;
 559 #else
 560                         net_process_received_packet(rxdata, length);
 561 #endif
 562                 } else {
 563                         puts("Error Rx");
 564                         length = -EIO;
 565                 }
 566                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
 567                 tpc->cur_rx = cur_rx;
 568                 return length;
 569
 570         } else {
 571                 ushort sts = RTL_R8(IntrStatus);
 572                 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
 573                 udelay(100);    /* wait */
 574         }
 575         tpc->cur_rx = cur_rx;
 576         return (0);             /* initially as this is called to flush the input */
 577 }
 578
 579 #ifdef CONFIG_DM_ETH
 580 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 581 {
 582         struct rtl8169_private *priv = dev_get_priv(dev);
 583
 584         return rtl_recv_common(dev, priv->iobase, packetp);
 585 }
 586 #else
 587 static int rtl_recv(struct eth_device *dev)
 588 {
 589         return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
 590                                dev->iobase, NULL);
 591 }
 592 #endif /* nCONFIG_DM_ETH */
 593
 594 #define HZ 1000
 595 /**************************************************************************
 596 SEND - Transmit a frame
 597 ***************************************************************************/
 598 #ifdef CONFIG_DM_ETH
 599 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
 600                            void *packet, int length)
 601 #else
 602 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
 603                            void *packet, int length)
 604 #endif
 605 {
 606         /* send the packet to destination */
 607
 608         u32 to;
 609         u8 *ptxb;
 610         int entry = tpc->cur_tx % NUM_TX_DESC;
 611         u32 len = length;
 612         int ret;
 613
 614 #ifdef DEBUG_RTL8169_TX
 615         int stime = currticks();
 616         printf ("%s\n", __FUNCTION__);
 617         printf("sending %d bytes\n", len);
 618 #endif
 619
 620         ioaddr = dev_iobase;
 621
 622         /* point to the current txb incase multiple tx_rings are used */
 623         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
 624         memcpy(ptxb, (char *)packet, (int)length);
 625
 626         while (len < ETH_ZLEN)
 627                 ptxb[len++] = '\0';
 628
 629         rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
 630
 631         tpc->TxDescArray[entry].buf_Haddr = 0;
 632 #ifdef CONFIG_DM_ETH
 633         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 634                 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 635 #else
 636         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 637                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 638 #endif
 639         if (entry != (NUM_TX_DESC - 1)) {
 640                 tpc->TxDescArray[entry].status =
 641                         cpu_to_le32((OWNbit | FSbit | LSbit) |
 642                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 643         } else {
 644                 tpc->TxDescArray[entry].status =
 645                         cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
 646                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 647         }
 648         rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
 649         RTL_W8(TxPoll, 0x40);   /* set polling bit */
 650
 651         tpc->cur_tx++;
 652         to = currticks() + TX_TIMEOUT;
 653         do {
 654                 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
 655         } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
 656                                 && (currticks() < to)); /* wait */
 657
 658         if (currticks() >= to) {
 659 #ifdef DEBUG_RTL8169_TX
 660                 puts("tx timeout/error\n");
 661                 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 662 #endif
 663                 ret = -ETIMEDOUT;
 664         } else {
 665 #ifdef DEBUG_RTL8169_TX
 666                 puts("tx done\n");
 667 #endif
 668                 ret = 0;
 669         }
 670         /* Delay to make net console (nc) work properly */
 671         udelay(20);
 672         return ret;
 673 }
 674
 675 #ifdef CONFIG_DM_ETH
 676 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
 677 {
 678         struct rtl8169_private *priv = dev_get_priv(dev);
 679
 680         return rtl_send_common(dev, priv->iobase, packet, length);
 681 }
 682
 683 #else
 684 static int rtl_send(struct eth_device *dev, void *packet, int length)
 685 {
 686         return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
 687                                dev->iobase, packet, length);
 688 }
 689 #endif
 690
 691 static void rtl8169_set_rx_mode(void)
 692 {
 693         u32 mc_filter[2];       /* Multicast hash filter */
 694         int rx_mode;
 695         u32 tmp = 0;
 696
 697 #ifdef DEBUG_RTL8169
 698         printf ("%s\n", __FUNCTION__);
 699 #endif
 700
 701         /* IFF_ALLMULTI */
 702         /* Too many to filter perfectly -- accept all multicasts. */
 703         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
 704         mc_filter[1] = mc_filter[0] = 0xffffffff;
 705
 706         tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
 707                                    rtl_chip_info[tpc->chipset].RxConfigMask);
 708
 709         RTL_W32(RxConfig, tmp);
 710         RTL_W32(MAR0 + 0, mc_filter[0]);
 711         RTL_W32(MAR0 + 4, mc_filter[1]);
 712 }
 713
 714 #ifdef CONFIG_DM_ETH
 715 static void rtl8169_hw_start(struct udevice *dev)
 716 #else
 717 static void rtl8169_hw_start(pci_dev_t dev)
 718 #endif
 719 {
 720         u32 i;
 721
 722 #ifdef DEBUG_RTL8169
 723         int stime = currticks();
 724         printf ("%s\n", __FUNCTION__);
 725 #endif
 726
 727 #if 0
 728         /* Soft reset the chip. */
 729         RTL_W8(ChipCmd, CmdReset);
 730
 731         /* Check that the chip has finished the reset. */
 732         for (i = 1000; i > 0; i--) {
 733                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 734                         break;
 735                 else
 736                         udelay(10);
 737         }
 738 #endif
 739
 740         RTL_W8(Cfg9346, Cfg9346_Unlock);
 741
 742         /* RTL-8169sb/8110sb or previous version */
 743         if (tpc->chipset <= 5)
 744                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 745
 746         RTL_W8(EarlyTxThres, EarlyTxThld);
 747
 748         /* For gigabit rtl8169 */
 749         RTL_W16(RxMaxSize, RxPacketMaxSize);
 750
 751         /* Set Rx Config register */
 752         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
 753                                  rtl_chip_info[tpc->chipset].RxConfigMask);
 754         RTL_W32(RxConfig, i);
 755
 756         /* Set DMA burst size and Interframe Gap Time */
 757         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
 758                                 (InterFrameGap << TxInterFrameGapShift));
 759
 760
 761         tpc->cur_rx = 0;
 762
 763 #ifdef CONFIG_DM_ETH
 764         RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
 765                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 766 #else
 767         RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
 768                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 769 #endif
 770         RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
 771 #ifdef CONFIG_DM_ETH
 772         RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
 773                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 774 #else
 775         RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
 776                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 777 #endif
 778         RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
 779
 780         /* RTL-8169sc/8110sc or later version */
 781         if (tpc->chipset > 5)
 782                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 783
 784         RTL_W8(Cfg9346, Cfg9346_Lock);
 785         udelay(10);
 786
 787         RTL_W32(RxMissed, 0);
 788
 789         rtl8169_set_rx_mode();
 790
 791         /* no early-rx interrupts */
 792         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 793
 794 #ifdef DEBUG_RTL8169
 795         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 796 #endif
 797 }
 798
 799 #ifdef CONFIG_DM_ETH
 800 static void rtl8169_init_ring(struct udevice *dev)
 801 #else
 802 static void rtl8169_init_ring(pci_dev_t dev)
 803 #endif
 804 {
 805         int i;
 806
 807 #ifdef DEBUG_RTL8169
 808         int stime = currticks();
 809         printf ("%s\n", __FUNCTION__);
 810 #endif
 811
 812         tpc->cur_rx = 0;
 813         tpc->cur_tx = 0;
 814         tpc->dirty_tx = 0;
 815         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
 816         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
 817
 818         for (i = 0; i < NUM_TX_DESC; i++) {
 819                 tpc->Tx_skbuff[i] = &txb[i];
 820         }
 821
 822         for (i = 0; i < NUM_RX_DESC; i++) {
 823                 if (i == (NUM_RX_DESC - 1))
 824                         tpc->RxDescArray[i].status =
 825                                 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 826                 else
 827                         tpc->RxDescArray[i].status =
 828                                 cpu_to_le32(OWNbit + RX_BUF_SIZE);
 829
 830                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 831 #ifdef CONFIG_DM_ETH
 832                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
 833                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 834 #else
 835                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
 836                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 837 #endif
 838                 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
 839         }
 840
 841 #ifdef DEBUG_RTL8169
 842         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 843 #endif
 844 }
 845
 846 #ifdef CONFIG_DM_ETH
 847 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
 848                                  unsigned long dev_iobase)
 849 #else
 850 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
 851                                  unsigned long dev_iobase)
 852 #endif
 853 {
 854         int i;
 855
 856 #ifdef DEBUG_RTL8169
 857         int stime = currticks();
 858         printf ("%s\n", __FUNCTION__);
 859 #endif
 860
 861         ioaddr = dev_iobase;
 862
 863         rtl8169_init_ring(dev);
 864         rtl8169_hw_start(dev);
 865         /* Construct a perfect filter frame with the mac address as first match
 866          * and broadcast for all others */
 867         for (i = 0; i < 192; i++)
 868                 txb[i] = 0xFF;
 869
 870         txb[0] = enetaddr[0];
 871         txb[1] = enetaddr[1];
 872         txb[2] = enetaddr[2];
 873         txb[3] = enetaddr[3];
 874         txb[4] = enetaddr[4];
 875         txb[5] = enetaddr[5];
 876
 877 #ifdef DEBUG_RTL8169
 878         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 879 #endif
 880 }
 881
 882 #ifdef CONFIG_DM_ETH
 883 static int rtl8169_eth_start(struct udevice *dev)
 884 {
 885         struct eth_pdata *plat = dev_get_platdata(dev);
 886         struct rtl8169_private *priv = dev_get_priv(dev);
 887
 888         rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
 889
 890         return 0;
 891 }
 892 #else
 893 /**************************************************************************
 894 RESET - Finish setting up the ethernet interface
 895 ***************************************************************************/
 896 static int rtl_reset(struct eth_device *dev, bd_t *bis)
 897 {
 898         rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
 899                              dev->enetaddr, dev->iobase);
 900
 901         return 0;
 902 }
 903 #endif /* nCONFIG_DM_ETH */
 904
 905 static void rtl_halt_common(unsigned long dev_iobase)
 906 {
 907         int i;
 908
 909 #ifdef DEBUG_RTL8169
 910         printf ("%s\n", __FUNCTION__);
 911 #endif
 912
 913         ioaddr = dev_iobase;
 914
 915         /* Stop the chip's Tx and Rx DMA processes. */
 916         RTL_W8(ChipCmd, 0x00);
 917
 918         /* Disable interrupts by clearing the interrupt mask. */
 919         RTL_W16(IntrMask, 0x0000);
 920
 921         RTL_W32(RxMissed, 0);
 922
 923         for (i = 0; i < NUM_RX_DESC; i++) {
 924                 tpc->RxBufferRing[i] = NULL;
 925         }
 926 }
 927
 928 #ifdef CONFIG_DM_ETH
 929 void rtl8169_eth_stop(struct udevice *dev)
 930 {
 931         struct rtl8169_private *priv = dev_get_priv(dev);
 932
 933         rtl_halt_common(priv->iobase);
 934 }
 935 #else
 936 /**************************************************************************
 937 HALT - Turn off ethernet interface
 938 ***************************************************************************/
 939 static void rtl_halt(struct eth_device *dev)
 940 {
 941         rtl_halt_common(dev->iobase);
 942 }
 943 #endif
 944
 945 #ifdef CONFIG_DM_ETH
 946 static int rtl8169_write_hwaddr(struct udevice *dev)
 947 {
 948         struct eth_pdata *plat = dev_get_platdata(dev);
 949         unsigned int i;
 950
 951         RTL_W8(Cfg9346, Cfg9346_Unlock);
 952
 953         for (i = 0; i < MAC_ADDR_LEN; i++)
 954                 RTL_W8(MAC0 + i, plat->enetaddr[i]);
 955
 956         RTL_W8(Cfg9346, Cfg9346_Lock);
 957
 958         return 0;
 959 }
 960 #endif
 961
 962 /**************************************************************************
 963 INIT - Look for an adapter, this routine's visible to the outside
 964 ***************************************************************************/
 965
 966 #define board_found 1
 967 #define valid_link 0
 968 static int rtl_init(unsigned long dev_ioaddr, const char *name,
 969                     unsigned char *enetaddr)
 970 {
 971         static int board_idx = -1;
 972         int i, rc;
 973         int option = -1, Cap10_100 = 0, Cap1000 = 0;
 974
 975 #ifdef DEBUG_RTL8169
 976         printf ("%s\n", __FUNCTION__);
 977 #endif
 978         ioaddr = dev_ioaddr;
 979
 980         board_idx++;
 981
 982         /* point to private storage */
 983         tpc = &tpx;
 984
 985         rc = rtl8169_init_board(ioaddr, name);
 986         if (rc)
 987                 return rc;
 988
 989         /* Get MAC address.  FIXME: read EEPROM */
 990         for (i = 0; i < MAC_ADDR_LEN; i++)
 991                 enetaddr[i] = RTL_R8(MAC0 + i);
 992
 993 #ifdef DEBUG_RTL8169
 994         printf("chipset = %d\n", tpc->chipset);
 995         printf("MAC Address");
 996         for (i = 0; i < MAC_ADDR_LEN; i++)
 997                 printf(":%02x", enetaddr[i]);
 998         putc('\n');
 999 #endif
1000
1001 #ifdef DEBUG_RTL8169
1002         /* Print out some hardware info */
1003         printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
1004 #endif
1005
1006         /* if TBI is not endbled */
1007         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
1008                 int val = mdio_read(PHY_AUTO_NEGO_REG);
1009
1010                 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1011                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
1012                 if (option > 0) {
1013 #ifdef DEBUG_RTL8169
1014                         printf("%s: Force-mode Enabled.\n", name);
1015 #endif
1016                         Cap10_100 = 0, Cap1000 = 0;
1017                         switch (option) {
1018                         case _10_Half:
1019                                 Cap10_100 = PHY_Cap_10_Half;
1020                                 Cap1000 = PHY_Cap_Null;
1021                                 break;
1022                         case _10_Full:
1023                                 Cap10_100 = PHY_Cap_10_Full;
1024                                 Cap1000 = PHY_Cap_Null;
1025                                 break;
1026                         case _100_Half:
1027                                 Cap10_100 = PHY_Cap_100_Half;
1028                                 Cap1000 = PHY_Cap_Null;
1029                                 break;
1030                         case _100_Full:
1031                                 Cap10_100 = PHY_Cap_100_Full;
1032                                 Cap1000 = PHY_Cap_Null;
1033                                 break;
1034                         case _1000_Full:
1035                                 Cap10_100 = PHY_Cap_Null;
1036                                 Cap1000 = PHY_Cap_1000_Full;
1037                                 break;
1038                         default:
1039                                 break;
1040                         }
1041                         mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F));        /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1042                         mdio_write(PHY_1000_CTRL_REG, Cap1000);
1043                 } else {
1044 #ifdef DEBUG_RTL8169
1045                         printf("%s: Auto-negotiation Enabled.\n",
1046                                name);
1047 #endif
1048                         /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1049                         mdio_write(PHY_AUTO_NEGO_REG,
1050                                    PHY_Cap_10_Half | PHY_Cap_10_Full |
1051                                    PHY_Cap_100_Half | PHY_Cap_100_Full |
1052                                    (val & 0x1F));
1053
1054                         /* enable 1000 Full Mode */
1055                         mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
1056
1057                 }
1058
1059                 /* Enable auto-negotiation and restart auto-nigotiation */
1060                 mdio_write(PHY_CTRL_REG,
1061                            PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1062                 udelay(100);
1063
1064                 /* wait for auto-negotiation process */
1065                 for (i = 10000; i > 0; i--) {
1066                         /* check if auto-negotiation complete */
1067                         if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1068                                 udelay(100);
1069                                 option = RTL_R8(PHYstatus);
1070                                 if (option & _1000bpsF) {
1071 #ifdef DEBUG_RTL8169
1072                                         printf("%s: 1000Mbps Full-duplex operation.\n",
1073                                                name);
1074 #endif
1075                                 } else {
1076 #ifdef DEBUG_RTL8169
1077                                         printf("%s: %sMbps %s-duplex operation.\n",
1078                                                name,
1079                                                (option & _100bps) ? "100" :
1080                                                "10",
1081                                                (option & FullDup) ? "Full" :
1082                                                "Half");
1083 #endif
1084                                 }
1085                                 break;
1086                         } else {
1087                                 udelay(100);
1088                         }
1089                 }               /* end for-loop to wait for auto-negotiation process */
1090
1091         } else {
1092                 udelay(100);
1093 #ifdef DEBUG_RTL8169
1094                 printf
1095                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1096                      name,
1097                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1098 #endif
1099         }
1100
1101
1102         tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1103         if (!tpc->RxDescArray)
1104                 return -ENOMEM;
1105
1106         tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1107         if (!tpc->TxDescArray)
1108                 return -ENOMEM;
1109
1110         return 0;
1111 }
1112
1113 #ifndef CONFIG_DM_ETH
1114 int rtl8169_initialize(bd_t *bis)
1115 {
1116         pci_dev_t devno;
1117         int card_number = 0;
1118         struct eth_device *dev;
1119         u32 iobase;
1120         int idx=0;
1121
1122         while(1){
1123                 unsigned int region;
1124                 u16 device;
1125                 int err;
1126
1127                 /* Find RTL8169 */
1128                 if ((devno = pci_find_devices(supported, idx++)) < 0)
1129                         break;
1130
1131                 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1132                 switch (device) {
1133                 case 0x8168:
1134                         region = 2;
1135                         break;
1136
1137                 default:
1138                         region = 1;
1139                         break;
1140                 }
1141
1142                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
1143                 iobase &= ~0xf;
1144
1145                 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1146
1147                 dev = (struct eth_device *)malloc(sizeof *dev);
1148                 if (!dev) {
1149                         printf("Can not allocate memory of rtl8169\n");
1150                         break;
1151                 }
1152
1153                 memset(dev, 0, sizeof(*dev));
1154                 sprintf (dev->name, "RTL8169#%d", card_number);
1155
1156                 dev->priv = (void *)(unsigned long)devno;
1157                 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1158
1159                 dev->init = rtl_reset;
1160                 dev->halt = rtl_halt;
1161                 dev->send = rtl_send;
1162                 dev->recv = rtl_recv;
1163
1164                 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
1165                 if (err < 0) {
1166                         printf(pr_fmt("failed to initialize card: %d\n"), err);
1167                         free(dev);
1168                         continue;
1169                 }
1170
1171                 eth_register (dev);
1172
1173                 card_number++;
1174         }
1175         return card_number;
1176 }
1177 #endif
1178
1179 #ifdef CONFIG_DM_ETH
1180 static int rtl8169_eth_probe(struct udevice *dev)
1181 {
1182         struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1183         struct rtl8169_private *priv = dev_get_priv(dev);
1184         struct eth_pdata *plat = dev_get_platdata(dev);
1185         u32 iobase;
1186         int region;
1187         int ret;
1188
1189         debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1190         switch (pplat->device) {
1191         case 0x8168:
1192                 region = 2;
1193                 break;
1194         default:
1195                 region = 1;
1196                 break;
1197         }
1198         dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
1199         iobase &= ~0xf;
1200         priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
1201
1202         ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1203         if (ret < 0) {
1204                 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1205                 return ret;
1206         }
1207
1208         return 0;
1209 }
1210
1211 static const struct eth_ops rtl8169_eth_ops = {
1212         .start  = rtl8169_eth_start,
1213         .send   = rtl8169_eth_send,
1214         .recv   = rtl8169_eth_recv,
1215         .stop   = rtl8169_eth_stop,
1216         .write_hwaddr = rtl8169_write_hwaddr,
1217 };
1218
1219 static const struct udevice_id rtl8169_eth_ids[] = {
1220         { .compatible = "realtek,rtl8169" },
1221         { }
1222 };
1223
1224 U_BOOT_DRIVER(eth_rtl8169) = {
1225         .name   = "eth_rtl8169",
1226         .id     = UCLASS_ETH,
1227         .of_match = rtl8169_eth_ids,
1228         .probe  = rtl8169_eth_probe,
1229         .ops    = &rtl8169_eth_ops,
1230         .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1231         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1232 };
1233
1234 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
1235 #endif