drivers/net/rtl8169.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rtl8169.c : U-Boot driver for the RealTek RTL8169
   4  *
   5  * Masami Komiya (mkomiya@sonare.it)
   6  *
   7  * Most part is taken from r8169.c of etherboot
   8  *
   9  */
  10
  11 /**************************************************************************
  12 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
  13 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
  14 *
  15 *    Portions of this code based on:
  16 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
  17 *               for Linux kernel 2.4.x.
  18 *
  19 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
  20 *         See Linux Driver for full information
  21 *
  22 *    Linux Driver Version 1.27a, 10.02.2002
  23 *
  24 *    Thanks to:
  25 *       Jean Chen of RealTek Semiconductor Corp. for
  26 *       providing the evaluation NIC used to develop
  27 *       this driver.  RealTek's support for Etherboot
  28 *       is appreciated.
  29 *
  30 *    REVISION HISTORY:
  31 *    ================
  32 *
  33 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
  34 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
  35 *
  36 *    Indent Options: indent -kr -i8
  37 ***************************************************************************/
  38 /*
  39  * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
  40  * Modified to use le32_to_cpu and cpu_to_le32 properly
  41  */
  42 #include <common.h>
  43 #include <cpu_func.h>
  44 #include <dm.h>
  45 #include <errno.h>
  46 #include <log.h>
  47 #include <malloc.h>
  48 #include <memalign.h>
  49 #include <net.h>
  50 #ifndef CONFIG_DM_ETH
  51 #include <netdev.h>
  52 #endif
  53 #include <asm/cache.h>
  54 #include <asm/io.h>
  55 #include <pci.h>
  56 #include <linux/delay.h>
  57
  58 #undef DEBUG_RTL8169
  59 #undef DEBUG_RTL8169_TX
  60 #undef DEBUG_RTL8169_RX
  61
  62 #define drv_version "v1.5"
  63 #define drv_date "01-17-2004"
  64
  65 static unsigned long ioaddr;
  66
  67 /* Condensed operations for readability. */
  68 #define currticks()     get_timer(0)
  69
  70 /* media options */
  71 #define MAX_UNITS 8
  72 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  73
  74 /* MAC address length*/
  75 #define MAC_ADDR_LEN    6
  76
  77 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
  78 #define MAX_ETH_FRAME_SIZE      1536
  79
  80 #define TX_FIFO_THRESH 256      /* In bytes */
  81
  82 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
  83 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  84 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  85 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  86 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
  87 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  88
  89 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
  90 #ifdef CONFIG_SYS_RX_ETH_BUFFER
  91   #define NUM_RX_DESC   CONFIG_SYS_RX_ETH_BUFFER
  92 #else
  93   #define NUM_RX_DESC   4       /* Number of Rx descriptor registers */
  94 #endif
  95 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  96 #define RX_BUF_LEN      8192
  97
  98 #define RTL_MIN_IO_SIZE 0x80
  99 #define TX_TIMEOUT  (6*HZ)
 100
 101 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
 102 #define RTL_W8(reg, val8)       writeb((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb(ioaddr + (reg))
 106 #define RTL_R16(reg)            readw(ioaddr + (reg))
 107 #define RTL_R32(reg)            readl(ioaddr + (reg))
 108
 109 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
 110         (pci_addr_t)(unsigned long)a)
 111 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
 112         (phys_addr_t)a)
 113
 114 enum RTL8169_registers {
 115         MAC0 = 0,               /* Ethernet hardware address. */
 116         MAR0 = 8,               /* Multicast filter. */
 117         TxDescStartAddrLow = 0x20,
 118         TxDescStartAddrHigh = 0x24,
 119         TxHDescStartAddrLow = 0x28,
 120         TxHDescStartAddrHigh = 0x2c,
 121         FLASH = 0x30,
 122         ERSR = 0x36,
 123         ChipCmd = 0x37,
 124         TxPoll = 0x38,
 125         IntrMask = 0x3C,
 126         IntrStatus = 0x3E,
 127         TxConfig = 0x40,
 128         RxConfig = 0x44,
 129         RxMissed = 0x4C,
 130         Cfg9346 = 0x50,
 131         Config0 = 0x51,
 132         Config1 = 0x52,
 133         Config2 = 0x53,
 134         Config3 = 0x54,
 135         Config4 = 0x55,
 136         Config5 = 0x56,
 137         MultiIntr = 0x5C,
 138         PHYAR = 0x60,
 139         TBICSR = 0x64,
 140         TBI_ANAR = 0x68,
 141         TBI_LPAR = 0x6A,
 142         PHYstatus = 0x6C,
 143         RxMaxSize = 0xDA,
 144         CPlusCmd = 0xE0,
 145         RxDescStartAddrLow = 0xE4,
 146         RxDescStartAddrHigh = 0xE8,
 147         EarlyTxThres = 0xEC,
 148         FuncEvent = 0xF0,
 149         FuncEventMask = 0xF4,
 150         FuncPresetState = 0xF8,
 151         FuncForceEvent = 0xFC,
 152 };
 153
 154 enum RTL8169_register_content {
 155         /*InterruptStatusBits */
 156         SYSErr = 0x8000,
 157         PCSTimeout = 0x4000,
 158         SWInt = 0x0100,
 159         TxDescUnavail = 0x80,
 160         RxFIFOOver = 0x40,
 161         RxUnderrun = 0x20,
 162         RxOverflow = 0x10,
 163         TxErr = 0x08,
 164         TxOK = 0x04,
 165         RxErr = 0x02,
 166         RxOK = 0x01,
 167
 168         /*RxStatusDesc */
 169         RxRES = 0x00200000,
 170         RxCRC = 0x00080000,
 171         RxRUNT = 0x00100000,
 172         RxRWT = 0x00400000,
 173
 174         /*ChipCmdBits */
 175         CmdReset = 0x10,
 176         CmdRxEnb = 0x08,
 177         CmdTxEnb = 0x04,
 178         RxBufEmpty = 0x01,
 179
 180         /*Cfg9346Bits */
 181         Cfg9346_Lock = 0x00,
 182         Cfg9346_Unlock = 0xC0,
 183
 184         /*rx_mode_bits */
 185         AcceptErr = 0x20,
 186         AcceptRunt = 0x10,
 187         AcceptBroadcast = 0x08,
 188         AcceptMulticast = 0x04,
 189         AcceptMyPhys = 0x02,
 190         AcceptAllPhys = 0x01,
 191
 192         /*RxConfigBits */
 193         RxCfgFIFOShift = 13,
 194         RxCfgDMAShift = 8,
 195
 196         /*TxConfigBits */
 197         TxInterFrameGapShift = 24,
 198         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 199
 200         /*rtl8169_PHYstatus */
 201         TBI_Enable = 0x80,
 202         TxFlowCtrl = 0x40,
 203         RxFlowCtrl = 0x20,
 204         _1000bpsF = 0x10,
 205         _100bps = 0x08,
 206         _10bps = 0x04,
 207         LinkStatus = 0x02,
 208         FullDup = 0x01,
 209
 210         /*GIGABIT_PHY_registers */
 211         PHY_CTRL_REG = 0,
 212         PHY_STAT_REG = 1,
 213         PHY_AUTO_NEGO_REG = 4,
 214         PHY_1000_CTRL_REG = 9,
 215
 216         /*GIGABIT_PHY_REG_BIT */
 217         PHY_Restart_Auto_Nego = 0x0200,
 218         PHY_Enable_Auto_Nego = 0x1000,
 219
 220         /* PHY_STAT_REG = 1; */
 221         PHY_Auto_Nego_Comp = 0x0020,
 222
 223         /* PHY_AUTO_NEGO_REG = 4; */
 224         PHY_Cap_10_Half = 0x0020,
 225         PHY_Cap_10_Full = 0x0040,
 226         PHY_Cap_100_Half = 0x0080,
 227         PHY_Cap_100_Full = 0x0100,
 228
 229         /* PHY_1000_CTRL_REG = 9; */
 230         PHY_Cap_1000_Full = 0x0200,
 231
 232         PHY_Cap_Null = 0x0,
 233
 234         /*_MediaType*/
 235         _10_Half = 0x01,
 236         _10_Full = 0x02,
 237         _100_Half = 0x04,
 238         _100_Full = 0x08,
 239         _1000_Full = 0x10,
 240
 241         /*_TBICSRBit*/
 242         TBILinkOK = 0x02000000,
 243 };
 244
 245 static struct {
 246         const char *name;
 247         u8 version;             /* depend on RTL8169 docs */
 248         u32 RxConfigMask;       /* should clear the bits supported by this chip */
 249 } rtl_chip_info[] = {
 250         {"RTL-8169", 0x00, 0xff7e1880,},
 251         {"RTL-8169", 0x04, 0xff7e1880,},
 252         {"RTL-8169", 0x00, 0xff7e1880,},
 253         {"RTL-8169s/8110s",     0x02, 0xff7e1880,},
 254         {"RTL-8169s/8110s",     0x04, 0xff7e1880,},
 255         {"RTL-8169sb/8110sb",   0x10, 0xff7e1880,},
 256         {"RTL-8169sc/8110sc",   0x18, 0xff7e1880,},
 257         {"RTL-8168b/8111sb",    0x30, 0xff7e1880,},
 258         {"RTL-8168b/8111sb",    0x38, 0xff7e1880,},
 259         {"RTL-8168c/8111c",     0x3c, 0xff7e1880,},
 260         {"RTL-8168d/8111d",     0x28, 0xff7e1880,},
 261         {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
 262         {"RTL-8168/8111g",      0x4c, 0xff7e1880,},
 263         {"RTL-8101e",           0x34, 0xff7e1880,},
 264         {"RTL-8100e",           0x32, 0xff7e1880,},
 265         {"RTL-8168h/8111h",     0x54, 0xff7e1880,},
 266 };
 267
 268 enum _DescStatusBit {
 269         OWNbit = 0x80000000,
 270         EORbit = 0x40000000,
 271         FSbit = 0x20000000,
 272         LSbit = 0x10000000,
 273 };
 274
 275 struct TxDesc {
 276         u32 status;
 277         u32 vlan_tag;
 278         u32 buf_addr;
 279         u32 buf_Haddr;
 280 };
 281
 282 struct RxDesc {
 283         u32 status;
 284         u32 vlan_tag;
 285         u32 buf_addr;
 286         u32 buf_Haddr;
 287 };
 288
 289 static unsigned char rxdata[RX_BUF_LEN];
 290
 291 #define RTL8169_DESC_SIZE 16
 292
 293 #if ARCH_DMA_MINALIGN > 256
 294 #  define RTL8169_ALIGN ARCH_DMA_MINALIGN
 295 #else
 296 #  define RTL8169_ALIGN 256
 297 #endif
 298
 299 /*
 300  * Warn if the cache-line size is larger than the descriptor size. In such
 301  * cases the driver will likely fail because the CPU needs to flush the cache
 302  * when requeuing RX buffers, therefore descriptors written by the hardware
 303  * may be discarded.
 304  *
 305  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
 306  * the driver to allocate descriptors from a pool of non-cached memory.
 307  */
 308 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 309 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
 310         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
 311 #warning cache-line size is larger than descriptor size
 312 #endif
 313 #endif
 314
 315 /*
 316  * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
 317  * descriptors point to a part of this buffer.
 318  */
 319 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 320
 321 /*
 322  * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
 323  * descriptors point to a part of this buffer.
 324  */
 325 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 326
 327 struct rtl8169_private {
 328         ulong iobase;
 329         void *mmio_addr;        /* memory map physical address */
 330         int chipset;
 331         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
 332         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
 333         unsigned long dirty_tx;
 334         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
 335         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
 336         unsigned char *RxBufferRings;   /* Index of Rx Buffer  */
 337         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
 338         unsigned char *Tx_skbuff[NUM_TX_DESC];
 339 } tpx;
 340
 341 static struct rtl8169_private *tpc;
 342
 343 static const unsigned int rtl8169_rx_config =
 344     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 345
 346 static struct pci_device_id supported[] = {
 347         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
 348         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
 349         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
 350         {}
 351 };
 352
 353 void mdio_write(int RegAddr, int value)
 354 {
 355         int i;
 356
 357         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 358         udelay(1000);
 359
 360         for (i = 2000; i > 0; i--) {
 361                 /* Check if the RTL8169 has completed writing to the specified MII register */
 362                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
 363                         break;
 364                 } else {
 365                         udelay(100);
 366                 }
 367         }
 368 }
 369
 370 int mdio_read(int RegAddr)
 371 {
 372         int i, value = -1;
 373
 374         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 375         udelay(1000);
 376
 377         for (i = 2000; i > 0; i--) {
 378                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
 379                 if (RTL_R32(PHYAR) & 0x80000000) {
 380                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 381                         break;
 382                 } else {
 383                         udelay(100);
 384                 }
 385         }
 386         return value;
 387 }
 388
 389 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
 390 {
 391         int i;
 392         u32 tmp;
 393
 394 #ifdef DEBUG_RTL8169
 395         printf ("%s\n", __FUNCTION__);
 396 #endif
 397         ioaddr = dev_iobase;
 398
 399         /* Soft reset the chip. */
 400         RTL_W8(ChipCmd, CmdReset);
 401
 402         /* Check that the chip has finished the reset. */
 403         for (i = 1000; i > 0; i--)
 404                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 405                         break;
 406                 else
 407                         udelay(10);
 408
 409         /* identify chip attached to board */
 410         tmp = RTL_R32(TxConfig);
 411         tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
 412
 413         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
 414                 if (tmp == rtl_chip_info[i].version) {
 415                         tpc->chipset = i;
 416                         goto match;
 417                 }
 418         }
 419
 420         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
 421         printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
 422                name);
 423         printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
 424         tpc->chipset = 0;
 425
 426 match:
 427         return 0;
 428 }
 429
 430 /*
 431  * TX and RX descriptors are 16 bytes. This causes problems with the cache
 432  * maintenance on CPUs where the cache-line size exceeds the size of these
 433  * descriptors. What will happen is that when the driver receives a packet
 434  * it will be immediately requeued for the hardware to reuse. The CPU will
 435  * therefore need to flush the cache-line containing the descriptor, which
 436  * will cause all other descriptors in the same cache-line to be flushed
 437  * along with it. If one of those descriptors had been written to by the
 438  * device those changes (and the associated packet) will be lost.
 439  *
 440  * To work around this, we make use of non-cached memory if available. If
 441  * descriptors are mapped uncached there's no need to manually flush them
 442  * or invalidate them.
 443  *
 444  * Note that this only applies to descriptors. The packet data buffers do
 445  * not have the same constraints since they are 1536 bytes large, so they
 446  * are unlikely to share cache-lines.
 447  */
 448 static void *rtl_alloc_descs(unsigned int num)
 449 {
 450         size_t size = num * RTL8169_DESC_SIZE;
 451
 452 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 453         return (void *)noncached_alloc(size, RTL8169_ALIGN);
 454 #else
 455         return memalign(RTL8169_ALIGN, size);
 456 #endif
 457 }
 458
 459 /*
 460  * Cache maintenance functions. These are simple wrappers around the more
 461  * general purpose flush_cache() and invalidate_dcache_range() functions.
 462  */
 463
 464 static void rtl_inval_rx_desc(struct RxDesc *desc)
 465 {
 466 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 467         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 468         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 469
 470         invalidate_dcache_range(start, end);
 471 #endif
 472 }
 473
 474 static void rtl_flush_rx_desc(struct RxDesc *desc)
 475 {
 476 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 477         flush_cache((unsigned long)desc, sizeof(*desc));
 478 #endif
 479 }
 480
 481 static void rtl_inval_tx_desc(struct TxDesc *desc)
 482 {
 483 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 484         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 485         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 486
 487         invalidate_dcache_range(start, end);
 488 #endif
 489 }
 490
 491 static void rtl_flush_tx_desc(struct TxDesc *desc)
 492 {
 493 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 494         flush_cache((unsigned long)desc, sizeof(*desc));
 495 #endif
 496 }
 497
 498 static void rtl_inval_buffer(void *buf, size_t size)
 499 {
 500         unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
 501         unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
 502
 503         invalidate_dcache_range(start, end);
 504 }
 505
 506 static void rtl_flush_buffer(void *buf, size_t size)
 507 {
 508         flush_cache((unsigned long)buf, size);
 509 }
 510
 511 /**************************************************************************
 512 RECV - Receive a frame
 513 ***************************************************************************/
 514 #ifdef CONFIG_DM_ETH
 515 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
 516                            uchar **packetp)
 517 #else
 518 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
 519                            uchar **packetp)
 520 #endif
 521 {
 522         /* return true if there's an ethernet packet ready to read */
 523         /* nic->packet should contain data on return */
 524         /* nic->packetlen should contain length of data */
 525         int cur_rx;
 526         int length = 0;
 527
 528 #ifdef DEBUG_RTL8169_RX
 529         printf ("%s\n", __FUNCTION__);
 530 #endif
 531         ioaddr = dev_iobase;
 532
 533         cur_rx = tpc->cur_rx;
 534
 535         rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
 536
 537         if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
 538                 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 539                         length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
 540                                                 status) & 0x00001FFF) - 4;
 541
 542                         rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
 543                         memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 544
 545                         if (cur_rx == NUM_RX_DESC - 1)
 546                                 tpc->RxDescArray[cur_rx].status =
 547                                         cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 548                         else
 549                                 tpc->RxDescArray[cur_rx].status =
 550                                         cpu_to_le32(OWNbit + RX_BUF_SIZE);
 551 #ifdef CONFIG_DM_ETH
 552                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 553                                 dm_pci_mem_to_phys(dev,
 554                                         (pci_addr_t)(unsigned long)
 555                                         tpc->RxBufferRing[cur_rx]));
 556 #else
 557                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 558                                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
 559                                 tpc->RxBufferRing[cur_rx]));
 560 #endif
 561                         rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
 562 #ifdef CONFIG_DM_ETH
 563                         *packetp = rxdata;
 564 #else
 565                         net_process_received_packet(rxdata, length);
 566 #endif
 567                 } else {
 568                         puts("Error Rx");
 569                         length = -EIO;
 570                 }
 571                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
 572                 tpc->cur_rx = cur_rx;
 573                 return length;
 574
 575         } else {
 576                 ushort sts = RTL_R8(IntrStatus);
 577                 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
 578                 udelay(100);    /* wait */
 579         }
 580         tpc->cur_rx = cur_rx;
 581         return (0);             /* initially as this is called to flush the input */
 582 }
 583
 584 #ifdef CONFIG_DM_ETH
 585 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 586 {
 587         struct rtl8169_private *priv = dev_get_priv(dev);
 588
 589         return rtl_recv_common(dev, priv->iobase, packetp);
 590 }
 591 #else
 592 static int rtl_recv(struct eth_device *dev)
 593 {
 594         return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
 595                                dev->iobase, NULL);
 596 }
 597 #endif /* nCONFIG_DM_ETH */
 598
 599 #define HZ 1000
 600 /**************************************************************************
 601 SEND - Transmit a frame
 602 ***************************************************************************/
 603 #ifdef CONFIG_DM_ETH
 604 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
 605                            void *packet, int length)
 606 #else
 607 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
 608                            void *packet, int length)
 609 #endif
 610 {
 611         /* send the packet to destination */
 612
 613         u32 to;
 614         u8 *ptxb;
 615         int entry = tpc->cur_tx % NUM_TX_DESC;
 616         u32 len = length;
 617         int ret;
 618
 619 #ifdef DEBUG_RTL8169_TX
 620         int stime = currticks();
 621         printf ("%s\n", __FUNCTION__);
 622         printf("sending %d bytes\n", len);
 623 #endif
 624
 625         ioaddr = dev_iobase;
 626
 627         /* point to the current txb incase multiple tx_rings are used */
 628         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
 629         memcpy(ptxb, (char *)packet, (int)length);
 630
 631         while (len < ETH_ZLEN)
 632                 ptxb[len++] = '\0';
 633
 634         rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
 635
 636         tpc->TxDescArray[entry].buf_Haddr = 0;
 637 #ifdef CONFIG_DM_ETH
 638         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 639                 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 640 #else
 641         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 642                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 643 #endif
 644         if (entry != (NUM_TX_DESC - 1)) {
 645                 tpc->TxDescArray[entry].status =
 646                         cpu_to_le32((OWNbit | FSbit | LSbit) |
 647                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 648         } else {
 649                 tpc->TxDescArray[entry].status =
 650                         cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
 651                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 652         }
 653         rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
 654         RTL_W8(TxPoll, 0x40);   /* set polling bit */
 655
 656         tpc->cur_tx++;
 657         to = currticks() + TX_TIMEOUT;
 658         do {
 659                 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
 660         } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
 661                                 && (currticks() < to)); /* wait */
 662
 663         if (currticks() >= to) {
 664 #ifdef DEBUG_RTL8169_TX
 665                 puts("tx timeout/error\n");
 666                 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 667 #endif
 668                 ret = -ETIMEDOUT;
 669         } else {
 670 #ifdef DEBUG_RTL8169_TX
 671                 puts("tx done\n");
 672 #endif
 673                 ret = 0;
 674         }
 675         /* Delay to make net console (nc) work properly */
 676         udelay(20);
 677         return ret;
 678 }
 679
 680 #ifdef CONFIG_DM_ETH
 681 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
 682 {
 683         struct rtl8169_private *priv = dev_get_priv(dev);
 684
 685         return rtl_send_common(dev, priv->iobase, packet, length);
 686 }
 687
 688 #else
 689 static int rtl_send(struct eth_device *dev, void *packet, int length)
 690 {
 691         return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
 692                                dev->iobase, packet, length);
 693 }
 694 #endif
 695
 696 static void rtl8169_set_rx_mode(void)
 697 {
 698         u32 mc_filter[2];       /* Multicast hash filter */
 699         int rx_mode;
 700         u32 tmp = 0;
 701
 702 #ifdef DEBUG_RTL8169
 703         printf ("%s\n", __FUNCTION__);
 704 #endif
 705
 706         /* IFF_ALLMULTI */
 707         /* Too many to filter perfectly -- accept all multicasts. */
 708         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
 709         mc_filter[1] = mc_filter[0] = 0xffffffff;
 710
 711         tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
 712                                    rtl_chip_info[tpc->chipset].RxConfigMask);
 713
 714         RTL_W32(RxConfig, tmp);
 715         RTL_W32(MAR0 + 0, mc_filter[0]);
 716         RTL_W32(MAR0 + 4, mc_filter[1]);
 717 }
 718
 719 #ifdef CONFIG_DM_ETH
 720 static void rtl8169_hw_start(struct udevice *dev)
 721 #else
 722 static void rtl8169_hw_start(pci_dev_t dev)
 723 #endif
 724 {
 725         u32 i;
 726
 727 #ifdef DEBUG_RTL8169
 728         int stime = currticks();
 729         printf ("%s\n", __FUNCTION__);
 730 #endif
 731
 732 #if 0
 733         /* Soft reset the chip. */
 734         RTL_W8(ChipCmd, CmdReset);
 735
 736         /* Check that the chip has finished the reset. */
 737         for (i = 1000; i > 0; i--) {
 738                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 739                         break;
 740                 else
 741                         udelay(10);
 742         }
 743 #endif
 744
 745         RTL_W8(Cfg9346, Cfg9346_Unlock);
 746
 747         /* RTL-8169sb/8110sb or previous version */
 748         if (tpc->chipset <= 5)
 749                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 750
 751         RTL_W8(EarlyTxThres, EarlyTxThld);
 752
 753         /* For gigabit rtl8169 */
 754         RTL_W16(RxMaxSize, RxPacketMaxSize);
 755
 756         /* Set Rx Config register */
 757         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
 758                                  rtl_chip_info[tpc->chipset].RxConfigMask);
 759         RTL_W32(RxConfig, i);
 760
 761         /* Set DMA burst size and Interframe Gap Time */
 762         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
 763                                 (InterFrameGap << TxInterFrameGapShift));
 764
 765
 766         tpc->cur_rx = 0;
 767
 768 #ifdef CONFIG_DM_ETH
 769         RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
 770                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 771 #else
 772         RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
 773                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 774 #endif
 775         RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
 776 #ifdef CONFIG_DM_ETH
 777         RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
 778                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 779 #else
 780         RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
 781                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 782 #endif
 783         RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
 784
 785         /* RTL-8169sc/8110sc or later version */
 786         if (tpc->chipset > 5)
 787                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 788
 789         RTL_W8(Cfg9346, Cfg9346_Lock);
 790         udelay(10);
 791
 792         RTL_W32(RxMissed, 0);
 793
 794         rtl8169_set_rx_mode();
 795
 796         /* no early-rx interrupts */
 797         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 798
 799 #ifdef DEBUG_RTL8169
 800         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 801 #endif
 802 }
 803
 804 #ifdef CONFIG_DM_ETH
 805 static void rtl8169_init_ring(struct udevice *dev)
 806 #else
 807 static void rtl8169_init_ring(pci_dev_t dev)
 808 #endif
 809 {
 810         int i;
 811
 812 #ifdef DEBUG_RTL8169
 813         int stime = currticks();
 814         printf ("%s\n", __FUNCTION__);
 815 #endif
 816
 817         tpc->cur_rx = 0;
 818         tpc->cur_tx = 0;
 819         tpc->dirty_tx = 0;
 820         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
 821         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
 822
 823         for (i = 0; i < NUM_TX_DESC; i++) {
 824                 tpc->Tx_skbuff[i] = &txb[i];
 825         }
 826
 827         for (i = 0; i < NUM_RX_DESC; i++) {
 828                 if (i == (NUM_RX_DESC - 1))
 829                         tpc->RxDescArray[i].status =
 830                                 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 831                 else
 832                         tpc->RxDescArray[i].status =
 833                                 cpu_to_le32(OWNbit + RX_BUF_SIZE);
 834
 835                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 836 #ifdef CONFIG_DM_ETH
 837                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
 838                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 839 #else
 840                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
 841                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 842 #endif
 843                 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
 844         }
 845
 846 #ifdef DEBUG_RTL8169
 847         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 848 #endif
 849 }
 850
 851 #ifdef CONFIG_DM_ETH
 852 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
 853                                  unsigned long dev_iobase)
 854 #else
 855 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
 856                                  unsigned long dev_iobase)
 857 #endif
 858 {
 859         int i;
 860
 861 #ifdef DEBUG_RTL8169
 862         int stime = currticks();
 863         printf ("%s\n", __FUNCTION__);
 864 #endif
 865
 866         ioaddr = dev_iobase;
 867
 868         rtl8169_init_ring(dev);
 869         rtl8169_hw_start(dev);
 870         /* Construct a perfect filter frame with the mac address as first match
 871          * and broadcast for all others */
 872         for (i = 0; i < 192; i++)
 873                 txb[i] = 0xFF;
 874
 875         txb[0] = enetaddr[0];
 876         txb[1] = enetaddr[1];
 877         txb[2] = enetaddr[2];
 878         txb[3] = enetaddr[3];
 879         txb[4] = enetaddr[4];
 880         txb[5] = enetaddr[5];
 881
 882 #ifdef DEBUG_RTL8169
 883         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 884 #endif
 885 }
 886
 887 #ifdef CONFIG_DM_ETH
 888 static int rtl8169_eth_start(struct udevice *dev)
 889 {
 890         struct eth_pdata *plat = dev_get_platdata(dev);
 891         struct rtl8169_private *priv = dev_get_priv(dev);
 892
 893         rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
 894
 895         return 0;
 896 }
 897 #else
 898 /**************************************************************************
 899 RESET - Finish setting up the ethernet interface
 900 ***************************************************************************/
 901 static int rtl_reset(struct eth_device *dev, bd_t *bis)
 902 {
 903         rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
 904                              dev->enetaddr, dev->iobase);
 905
 906         return 0;
 907 }
 908 #endif /* nCONFIG_DM_ETH */
 909
 910 static void rtl_halt_common(unsigned long dev_iobase)
 911 {
 912         int i;
 913
 914 #ifdef DEBUG_RTL8169
 915         printf ("%s\n", __FUNCTION__);
 916 #endif
 917
 918         ioaddr = dev_iobase;
 919
 920         /* Stop the chip's Tx and Rx DMA processes. */
 921         RTL_W8(ChipCmd, 0x00);
 922
 923         /* Disable interrupts by clearing the interrupt mask. */
 924         RTL_W16(IntrMask, 0x0000);
 925
 926         RTL_W32(RxMissed, 0);
 927
 928         for (i = 0; i < NUM_RX_DESC; i++) {
 929                 tpc->RxBufferRing[i] = NULL;
 930         }
 931 }
 932
 933 #ifdef CONFIG_DM_ETH
 934 void rtl8169_eth_stop(struct udevice *dev)
 935 {
 936         struct rtl8169_private *priv = dev_get_priv(dev);
 937
 938         rtl_halt_common(priv->iobase);
 939 }
 940 #else
 941 /**************************************************************************
 942 HALT - Turn off ethernet interface
 943 ***************************************************************************/
 944 static void rtl_halt(struct eth_device *dev)
 945 {
 946         rtl_halt_common(dev->iobase);
 947 }
 948 #endif
 949
 950 #ifdef CONFIG_DM_ETH
 951 static int rtl8169_write_hwaddr(struct udevice *dev)
 952 {
 953         struct eth_pdata *plat = dev_get_platdata(dev);
 954         unsigned int i;
 955
 956         RTL_W8(Cfg9346, Cfg9346_Unlock);
 957
 958         for (i = 0; i < MAC_ADDR_LEN; i++)
 959                 RTL_W8(MAC0 + i, plat->enetaddr[i]);
 960
 961         RTL_W8(Cfg9346, Cfg9346_Lock);
 962
 963         return 0;
 964 }
 965 #endif
 966
 967 /**************************************************************************
 968 INIT - Look for an adapter, this routine's visible to the outside
 969 ***************************************************************************/
 970
 971 #define board_found 1
 972 #define valid_link 0
 973 static int rtl_init(unsigned long dev_ioaddr, const char *name,
 974                     unsigned char *enetaddr)
 975 {
 976         static int board_idx = -1;
 977         int i, rc;
 978         int option = -1, Cap10_100 = 0, Cap1000 = 0;
 979
 980 #ifdef DEBUG_RTL8169
 981         printf ("%s\n", __FUNCTION__);
 982 #endif
 983         ioaddr = dev_ioaddr;
 984
 985         board_idx++;
 986
 987         /* point to private storage */
 988         tpc = &tpx;
 989
 990         rc = rtl8169_init_board(ioaddr, name);
 991         if (rc)
 992                 return rc;
 993
 994         /* Get MAC address.  FIXME: read EEPROM */
 995         for (i = 0; i < MAC_ADDR_LEN; i++)
 996                 enetaddr[i] = RTL_R8(MAC0 + i);
 997
 998 #ifdef DEBUG_RTL8169
 999         printf("chipset = %d\n", tpc->chipset);
1000         printf("MAC Address");
1001         for (i = 0; i < MAC_ADDR_LEN; i++)
1002                 printf(":%02x", enetaddr[i]);
1003         putc('\n');
1004 #endif
1005
1006 #ifdef DEBUG_RTL8169
1007         /* Print out some hardware info */
1008         printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
1009 #endif
1010
1011         /* if TBI is not endbled */
1012         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
1013                 int val = mdio_read(PHY_AUTO_NEGO_REG);
1014
1015                 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1016                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
1017                 if (option > 0) {
1018 #ifdef DEBUG_RTL8169
1019                         printf("%s: Force-mode Enabled.\n", name);
1020 #endif
1021                         Cap10_100 = 0, Cap1000 = 0;
1022                         switch (option) {
1023                         case _10_Half:
1024                                 Cap10_100 = PHY_Cap_10_Half;
1025                                 Cap1000 = PHY_Cap_Null;
1026                                 break;
1027                         case _10_Full:
1028                                 Cap10_100 = PHY_Cap_10_Full;
1029                                 Cap1000 = PHY_Cap_Null;
1030                                 break;
1031                         case _100_Half:
1032                                 Cap10_100 = PHY_Cap_100_Half;
1033                                 Cap1000 = PHY_Cap_Null;
1034                                 break;
1035                         case _100_Full:
1036                                 Cap10_100 = PHY_Cap_100_Full;
1037                                 Cap1000 = PHY_Cap_Null;
1038                                 break;
1039                         case _1000_Full:
1040                                 Cap10_100 = PHY_Cap_Null;
1041                                 Cap1000 = PHY_Cap_1000_Full;
1042                                 break;
1043                         default:
1044                                 break;
1045                         }
1046                         mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F));        /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1047                         mdio_write(PHY_1000_CTRL_REG, Cap1000);
1048                 } else {
1049 #ifdef DEBUG_RTL8169
1050                         printf("%s: Auto-negotiation Enabled.\n",
1051                                name);
1052 #endif
1053                         /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1054                         mdio_write(PHY_AUTO_NEGO_REG,
1055                                    PHY_Cap_10_Half | PHY_Cap_10_Full |
1056                                    PHY_Cap_100_Half | PHY_Cap_100_Full |
1057                                    (val & 0x1F));
1058
1059                         /* enable 1000 Full Mode */
1060                         mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
1061
1062                 }
1063
1064                 /* Enable auto-negotiation and restart auto-nigotiation */
1065                 mdio_write(PHY_CTRL_REG,
1066                            PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1067                 udelay(100);
1068
1069                 /* wait for auto-negotiation process */
1070                 for (i = 10000; i > 0; i--) {
1071                         /* check if auto-negotiation complete */
1072                         if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1073                                 udelay(100);
1074                                 option = RTL_R8(PHYstatus);
1075                                 if (option & _1000bpsF) {
1076 #ifdef DEBUG_RTL8169
1077                                         printf("%s: 1000Mbps Full-duplex operation.\n",
1078                                                name);
1079 #endif
1080                                 } else {
1081 #ifdef DEBUG_RTL8169
1082                                         printf("%s: %sMbps %s-duplex operation.\n",
1083                                                name,
1084                                                (option & _100bps) ? "100" :
1085                                                "10",
1086                                                (option & FullDup) ? "Full" :
1087                                                "Half");
1088 #endif
1089                                 }
1090                                 break;
1091                         } else {
1092                                 udelay(100);
1093                         }
1094                 }               /* end for-loop to wait for auto-negotiation process */
1095
1096         } else {
1097                 udelay(100);
1098 #ifdef DEBUG_RTL8169
1099                 printf
1100                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1101                      name,
1102                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1103 #endif
1104         }
1105
1106
1107         tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1108         if (!tpc->RxDescArray)
1109                 return -ENOMEM;
1110
1111         tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1112         if (!tpc->TxDescArray)
1113                 return -ENOMEM;
1114
1115         return 0;
1116 }
1117
1118 #ifndef CONFIG_DM_ETH
1119 int rtl8169_initialize(bd_t *bis)
1120 {
1121         pci_dev_t devno;
1122         int card_number = 0;
1123         struct eth_device *dev;
1124         u32 iobase;
1125         int idx=0;
1126
1127         while(1){
1128                 unsigned int region;
1129                 u16 device;
1130                 int err;
1131
1132                 /* Find RTL8169 */
1133                 if ((devno = pci_find_devices(supported, idx++)) < 0)
1134                         break;
1135
1136                 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1137                 switch (device) {
1138                 case 0x8168:
1139                         region = 2;
1140                         break;
1141
1142                 default:
1143                         region = 1;
1144                         break;
1145                 }
1146
1147                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
1148                 iobase &= ~0xf;
1149
1150                 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1151
1152                 dev = (struct eth_device *)malloc(sizeof *dev);
1153                 if (!dev) {
1154                         printf("Can not allocate memory of rtl8169\n");
1155                         break;
1156                 }
1157
1158                 memset(dev, 0, sizeof(*dev));
1159                 sprintf (dev->name, "RTL8169#%d", card_number);
1160
1161                 dev->priv = (void *)(unsigned long)devno;
1162                 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1163
1164                 dev->init = rtl_reset;
1165                 dev->halt = rtl_halt;
1166                 dev->send = rtl_send;
1167                 dev->recv = rtl_recv;
1168
1169                 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
1170                 if (err < 0) {
1171                         printf(pr_fmt("failed to initialize card: %d\n"), err);
1172                         free(dev);
1173                         continue;
1174                 }
1175
1176                 eth_register (dev);
1177
1178                 card_number++;
1179         }
1180         return card_number;
1181 }
1182 #endif
1183
1184 #ifdef CONFIG_DM_ETH
1185 static int rtl8169_eth_probe(struct udevice *dev)
1186 {
1187         struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1188         struct rtl8169_private *priv = dev_get_priv(dev);
1189         struct eth_pdata *plat = dev_get_platdata(dev);
1190         u32 iobase;
1191         int region;
1192         int ret;
1193
1194         debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1195         switch (pplat->device) {
1196         case 0x8168:
1197                 region = 2;
1198                 break;
1199         default:
1200                 region = 1;
1201                 break;
1202         }
1203         dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
1204         iobase &= ~0xf;
1205         priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
1206
1207         ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1208         if (ret < 0) {
1209                 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1210                 return ret;
1211         }
1212
1213         return 0;
1214 }
1215
1216 static const struct eth_ops rtl8169_eth_ops = {
1217         .start  = rtl8169_eth_start,
1218         .send   = rtl8169_eth_send,
1219         .recv   = rtl8169_eth_recv,
1220         .stop   = rtl8169_eth_stop,
1221         .write_hwaddr = rtl8169_write_hwaddr,
1222 };
1223
1224 static const struct udevice_id rtl8169_eth_ids[] = {
1225         { .compatible = "realtek,rtl8169" },
1226         { }
1227 };
1228
1229 U_BOOT_DRIVER(eth_rtl8169) = {
1230         .name   = "eth_rtl8169",
1231         .id     = UCLASS_ETH,
1232         .of_match = rtl8169_eth_ids,
1233         .probe  = rtl8169_eth_probe,
1234         .ops    = &rtl8169_eth_ops,
1235         .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1236         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1237 };
1238
1239 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
1240 #endif