drivers/net/rtl8169.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rtl8169.c : U-Boot driver for the RealTek RTL8169
   4  *
   5  * Masami Komiya (mkomiya@sonare.it)
   6  *
   7  * Most part is taken from r8169.c of etherboot
   8  *
   9  */
  10
  11 /**************************************************************************
  12 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
  13 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
  14 *
  15 *    Portions of this code based on:
  16 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
  17 *               for Linux kernel 2.4.x.
  18 *
  19 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
  20 *         See Linux Driver for full information
  21 *
  22 *    Linux Driver Version 1.27a, 10.02.2002
  23 *
  24 *    Thanks to:
  25 *       Jean Chen of RealTek Semiconductor Corp. for
  26 *       providing the evaluation NIC used to develop
  27 *       this driver.  RealTek's support for Etherboot
  28 *       is appreciated.
  29 *
  30 *    REVISION HISTORY:
  31 *    ================
  32 *
  33 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
  34 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
  35 *
  36 *    Indent Options: indent -kr -i8
  37 ***************************************************************************/
  38 /*
  39  * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
  40  * Modified to use le32_to_cpu and cpu_to_le32 properly
  41  */
  42 #include <common.h>
  43 #include <cpu_func.h>
  44 #include <dm.h>
  45 #include <errno.h>
  46 #include <malloc.h>
  47 #include <memalign.h>
  48 #include <net.h>
  49 #ifndef CONFIG_DM_ETH
  50 #include <netdev.h>
  51 #endif
  52 #include <asm/io.h>
  53 #include <pci.h>
  54
  55 #undef DEBUG_RTL8169
  56 #undef DEBUG_RTL8169_TX
  57 #undef DEBUG_RTL8169_RX
  58
  59 #define drv_version "v1.5"
  60 #define drv_date "01-17-2004"
  61
  62 static unsigned long ioaddr;
  63
  64 /* Condensed operations for readability. */
  65 #define currticks()     get_timer(0)
  66
  67 /* media options */
  68 #define MAX_UNITS 8
  69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  70
  71 /* MAC address length*/
  72 #define MAC_ADDR_LEN    6
  73
  74 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
  75 #define MAX_ETH_FRAME_SIZE      1536
  76
  77 #define TX_FIFO_THRESH 256      /* In bytes */
  78
  79 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
  80 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  83 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
  84 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  85
  86 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
  87 #ifdef CONFIG_SYS_RX_ETH_BUFFER
  88   #define NUM_RX_DESC   CONFIG_SYS_RX_ETH_BUFFER
  89 #else
  90   #define NUM_RX_DESC   4       /* Number of Rx descriptor registers */
  91 #endif
  92 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  93 #define RX_BUF_LEN      8192
  94
  95 #define RTL_MIN_IO_SIZE 0x80
  96 #define TX_TIMEOUT  (6*HZ)
  97
  98 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
  99 #define RTL_W8(reg, val8)       writeb((val8), ioaddr + (reg))
 100 #define RTL_W16(reg, val16)     writew((val16), ioaddr + (reg))
 101 #define RTL_W32(reg, val32)     writel((val32), ioaddr + (reg))
 102 #define RTL_R8(reg)             readb(ioaddr + (reg))
 103 #define RTL_R16(reg)            readw(ioaddr + (reg))
 104 #define RTL_R32(reg)            readl(ioaddr + (reg))
 105
 106 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
 107         (pci_addr_t)(unsigned long)a)
 108 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
 109         (phys_addr_t)a)
 110
 111 enum RTL8169_registers {
 112         MAC0 = 0,               /* Ethernet hardware address. */
 113         MAR0 = 8,               /* Multicast filter. */
 114         TxDescStartAddrLow = 0x20,
 115         TxDescStartAddrHigh = 0x24,
 116         TxHDescStartAddrLow = 0x28,
 117         TxHDescStartAddrHigh = 0x2c,
 118         FLASH = 0x30,
 119         ERSR = 0x36,
 120         ChipCmd = 0x37,
 121         TxPoll = 0x38,
 122         IntrMask = 0x3C,
 123         IntrStatus = 0x3E,
 124         TxConfig = 0x40,
 125         RxConfig = 0x44,
 126         RxMissed = 0x4C,
 127         Cfg9346 = 0x50,
 128         Config0 = 0x51,
 129         Config1 = 0x52,
 130         Config2 = 0x53,
 131         Config3 = 0x54,
 132         Config4 = 0x55,
 133         Config5 = 0x56,
 134         MultiIntr = 0x5C,
 135         PHYAR = 0x60,
 136         TBICSR = 0x64,
 137         TBI_ANAR = 0x68,
 138         TBI_LPAR = 0x6A,
 139         PHYstatus = 0x6C,
 140         RxMaxSize = 0xDA,
 141         CPlusCmd = 0xE0,
 142         RxDescStartAddrLow = 0xE4,
 143         RxDescStartAddrHigh = 0xE8,
 144         EarlyTxThres = 0xEC,
 145         FuncEvent = 0xF0,
 146         FuncEventMask = 0xF4,
 147         FuncPresetState = 0xF8,
 148         FuncForceEvent = 0xFC,
 149 };
 150
 151 enum RTL8169_register_content {
 152         /*InterruptStatusBits */
 153         SYSErr = 0x8000,
 154         PCSTimeout = 0x4000,
 155         SWInt = 0x0100,
 156         TxDescUnavail = 0x80,
 157         RxFIFOOver = 0x40,
 158         RxUnderrun = 0x20,
 159         RxOverflow = 0x10,
 160         TxErr = 0x08,
 161         TxOK = 0x04,
 162         RxErr = 0x02,
 163         RxOK = 0x01,
 164
 165         /*RxStatusDesc */
 166         RxRES = 0x00200000,
 167         RxCRC = 0x00080000,
 168         RxRUNT = 0x00100000,
 169         RxRWT = 0x00400000,
 170
 171         /*ChipCmdBits */
 172         CmdReset = 0x10,
 173         CmdRxEnb = 0x08,
 174         CmdTxEnb = 0x04,
 175         RxBufEmpty = 0x01,
 176
 177         /*Cfg9346Bits */
 178         Cfg9346_Lock = 0x00,
 179         Cfg9346_Unlock = 0xC0,
 180
 181         /*rx_mode_bits */
 182         AcceptErr = 0x20,
 183         AcceptRunt = 0x10,
 184         AcceptBroadcast = 0x08,
 185         AcceptMulticast = 0x04,
 186         AcceptMyPhys = 0x02,
 187         AcceptAllPhys = 0x01,
 188
 189         /*RxConfigBits */
 190         RxCfgFIFOShift = 13,
 191         RxCfgDMAShift = 8,
 192
 193         /*TxConfigBits */
 194         TxInterFrameGapShift = 24,
 195         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 196
 197         /*rtl8169_PHYstatus */
 198         TBI_Enable = 0x80,
 199         TxFlowCtrl = 0x40,
 200         RxFlowCtrl = 0x20,
 201         _1000bpsF = 0x10,
 202         _100bps = 0x08,
 203         _10bps = 0x04,
 204         LinkStatus = 0x02,
 205         FullDup = 0x01,
 206
 207         /*GIGABIT_PHY_registers */
 208         PHY_CTRL_REG = 0,
 209         PHY_STAT_REG = 1,
 210         PHY_AUTO_NEGO_REG = 4,
 211         PHY_1000_CTRL_REG = 9,
 212
 213         /*GIGABIT_PHY_REG_BIT */
 214         PHY_Restart_Auto_Nego = 0x0200,
 215         PHY_Enable_Auto_Nego = 0x1000,
 216
 217         /* PHY_STAT_REG = 1; */
 218         PHY_Auto_Nego_Comp = 0x0020,
 219
 220         /* PHY_AUTO_NEGO_REG = 4; */
 221         PHY_Cap_10_Half = 0x0020,
 222         PHY_Cap_10_Full = 0x0040,
 223         PHY_Cap_100_Half = 0x0080,
 224         PHY_Cap_100_Full = 0x0100,
 225
 226         /* PHY_1000_CTRL_REG = 9; */
 227         PHY_Cap_1000_Full = 0x0200,
 228
 229         PHY_Cap_Null = 0x0,
 230
 231         /*_MediaType*/
 232         _10_Half = 0x01,
 233         _10_Full = 0x02,
 234         _100_Half = 0x04,
 235         _100_Full = 0x08,
 236         _1000_Full = 0x10,
 237
 238         /*_TBICSRBit*/
 239         TBILinkOK = 0x02000000,
 240 };
 241
 242 static struct {
 243         const char *name;
 244         u8 version;             /* depend on RTL8169 docs */
 245         u32 RxConfigMask;       /* should clear the bits supported by this chip */
 246 } rtl_chip_info[] = {
 247         {"RTL-8169", 0x00, 0xff7e1880,},
 248         {"RTL-8169", 0x04, 0xff7e1880,},
 249         {"RTL-8169", 0x00, 0xff7e1880,},
 250         {"RTL-8169s/8110s",     0x02, 0xff7e1880,},
 251         {"RTL-8169s/8110s",     0x04, 0xff7e1880,},
 252         {"RTL-8169sb/8110sb",   0x10, 0xff7e1880,},
 253         {"RTL-8169sc/8110sc",   0x18, 0xff7e1880,},
 254         {"RTL-8168b/8111sb",    0x30, 0xff7e1880,},
 255         {"RTL-8168b/8111sb",    0x38, 0xff7e1880,},
 256         {"RTL-8168d/8111d",     0x28, 0xff7e1880,},
 257         {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
 258         {"RTL-8168/8111g",      0x4c, 0xff7e1880,},
 259         {"RTL-8101e",           0x34, 0xff7e1880,},
 260         {"RTL-8100e",           0x32, 0xff7e1880,},
 261         {"RTL-8168h/8111h",     0x54, 0xff7e1880,},
 262 };
 263
 264 enum _DescStatusBit {
 265         OWNbit = 0x80000000,
 266         EORbit = 0x40000000,
 267         FSbit = 0x20000000,
 268         LSbit = 0x10000000,
 269 };
 270
 271 struct TxDesc {
 272         u32 status;
 273         u32 vlan_tag;
 274         u32 buf_addr;
 275         u32 buf_Haddr;
 276 };
 277
 278 struct RxDesc {
 279         u32 status;
 280         u32 vlan_tag;
 281         u32 buf_addr;
 282         u32 buf_Haddr;
 283 };
 284
 285 static unsigned char rxdata[RX_BUF_LEN];
 286
 287 #define RTL8169_DESC_SIZE 16
 288
 289 #if ARCH_DMA_MINALIGN > 256
 290 #  define RTL8169_ALIGN ARCH_DMA_MINALIGN
 291 #else
 292 #  define RTL8169_ALIGN 256
 293 #endif
 294
 295 /*
 296  * Warn if the cache-line size is larger than the descriptor size. In such
 297  * cases the driver will likely fail because the CPU needs to flush the cache
 298  * when requeuing RX buffers, therefore descriptors written by the hardware
 299  * may be discarded.
 300  *
 301  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
 302  * the driver to allocate descriptors from a pool of non-cached memory.
 303  */
 304 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 305 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
 306         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
 307 #warning cache-line size is larger than descriptor size
 308 #endif
 309 #endif
 310
 311 /*
 312  * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
 313  * descriptors point to a part of this buffer.
 314  */
 315 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 316
 317 /*
 318  * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
 319  * descriptors point to a part of this buffer.
 320  */
 321 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 322
 323 struct rtl8169_private {
 324         ulong iobase;
 325         void *mmio_addr;        /* memory map physical address */
 326         int chipset;
 327         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
 328         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
 329         unsigned long dirty_tx;
 330         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
 331         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
 332         unsigned char *RxBufferRings;   /* Index of Rx Buffer  */
 333         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
 334         unsigned char *Tx_skbuff[NUM_TX_DESC];
 335 } tpx;
 336
 337 static struct rtl8169_private *tpc;
 338
 339 static const unsigned int rtl8169_rx_config =
 340     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 341
 342 static struct pci_device_id supported[] = {
 343         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
 344         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
 345         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
 346         {}
 347 };
 348
 349 void mdio_write(int RegAddr, int value)
 350 {
 351         int i;
 352
 353         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 354         udelay(1000);
 355
 356         for (i = 2000; i > 0; i--) {
 357                 /* Check if the RTL8169 has completed writing to the specified MII register */
 358                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
 359                         break;
 360                 } else {
 361                         udelay(100);
 362                 }
 363         }
 364 }
 365
 366 int mdio_read(int RegAddr)
 367 {
 368         int i, value = -1;
 369
 370         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 371         udelay(1000);
 372
 373         for (i = 2000; i > 0; i--) {
 374                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
 375                 if (RTL_R32(PHYAR) & 0x80000000) {
 376                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 377                         break;
 378                 } else {
 379                         udelay(100);
 380                 }
 381         }
 382         return value;
 383 }
 384
 385 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
 386 {
 387         int i;
 388         u32 tmp;
 389
 390 #ifdef DEBUG_RTL8169
 391         printf ("%s\n", __FUNCTION__);
 392 #endif
 393         ioaddr = dev_iobase;
 394
 395         /* Soft reset the chip. */
 396         RTL_W8(ChipCmd, CmdReset);
 397
 398         /* Check that the chip has finished the reset. */
 399         for (i = 1000; i > 0; i--)
 400                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 401                         break;
 402                 else
 403                         udelay(10);
 404
 405         /* identify chip attached to board */
 406         tmp = RTL_R32(TxConfig);
 407         tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
 408
 409         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
 410                 if (tmp == rtl_chip_info[i].version) {
 411                         tpc->chipset = i;
 412                         goto match;
 413                 }
 414         }
 415
 416         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
 417         printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
 418                name);
 419         printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
 420         tpc->chipset = 0;
 421
 422 match:
 423         return 0;
 424 }
 425
 426 /*
 427  * TX and RX descriptors are 16 bytes. This causes problems with the cache
 428  * maintenance on CPUs where the cache-line size exceeds the size of these
 429  * descriptors. What will happen is that when the driver receives a packet
 430  * it will be immediately requeued for the hardware to reuse. The CPU will
 431  * therefore need to flush the cache-line containing the descriptor, which
 432  * will cause all other descriptors in the same cache-line to be flushed
 433  * along with it. If one of those descriptors had been written to by the
 434  * device those changes (and the associated packet) will be lost.
 435  *
 436  * To work around this, we make use of non-cached memory if available. If
 437  * descriptors are mapped uncached there's no need to manually flush them
 438  * or invalidate them.
 439  *
 440  * Note that this only applies to descriptors. The packet data buffers do
 441  * not have the same constraints since they are 1536 bytes large, so they
 442  * are unlikely to share cache-lines.
 443  */
 444 static void *rtl_alloc_descs(unsigned int num)
 445 {
 446         size_t size = num * RTL8169_DESC_SIZE;
 447
 448 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 449         return (void *)noncached_alloc(size, RTL8169_ALIGN);
 450 #else
 451         return memalign(RTL8169_ALIGN, size);
 452 #endif
 453 }
 454
 455 /*
 456  * Cache maintenance functions. These are simple wrappers around the more
 457  * general purpose flush_cache() and invalidate_dcache_range() functions.
 458  */
 459
 460 static void rtl_inval_rx_desc(struct RxDesc *desc)
 461 {
 462 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 463         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 464         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 465
 466         invalidate_dcache_range(start, end);
 467 #endif
 468 }
 469
 470 static void rtl_flush_rx_desc(struct RxDesc *desc)
 471 {
 472 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 473         flush_cache((unsigned long)desc, sizeof(*desc));
 474 #endif
 475 }
 476
 477 static void rtl_inval_tx_desc(struct TxDesc *desc)
 478 {
 479 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 480         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 481         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 482
 483         invalidate_dcache_range(start, end);
 484 #endif
 485 }
 486
 487 static void rtl_flush_tx_desc(struct TxDesc *desc)
 488 {
 489 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 490         flush_cache((unsigned long)desc, sizeof(*desc));
 491 #endif
 492 }
 493
 494 static void rtl_inval_buffer(void *buf, size_t size)
 495 {
 496         unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
 497         unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
 498
 499         invalidate_dcache_range(start, end);
 500 }
 501
 502 static void rtl_flush_buffer(void *buf, size_t size)
 503 {
 504         flush_cache((unsigned long)buf, size);
 505 }
 506
 507 /**************************************************************************
 508 RECV - Receive a frame
 509 ***************************************************************************/
 510 #ifdef CONFIG_DM_ETH
 511 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
 512                            uchar **packetp)
 513 #else
 514 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
 515                            uchar **packetp)
 516 #endif
 517 {
 518         /* return true if there's an ethernet packet ready to read */
 519         /* nic->packet should contain data on return */
 520         /* nic->packetlen should contain length of data */
 521         int cur_rx;
 522         int length = 0;
 523
 524 #ifdef DEBUG_RTL8169_RX
 525         printf ("%s\n", __FUNCTION__);
 526 #endif
 527         ioaddr = dev_iobase;
 528
 529         cur_rx = tpc->cur_rx;
 530
 531         rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
 532
 533         if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
 534                 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 535                         length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
 536                                                 status) & 0x00001FFF) - 4;
 537
 538                         rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
 539                         memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 540
 541                         if (cur_rx == NUM_RX_DESC - 1)
 542                                 tpc->RxDescArray[cur_rx].status =
 543                                         cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 544                         else
 545                                 tpc->RxDescArray[cur_rx].status =
 546                                         cpu_to_le32(OWNbit + RX_BUF_SIZE);
 547 #ifdef CONFIG_DM_ETH
 548                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 549                                 dm_pci_mem_to_phys(dev,
 550                                         (pci_addr_t)(unsigned long)
 551                                         tpc->RxBufferRing[cur_rx]));
 552 #else
 553                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 554                                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
 555                                 tpc->RxBufferRing[cur_rx]));
 556 #endif
 557                         rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
 558 #ifdef CONFIG_DM_ETH
 559                         *packetp = rxdata;
 560 #else
 561                         net_process_received_packet(rxdata, length);
 562 #endif
 563                 } else {
 564                         puts("Error Rx");
 565                         length = -EIO;
 566                 }
 567                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
 568                 tpc->cur_rx = cur_rx;
 569                 return length;
 570
 571         } else {
 572                 ushort sts = RTL_R8(IntrStatus);
 573                 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
 574                 udelay(100);    /* wait */
 575         }
 576         tpc->cur_rx = cur_rx;
 577         return (0);             /* initially as this is called to flush the input */
 578 }
 579
 580 #ifdef CONFIG_DM_ETH
 581 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 582 {
 583         struct rtl8169_private *priv = dev_get_priv(dev);
 584
 585         return rtl_recv_common(dev, priv->iobase, packetp);
 586 }
 587 #else
 588 static int rtl_recv(struct eth_device *dev)
 589 {
 590         return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
 591                                dev->iobase, NULL);
 592 }
 593 #endif /* nCONFIG_DM_ETH */
 594
 595 #define HZ 1000
 596 /**************************************************************************
 597 SEND - Transmit a frame
 598 ***************************************************************************/
 599 #ifdef CONFIG_DM_ETH
 600 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
 601                            void *packet, int length)
 602 #else
 603 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
 604                            void *packet, int length)
 605 #endif
 606 {
 607         /* send the packet to destination */
 608
 609         u32 to;
 610         u8 *ptxb;
 611         int entry = tpc->cur_tx % NUM_TX_DESC;
 612         u32 len = length;
 613         int ret;
 614
 615 #ifdef DEBUG_RTL8169_TX
 616         int stime = currticks();
 617         printf ("%s\n", __FUNCTION__);
 618         printf("sending %d bytes\n", len);
 619 #endif
 620
 621         ioaddr = dev_iobase;
 622
 623         /* point to the current txb incase multiple tx_rings are used */
 624         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
 625         memcpy(ptxb, (char *)packet, (int)length);
 626
 627         while (len < ETH_ZLEN)
 628                 ptxb[len++] = '\0';
 629
 630         rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
 631
 632         tpc->TxDescArray[entry].buf_Haddr = 0;
 633 #ifdef CONFIG_DM_ETH
 634         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 635                 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 636 #else
 637         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 638                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 639 #endif
 640         if (entry != (NUM_TX_DESC - 1)) {
 641                 tpc->TxDescArray[entry].status =
 642                         cpu_to_le32((OWNbit | FSbit | LSbit) |
 643                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 644         } else {
 645                 tpc->TxDescArray[entry].status =
 646                         cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
 647                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 648         }
 649         rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
 650         RTL_W8(TxPoll, 0x40);   /* set polling bit */
 651
 652         tpc->cur_tx++;
 653         to = currticks() + TX_TIMEOUT;
 654         do {
 655                 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
 656         } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
 657                                 && (currticks() < to)); /* wait */
 658
 659         if (currticks() >= to) {
 660 #ifdef DEBUG_RTL8169_TX
 661                 puts("tx timeout/error\n");
 662                 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 663 #endif
 664                 ret = -ETIMEDOUT;
 665         } else {
 666 #ifdef DEBUG_RTL8169_TX
 667                 puts("tx done\n");
 668 #endif
 669                 ret = 0;
 670         }
 671         /* Delay to make net console (nc) work properly */
 672         udelay(20);
 673         return ret;
 674 }
 675
 676 #ifdef CONFIG_DM_ETH
 677 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
 678 {
 679         struct rtl8169_private *priv = dev_get_priv(dev);
 680
 681         return rtl_send_common(dev, priv->iobase, packet, length);
 682 }
 683
 684 #else
 685 static int rtl_send(struct eth_device *dev, void *packet, int length)
 686 {
 687         return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
 688                                dev->iobase, packet, length);
 689 }
 690 #endif
 691
 692 static void rtl8169_set_rx_mode(void)
 693 {
 694         u32 mc_filter[2];       /* Multicast hash filter */
 695         int rx_mode;
 696         u32 tmp = 0;
 697
 698 #ifdef DEBUG_RTL8169
 699         printf ("%s\n", __FUNCTION__);
 700 #endif
 701
 702         /* IFF_ALLMULTI */
 703         /* Too many to filter perfectly -- accept all multicasts. */
 704         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
 705         mc_filter[1] = mc_filter[0] = 0xffffffff;
 706
 707         tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
 708                                    rtl_chip_info[tpc->chipset].RxConfigMask);
 709
 710         RTL_W32(RxConfig, tmp);
 711         RTL_W32(MAR0 + 0, mc_filter[0]);
 712         RTL_W32(MAR0 + 4, mc_filter[1]);
 713 }
 714
 715 #ifdef CONFIG_DM_ETH
 716 static void rtl8169_hw_start(struct udevice *dev)
 717 #else
 718 static void rtl8169_hw_start(pci_dev_t dev)
 719 #endif
 720 {
 721         u32 i;
 722
 723 #ifdef DEBUG_RTL8169
 724         int stime = currticks();
 725         printf ("%s\n", __FUNCTION__);
 726 #endif
 727
 728 #if 0
 729         /* Soft reset the chip. */
 730         RTL_W8(ChipCmd, CmdReset);
 731
 732         /* Check that the chip has finished the reset. */
 733         for (i = 1000; i > 0; i--) {
 734                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 735                         break;
 736                 else
 737                         udelay(10);
 738         }
 739 #endif
 740
 741         RTL_W8(Cfg9346, Cfg9346_Unlock);
 742
 743         /* RTL-8169sb/8110sb or previous version */
 744         if (tpc->chipset <= 5)
 745                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 746
 747         RTL_W8(EarlyTxThres, EarlyTxThld);
 748
 749         /* For gigabit rtl8169 */
 750         RTL_W16(RxMaxSize, RxPacketMaxSize);
 751
 752         /* Set Rx Config register */
 753         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
 754                                  rtl_chip_info[tpc->chipset].RxConfigMask);
 755         RTL_W32(RxConfig, i);
 756
 757         /* Set DMA burst size and Interframe Gap Time */
 758         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
 759                                 (InterFrameGap << TxInterFrameGapShift));
 760
 761
 762         tpc->cur_rx = 0;
 763
 764 #ifdef CONFIG_DM_ETH
 765         RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
 766                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 767 #else
 768         RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
 769                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 770 #endif
 771         RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
 772 #ifdef CONFIG_DM_ETH
 773         RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
 774                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 775 #else
 776         RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
 777                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 778 #endif
 779         RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
 780
 781         /* RTL-8169sc/8110sc or later version */
 782         if (tpc->chipset > 5)
 783                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 784
 785         RTL_W8(Cfg9346, Cfg9346_Lock);
 786         udelay(10);
 787
 788         RTL_W32(RxMissed, 0);
 789
 790         rtl8169_set_rx_mode();
 791
 792         /* no early-rx interrupts */
 793         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 794
 795 #ifdef DEBUG_RTL8169
 796         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 797 #endif
 798 }
 799
 800 #ifdef CONFIG_DM_ETH
 801 static void rtl8169_init_ring(struct udevice *dev)
 802 #else
 803 static void rtl8169_init_ring(pci_dev_t dev)
 804 #endif
 805 {
 806         int i;
 807
 808 #ifdef DEBUG_RTL8169
 809         int stime = currticks();
 810         printf ("%s\n", __FUNCTION__);
 811 #endif
 812
 813         tpc->cur_rx = 0;
 814         tpc->cur_tx = 0;
 815         tpc->dirty_tx = 0;
 816         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
 817         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
 818
 819         for (i = 0; i < NUM_TX_DESC; i++) {
 820                 tpc->Tx_skbuff[i] = &txb[i];
 821         }
 822
 823         for (i = 0; i < NUM_RX_DESC; i++) {
 824                 if (i == (NUM_RX_DESC - 1))
 825                         tpc->RxDescArray[i].status =
 826                                 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 827                 else
 828                         tpc->RxDescArray[i].status =
 829                                 cpu_to_le32(OWNbit + RX_BUF_SIZE);
 830
 831                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 832 #ifdef CONFIG_DM_ETH
 833                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
 834                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 835 #else
 836                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
 837                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 838 #endif
 839                 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
 840         }
 841
 842 #ifdef DEBUG_RTL8169
 843         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 844 #endif
 845 }
 846
 847 #ifdef CONFIG_DM_ETH
 848 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
 849                                  unsigned long dev_iobase)
 850 #else
 851 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
 852                                  unsigned long dev_iobase)
 853 #endif
 854 {
 855         int i;
 856
 857 #ifdef DEBUG_RTL8169
 858         int stime = currticks();
 859         printf ("%s\n", __FUNCTION__);
 860 #endif
 861
 862         ioaddr = dev_iobase;
 863
 864         rtl8169_init_ring(dev);
 865         rtl8169_hw_start(dev);
 866         /* Construct a perfect filter frame with the mac address as first match
 867          * and broadcast for all others */
 868         for (i = 0; i < 192; i++)
 869                 txb[i] = 0xFF;
 870
 871         txb[0] = enetaddr[0];
 872         txb[1] = enetaddr[1];
 873         txb[2] = enetaddr[2];
 874         txb[3] = enetaddr[3];
 875         txb[4] = enetaddr[4];
 876         txb[5] = enetaddr[5];
 877
 878 #ifdef DEBUG_RTL8169
 879         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 880 #endif
 881 }
 882
 883 #ifdef CONFIG_DM_ETH
 884 static int rtl8169_eth_start(struct udevice *dev)
 885 {
 886         struct eth_pdata *plat = dev_get_platdata(dev);
 887         struct rtl8169_private *priv = dev_get_priv(dev);
 888
 889         rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
 890
 891         return 0;
 892 }
 893 #else
 894 /**************************************************************************
 895 RESET - Finish setting up the ethernet interface
 896 ***************************************************************************/
 897 static int rtl_reset(struct eth_device *dev, bd_t *bis)
 898 {
 899         rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
 900                              dev->enetaddr, dev->iobase);
 901
 902         return 0;
 903 }
 904 #endif /* nCONFIG_DM_ETH */
 905
 906 static void rtl_halt_common(unsigned long dev_iobase)
 907 {
 908         int i;
 909
 910 #ifdef DEBUG_RTL8169
 911         printf ("%s\n", __FUNCTION__);
 912 #endif
 913
 914         ioaddr = dev_iobase;
 915
 916         /* Stop the chip's Tx and Rx DMA processes. */
 917         RTL_W8(ChipCmd, 0x00);
 918
 919         /* Disable interrupts by clearing the interrupt mask. */
 920         RTL_W16(IntrMask, 0x0000);
 921
 922         RTL_W32(RxMissed, 0);
 923
 924         for (i = 0; i < NUM_RX_DESC; i++) {
 925                 tpc->RxBufferRing[i] = NULL;
 926         }
 927 }
 928
 929 #ifdef CONFIG_DM_ETH
 930 void rtl8169_eth_stop(struct udevice *dev)
 931 {
 932         struct rtl8169_private *priv = dev_get_priv(dev);
 933
 934         rtl_halt_common(priv->iobase);
 935 }
 936 #else
 937 /**************************************************************************
 938 HALT - Turn off ethernet interface
 939 ***************************************************************************/
 940 static void rtl_halt(struct eth_device *dev)
 941 {
 942         rtl_halt_common(dev->iobase);
 943 }
 944 #endif
 945
 946 #ifdef CONFIG_DM_ETH
 947 static int rtl8169_write_hwaddr(struct udevice *dev)
 948 {
 949         struct eth_pdata *plat = dev_get_platdata(dev);
 950         unsigned int i;
 951
 952         RTL_W8(Cfg9346, Cfg9346_Unlock);
 953
 954         for (i = 0; i < MAC_ADDR_LEN; i++)
 955                 RTL_W8(MAC0 + i, plat->enetaddr[i]);
 956
 957         RTL_W8(Cfg9346, Cfg9346_Lock);
 958
 959         return 0;
 960 }
 961 #endif
 962
 963 /**************************************************************************
 964 INIT - Look for an adapter, this routine's visible to the outside
 965 ***************************************************************************/
 966
 967 #define board_found 1
 968 #define valid_link 0
 969 static int rtl_init(unsigned long dev_ioaddr, const char *name,
 970                     unsigned char *enetaddr)
 971 {
 972         static int board_idx = -1;
 973         int i, rc;
 974         int option = -1, Cap10_100 = 0, Cap1000 = 0;
 975
 976 #ifdef DEBUG_RTL8169
 977         printf ("%s\n", __FUNCTION__);
 978 #endif
 979         ioaddr = dev_ioaddr;
 980
 981         board_idx++;
 982
 983         /* point to private storage */
 984         tpc = &tpx;
 985
 986         rc = rtl8169_init_board(ioaddr, name);
 987         if (rc)
 988                 return rc;
 989
 990         /* Get MAC address.  FIXME: read EEPROM */
 991         for (i = 0; i < MAC_ADDR_LEN; i++)
 992                 enetaddr[i] = RTL_R8(MAC0 + i);
 993
 994 #ifdef DEBUG_RTL8169
 995         printf("chipset = %d\n", tpc->chipset);
 996         printf("MAC Address");
 997         for (i = 0; i < MAC_ADDR_LEN; i++)
 998                 printf(":%02x", enetaddr[i]);
 999         putc('\n');
1000 #endif
1001
1002 #ifdef DEBUG_RTL8169
1003         /* Print out some hardware info */
1004         printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
1005 #endif
1006
1007         /* if TBI is not endbled */
1008         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
1009                 int val = mdio_read(PHY_AUTO_NEGO_REG);
1010
1011                 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1012                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
1013                 if (option > 0) {
1014 #ifdef DEBUG_RTL8169
1015                         printf("%s: Force-mode Enabled.\n", name);
1016 #endif
1017                         Cap10_100 = 0, Cap1000 = 0;
1018                         switch (option) {
1019                         case _10_Half:
1020                                 Cap10_100 = PHY_Cap_10_Half;
1021                                 Cap1000 = PHY_Cap_Null;
1022                                 break;
1023                         case _10_Full:
1024                                 Cap10_100 = PHY_Cap_10_Full;
1025                                 Cap1000 = PHY_Cap_Null;
1026                                 break;
1027                         case _100_Half:
1028                                 Cap10_100 = PHY_Cap_100_Half;
1029                                 Cap1000 = PHY_Cap_Null;
1030                                 break;
1031                         case _100_Full:
1032                                 Cap10_100 = PHY_Cap_100_Full;
1033                                 Cap1000 = PHY_Cap_Null;
1034                                 break;
1035                         case _1000_Full:
1036                                 Cap10_100 = PHY_Cap_Null;
1037                                 Cap1000 = PHY_Cap_1000_Full;
1038                                 break;
1039                         default:
1040                                 break;
1041                         }
1042                         mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F));        /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1043                         mdio_write(PHY_1000_CTRL_REG, Cap1000);
1044                 } else {
1045 #ifdef DEBUG_RTL8169
1046                         printf("%s: Auto-negotiation Enabled.\n",
1047                                name);
1048 #endif
1049                         /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1050                         mdio_write(PHY_AUTO_NEGO_REG,
1051                                    PHY_Cap_10_Half | PHY_Cap_10_Full |
1052                                    PHY_Cap_100_Half | PHY_Cap_100_Full |
1053                                    (val & 0x1F));
1054
1055                         /* enable 1000 Full Mode */
1056                         mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
1057
1058                 }
1059
1060                 /* Enable auto-negotiation and restart auto-nigotiation */
1061                 mdio_write(PHY_CTRL_REG,
1062                            PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1063                 udelay(100);
1064
1065                 /* wait for auto-negotiation process */
1066                 for (i = 10000; i > 0; i--) {
1067                         /* check if auto-negotiation complete */
1068                         if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1069                                 udelay(100);
1070                                 option = RTL_R8(PHYstatus);
1071                                 if (option & _1000bpsF) {
1072 #ifdef DEBUG_RTL8169
1073                                         printf("%s: 1000Mbps Full-duplex operation.\n",
1074                                                name);
1075 #endif
1076                                 } else {
1077 #ifdef DEBUG_RTL8169
1078                                         printf("%s: %sMbps %s-duplex operation.\n",
1079                                                name,
1080                                                (option & _100bps) ? "100" :
1081                                                "10",
1082                                                (option & FullDup) ? "Full" :
1083                                                "Half");
1084 #endif
1085                                 }
1086                                 break;
1087                         } else {
1088                                 udelay(100);
1089                         }
1090                 }               /* end for-loop to wait for auto-negotiation process */
1091
1092         } else {
1093                 udelay(100);
1094 #ifdef DEBUG_RTL8169
1095                 printf
1096                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1097                      name,
1098                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1099 #endif
1100         }
1101
1102
1103         tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1104         if (!tpc->RxDescArray)
1105                 return -ENOMEM;
1106
1107         tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1108         if (!tpc->TxDescArray)
1109                 return -ENOMEM;
1110
1111         return 0;
1112 }
1113
1114 #ifndef CONFIG_DM_ETH
1115 int rtl8169_initialize(bd_t *bis)
1116 {
1117         pci_dev_t devno;
1118         int card_number = 0;
1119         struct eth_device *dev;
1120         u32 iobase;
1121         int idx=0;
1122
1123         while(1){
1124                 unsigned int region;
1125                 u16 device;
1126                 int err;
1127
1128                 /* Find RTL8169 */
1129                 if ((devno = pci_find_devices(supported, idx++)) < 0)
1130                         break;
1131
1132                 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1133                 switch (device) {
1134                 case 0x8168:
1135                         region = 2;
1136                         break;
1137
1138                 default:
1139                         region = 1;
1140                         break;
1141                 }
1142
1143                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
1144                 iobase &= ~0xf;
1145
1146                 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1147
1148                 dev = (struct eth_device *)malloc(sizeof *dev);
1149                 if (!dev) {
1150                         printf("Can not allocate memory of rtl8169\n");
1151                         break;
1152                 }
1153
1154                 memset(dev, 0, sizeof(*dev));
1155                 sprintf (dev->name, "RTL8169#%d", card_number);
1156
1157                 dev->priv = (void *)(unsigned long)devno;
1158                 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1159
1160                 dev->init = rtl_reset;
1161                 dev->halt = rtl_halt;
1162                 dev->send = rtl_send;
1163                 dev->recv = rtl_recv;
1164
1165                 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
1166                 if (err < 0) {
1167                         printf(pr_fmt("failed to initialize card: %d\n"), err);
1168                         free(dev);
1169                         continue;
1170                 }
1171
1172                 eth_register (dev);
1173
1174                 card_number++;
1175         }
1176         return card_number;
1177 }
1178 #endif
1179
1180 #ifdef CONFIG_DM_ETH
1181 static int rtl8169_eth_probe(struct udevice *dev)
1182 {
1183         struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1184         struct rtl8169_private *priv = dev_get_priv(dev);
1185         struct eth_pdata *plat = dev_get_platdata(dev);
1186         u32 iobase;
1187         int region;
1188         int ret;
1189
1190         debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1191         switch (pplat->device) {
1192         case 0x8168:
1193                 region = 2;
1194                 break;
1195         default:
1196                 region = 1;
1197                 break;
1198         }
1199         dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
1200         iobase &= ~0xf;
1201         priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
1202
1203         ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1204         if (ret < 0) {
1205                 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1206                 return ret;
1207         }
1208
1209         return 0;
1210 }
1211
1212 static const struct eth_ops rtl8169_eth_ops = {
1213         .start  = rtl8169_eth_start,
1214         .send   = rtl8169_eth_send,
1215         .recv   = rtl8169_eth_recv,
1216         .stop   = rtl8169_eth_stop,
1217         .write_hwaddr = rtl8169_write_hwaddr,
1218 };
1219
1220 static const struct udevice_id rtl8169_eth_ids[] = {
1221         { .compatible = "realtek,rtl8169" },
1222         { }
1223 };
1224
1225 U_BOOT_DRIVER(eth_rtl8169) = {
1226         .name   = "eth_rtl8169",
1227         .id     = UCLASS_ETH,
1228         .of_match = rtl8169_eth_ids,
1229         .probe  = rtl8169_eth_probe,
1230         .ops    = &rtl8169_eth_ops,
1231         .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1232         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1233 };
1234
1235 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
1236 #endif