1 // SPDX-License-Identifier: GPL-2.0+
4 * This file is driver for Renesas Ethernet AVB.
6 * Copyright (C) 2015-2017 Renesas Electronics Corporation
8 * Based on the SuperH Ethernet driver.
17 #include <linux/mii.h>
23 #define RAVB_REG_CCC 0x000
24 #define RAVB_REG_DBAT 0x004
25 #define RAVB_REG_CSR 0x00C
26 #define RAVB_REG_APSR 0x08C
27 #define RAVB_REG_RCR 0x090
28 #define RAVB_REG_TGC 0x300
29 #define RAVB_REG_TCCR 0x304
30 #define RAVB_REG_RIC0 0x360
31 #define RAVB_REG_RIC1 0x368
32 #define RAVB_REG_RIC2 0x370
33 #define RAVB_REG_TIC 0x378
34 #define RAVB_REG_ECMR 0x500
35 #define RAVB_REG_RFLR 0x508
36 #define RAVB_REG_ECSIPR 0x518
37 #define RAVB_REG_PIR 0x520
38 #define RAVB_REG_GECMR 0x5b0
39 #define RAVB_REG_MAHR 0x5c0
40 #define RAVB_REG_MALR 0x5c8
42 #define CCC_OPC_CONFIG BIT(0)
43 #define CCC_OPC_OPERATION BIT(1)
44 #define CCC_BOC BIT(20)
46 #define CSR_OPS 0x0000000F
47 #define CSR_OPS_CONFIG BIT(1)
49 #define APSR_TDM BIT(14)
51 #define TCCR_TSRQ0 BIT(0)
53 #define RFLR_RFL_MIN 0x05EE
55 #define PIR_MDI BIT(3)
56 #define PIR_MDO BIT(2)
57 #define PIR_MMD BIT(1)
58 #define PIR_MDC BIT(0)
60 #define ECMR_TRCCM BIT(26)
61 #define ECMR_RZPF BIT(20)
62 #define ECMR_PFR BIT(18)
63 #define ECMR_RXF BIT(17)
64 #define ECMR_RE BIT(6)
65 #define ECMR_TE BIT(5)
66 #define ECMR_DM BIT(1)
67 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
70 #define RAVB_NUM_BASE_DESC 16
71 #define RAVB_NUM_TX_DESC 8
72 #define RAVB_NUM_RX_DESC 8
74 #define RAVB_TX_QUEUE_OFFSET 0
75 #define RAVB_RX_QUEUE_OFFSET 4
77 #define RAVB_DESC_DT(n) ((n) << 28)
78 #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
79 #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
80 #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
81 #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
82 #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
83 #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
85 #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
86 #define RAVB_DESC_DS_MASK 0xfff
88 #define RAVB_RX_DESC_MSC_MC BIT(23)
89 #define RAVB_RX_DESC_MSC_CEEF BIT(22)
90 #define RAVB_RX_DESC_MSC_CRL BIT(21)
91 #define RAVB_RX_DESC_MSC_FRE BIT(20)
92 #define RAVB_RX_DESC_MSC_RTLF BIT(19)
93 #define RAVB_RX_DESC_MSC_RTSF BIT(18)
94 #define RAVB_RX_DESC_MSC_RFE BIT(17)
95 #define RAVB_RX_DESC_MSC_CRC BIT(16)
96 #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
98 #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
99 (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
100 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
102 #define RAVB_TX_TIMEOUT_MS 1000
110 struct ravb_desc data;
111 struct ravb_desc link;
113 u8 packet[PKTSIZE_ALIGN];
117 struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
118 struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
119 struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
123 struct phy_device *phydev;
125 void __iomem *iobase;
127 struct gpio_desc reset_gpio;
130 static inline void ravb_flush_dcache(u32 addr, u32 len)
132 flush_dcache_range(addr, addr + len);
135 static inline void ravb_invalidate_dcache(u32 addr, u32 len)
137 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
138 u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
139 invalidate_dcache_range(start, end);
142 static int ravb_send(struct udevice *dev, void *packet, int len)
144 struct ravb_priv *eth = dev_get_priv(dev);
145 struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx];
148 /* Update TX descriptor */
149 ravb_flush_dcache((uintptr_t)packet, len);
150 memset(desc, 0x0, sizeof(*desc));
151 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
152 desc->dptr = (uintptr_t)packet;
153 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
155 /* Restart the transmitter if disabled */
156 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
157 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
159 /* Wait until packet is transmitted */
160 start = get_timer(0);
161 while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
162 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
163 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
168 if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
171 eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
175 static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
177 struct ravb_priv *eth = dev_get_priv(dev);
178 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
182 /* Check if the rx descriptor is ready */
183 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
184 if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
187 /* Check for errors */
188 if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
189 desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
193 len = desc->data.ctrl & RAVB_DESC_DS_MASK;
194 packet = (u8 *)(uintptr_t)desc->data.dptr;
195 ravb_invalidate_dcache((uintptr_t)packet, len);
201 static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
203 struct ravb_priv *eth = dev_get_priv(dev);
204 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
206 /* Make current descriptor available again */
207 desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
208 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
210 /* Point to the next descriptor */
211 eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
212 desc = ð->rx_desc[eth->rx_desc_idx];
213 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
218 static int ravb_reset(struct udevice *dev)
220 struct ravb_priv *eth = dev_get_priv(dev);
222 /* Set config mode */
223 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
225 /* Check the operating mode is changed to the config mode. */
226 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
227 CSR_OPS_CONFIG, true, 100, true);
230 static void ravb_base_desc_init(struct ravb_priv *eth)
232 const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
235 /* Initialize all descriptors */
236 memset(eth->base_desc, 0x0, desc_size);
238 for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
239 eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
241 ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
243 /* Register the descriptor base address table */
244 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
247 static void ravb_tx_desc_init(struct ravb_priv *eth)
249 const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
252 /* Initialize all descriptors */
253 memset(eth->tx_desc, 0x0, desc_size);
254 eth->tx_desc_idx = 0;
256 for (i = 0; i < RAVB_NUM_TX_DESC; i++)
257 eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
259 /* Mark the end of the descriptors */
260 eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
261 eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
262 ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
264 /* Point the controller to the TX descriptor list. */
265 eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
266 eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
267 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET],
268 sizeof(struct ravb_desc));
271 static void ravb_rx_desc_init(struct ravb_priv *eth)
273 const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
276 /* Initialize all descriptors */
277 memset(eth->rx_desc, 0x0, desc_size);
278 eth->rx_desc_idx = 0;
280 for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
281 eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
282 RAVB_DESC_DS(PKTSIZE_ALIGN);
283 eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
285 eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
286 eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1];
289 /* Mark the end of the descriptors */
290 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
291 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
292 ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
294 /* Point the controller to the rx descriptor list */
295 eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
296 eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
297 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET],
298 sizeof(struct ravb_desc));
301 static int ravb_phy_config(struct udevice *dev)
303 struct ravb_priv *eth = dev_get_priv(dev);
304 struct eth_pdata *pdata = dev_get_platdata(dev);
305 struct phy_device *phydev;
306 int mask = 0xffffffff, reg;
308 if (dm_gpio_is_valid(ð->reset_gpio)) {
309 dm_gpio_set_value(ð->reset_gpio, 1);
311 dm_gpio_set_value(ð->reset_gpio, 0);
315 phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
319 phy_connect_dev(phydev, dev);
321 eth->phydev = phydev;
323 phydev->supported &= SUPPORTED_100baseT_Full |
324 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
325 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
326 SUPPORTED_Asym_Pause;
328 if (pdata->max_speed != 1000) {
329 phydev->supported &= ~SUPPORTED_1000baseT_Full;
330 reg = phy_read(phydev, -1, MII_CTRL1000);
331 reg &= ~(BIT(9) | BIT(8));
332 phy_write(phydev, -1, MII_CTRL1000, reg);
340 /* Set Mac address */
341 static int ravb_write_hwaddr(struct udevice *dev)
343 struct ravb_priv *eth = dev_get_priv(dev);
344 struct eth_pdata *pdata = dev_get_platdata(dev);
345 unsigned char *mac = pdata->enetaddr;
347 writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
348 eth->iobase + RAVB_REG_MAHR);
350 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
355 /* E-MAC init function */
356 static int ravb_mac_init(struct ravb_priv *eth)
358 /* Disable MAC Interrupt */
359 writel(0, eth->iobase + RAVB_REG_ECSIPR);
361 /* Recv frame limit set register */
362 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
367 /* AVB-DMAC init function */
368 static int ravb_dmac_init(struct udevice *dev)
370 struct ravb_priv *eth = dev_get_priv(dev);
371 struct eth_pdata *pdata = dev_get_platdata(dev);
374 /* Set CONFIG mode */
375 ret = ravb_reset(dev);
379 /* Disable all interrupts */
380 writel(0, eth->iobase + RAVB_REG_RIC0);
381 writel(0, eth->iobase + RAVB_REG_RIC1);
382 writel(0, eth->iobase + RAVB_REG_RIC2);
383 writel(0, eth->iobase + RAVB_REG_TIC);
385 /* Set little endian */
386 clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
389 writel(0x18000001, eth->iobase + RAVB_REG_RCR);
392 writel(0x00222210, eth->iobase + RAVB_REG_TGC);
394 /* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
395 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||
396 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
399 if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
400 (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
401 writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
406 static int ravb_config(struct udevice *dev)
408 struct ravb_priv *eth = dev_get_priv(dev);
409 struct phy_device *phy = eth->phydev;
410 u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
413 /* Configure AVB-DMAC register */
416 /* Configure E-MAC registers */
418 ravb_write_hwaddr(dev);
420 ret = phy_startup(phy);
424 /* Set the transfer speed */
425 if (phy->speed == 100)
426 writel(0, eth->iobase + RAVB_REG_GECMR);
427 else if (phy->speed == 1000)
428 writel(1, eth->iobase + RAVB_REG_GECMR);
430 /* Check if full duplex mode is supported by the phy */
434 writel(mask, eth->iobase + RAVB_REG_ECMR);
436 phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
441 static int ravb_start(struct udevice *dev)
443 struct ravb_priv *eth = dev_get_priv(dev);
446 ret = ravb_reset(dev);
450 ravb_base_desc_init(eth);
451 ravb_tx_desc_init(eth);
452 ravb_rx_desc_init(eth);
454 ret = ravb_config(dev);
458 /* Setting the control will start the AVB-DMAC process. */
459 writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
464 static void ravb_stop(struct udevice *dev)
466 struct ravb_priv *eth = dev_get_priv(dev);
468 phy_shutdown(eth->phydev);
472 static int ravb_probe(struct udevice *dev)
474 struct eth_pdata *pdata = dev_get_platdata(dev);
475 struct ravb_priv *eth = dev_get_priv(dev);
476 struct ofnode_phandle_args phandle_args;
477 struct mii_dev *mdiodev;
478 void __iomem *iobase;
481 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
482 eth->iobase = iobase;
484 ret = clk_get_by_index(dev, 0, ð->clk);
488 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
490 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
491 ð->reset_gpio, GPIOD_IS_OUT);
494 if (!dm_gpio_is_valid(ð->reset_gpio)) {
495 gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
499 mdiodev = mdio_alloc();
505 mdiodev->read = bb_miiphy_read;
506 mdiodev->write = bb_miiphy_write;
507 bb_miiphy_buses[0].priv = eth;
508 snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
510 ret = mdio_register(mdiodev);
512 goto err_mdio_register;
514 eth->bus = miiphy_get_dev_by_name(dev->name);
517 ret = clk_enable(ð->clk);
519 goto err_mdio_register;
521 ret = ravb_reset(dev);
525 ret = ravb_phy_config(dev);
532 clk_disable(ð->clk);
536 unmap_physmem(eth->iobase, MAP_NOCACHE);
540 static int ravb_remove(struct udevice *dev)
542 struct ravb_priv *eth = dev_get_priv(dev);
544 clk_disable(ð->clk);
547 mdio_unregister(eth->bus);
549 if (dm_gpio_is_valid(ð->reset_gpio))
550 dm_gpio_free(dev, ð->reset_gpio);
551 unmap_physmem(eth->iobase, MAP_NOCACHE);
556 int ravb_bb_init(struct bb_miiphy_bus *bus)
561 int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
563 struct ravb_priv *eth = bus->priv;
565 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
570 int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
572 struct ravb_priv *eth = bus->priv;
574 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
579 int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
581 struct ravb_priv *eth = bus->priv;
584 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
586 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
591 int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
593 struct ravb_priv *eth = bus->priv;
595 *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
600 int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
602 struct ravb_priv *eth = bus->priv;
605 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
607 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
612 int ravb_bb_delay(struct bb_miiphy_bus *bus)
619 struct bb_miiphy_bus bb_miiphy_buses[] = {
622 .init = ravb_bb_init,
623 .mdio_active = ravb_bb_mdio_active,
624 .mdio_tristate = ravb_bb_mdio_tristate,
625 .set_mdio = ravb_bb_set_mdio,
626 .get_mdio = ravb_bb_get_mdio,
627 .set_mdc = ravb_bb_set_mdc,
628 .delay = ravb_bb_delay,
631 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
633 static const struct eth_ops ravb_ops = {
637 .free_pkt = ravb_free_pkt,
639 .write_hwaddr = ravb_write_hwaddr,
642 int ravb_ofdata_to_platdata(struct udevice *dev)
644 struct eth_pdata *pdata = dev_get_platdata(dev);
645 const char *phy_mode;
649 pdata->iobase = devfdt_get_addr(dev);
650 pdata->phy_interface = -1;
651 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
654 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
655 if (pdata->phy_interface == -1) {
656 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
660 pdata->max_speed = 1000;
661 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
663 pdata->max_speed = fdt32_to_cpu(*cell);
665 sprintf(bb_miiphy_buses[0].name, dev->name);
670 static const struct udevice_id ravb_ids[] = {
671 { .compatible = "renesas,etheravb-r8a7795" },
672 { .compatible = "renesas,etheravb-r8a7796" },
673 { .compatible = "renesas,etheravb-r8a77965" },
674 { .compatible = "renesas,etheravb-r8a77970" },
675 { .compatible = "renesas,etheravb-r8a77990" },
676 { .compatible = "renesas,etheravb-r8a77995" },
677 { .compatible = "renesas,etheravb-rcar-gen3" },
681 U_BOOT_DRIVER(eth_ravb) = {
684 .of_match = ravb_ids,
685 .ofdata_to_platdata = ravb_ofdata_to_platdata,
687 .remove = ravb_remove,
689 .priv_auto_alloc_size = sizeof(struct ravb_priv),
690 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
691 .flags = DM_FLAG_ALLOC_PRIV_DMA,