drivers/net/pic32_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
   4  *
   5  */
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <errno.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <malloc.h>
  12 #include <net.h>
  13 #include <miiphy.h>
  14 #include <console.h>
  15 #include <time.h>
  16 #include <wait_bit.h>
  17 #include <asm/gpio.h>
  18 #include <linux/mii.h>
  19
  20 #include "pic32_eth.h"
  21
  22 #define MAX_RX_BUF_SIZE         1536
  23 #define MAX_RX_DESCR            PKTBUFSRX
  24 #define MAX_TX_DESCR            2
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 struct pic32eth_dev {
  29         struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
  30         struct eth_dma_desc txd_ring[MAX_TX_DESCR];
  31         u32 rxd_idx; /* index of RX desc to read */
  32         /* regs */
  33         struct pic32_ectl_regs *ectl_regs;
  34         struct pic32_emac_regs *emac_regs;
  35         /* Phy */
  36         struct phy_device *phydev;
  37         phy_interface_t phyif;
  38         u32 phy_addr;
  39         struct gpio_desc rst_gpio;
  40 };
  41
  42 void __weak board_netphy_reset(void *dev)
  43 {
  44         struct pic32eth_dev *priv = dev;
  45
  46         if (!dm_gpio_is_valid(&priv->rst_gpio))
  47                 return;
  48
  49         /* phy reset */
  50         dm_gpio_set_value(&priv->rst_gpio, 0);
  51         udelay(300);
  52         dm_gpio_set_value(&priv->rst_gpio, 1);
  53         udelay(300);
  54 }
  55
  56 /* Initialize mii(MDIO) interface, discover which PHY is
  57  * attached to the device, and configure it properly.
  58  */
  59 static int pic32_mii_init(struct pic32eth_dev *priv)
  60 {
  61         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  62         struct pic32_emac_regs *emac_p = priv->emac_regs;
  63
  64         /* board phy reset */
  65         board_netphy_reset(priv);
  66
  67         /* disable RX, TX & all transactions */
  68         writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  69
  70         /* wait till busy */
  71         wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  72                           CONFIG_SYS_HZ, false);
  73
  74         /* turn controller ON to access PHY over MII */
  75         writel(ETHCON_ON, &ectl_p->con1.set);
  76
  77         mdelay(10);
  78
  79         /* reset MAC */
  80         writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
  81         mdelay(10);
  82         writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
  83
  84         /* initialize MDIO/MII */
  85         if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
  86                 writel(EMAC_RMII_RESET, &emac_p->supp.set);
  87                 mdelay(10);
  88                 writel(EMAC_RMII_RESET, &emac_p->supp.clr);
  89         }
  90
  91         return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
  92 }
  93
  94 static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
  95 {
  96         struct mii_dev *mii;
  97
  98         mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  99
 100         /* find & connect PHY */
 101         priv->phydev = phy_connect(mii, priv->phy_addr,
 102                                    dev, priv->phyif);
 103         if (!priv->phydev) {
 104                 printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
 105                 return 0;
 106         }
 107
 108         /* Wait for phy to complete reset */
 109         mdelay(10);
 110
 111         /* configure supported modes */
 112         priv->phydev->supported = SUPPORTED_10baseT_Half |
 113                                   SUPPORTED_10baseT_Full |
 114                                   SUPPORTED_100baseT_Half |
 115                                   SUPPORTED_100baseT_Full |
 116                                   SUPPORTED_Autoneg;
 117
 118         priv->phydev->advertising = ADVERTISED_10baseT_Half |
 119                                     ADVERTISED_10baseT_Full |
 120                                     ADVERTISED_100baseT_Half |
 121                                     ADVERTISED_100baseT_Full |
 122                                     ADVERTISED_Autoneg;
 123
 124         priv->phydev->autoneg = AUTONEG_ENABLE;
 125
 126         return 0;
 127 }
 128
 129 /* Configure MAC based on negotiated speed and duplex
 130  * reported by PHY.
 131  */
 132 static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
 133 {
 134         struct phy_device *phydev = priv->phydev;
 135         struct pic32_emac_regs *emac_p = priv->emac_regs;
 136
 137         if (!phydev->link) {
 138                 printf("%s: No link.\n", phydev->dev->name);
 139                 return -EINVAL;
 140         }
 141
 142         if (phydev->duplex) {
 143                 writel(EMAC_FULLDUP, &emac_p->cfg2.set);
 144                 writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
 145         } else {
 146                 writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
 147                 writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
 148         }
 149
 150         switch (phydev->speed) {
 151         case SPEED_100:
 152                 writel(EMAC_RMII_SPD100, &emac_p->supp.set);
 153                 break;
 154         case SPEED_10:
 155                 writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
 156                 break;
 157         default:
 158                 printf("%s: Speed was bad\n", phydev->dev->name);
 159                 return -EINVAL;
 160         }
 161
 162         printf("pic32eth: PHY is %s with %dbase%s, %s\n",
 163                phydev->drv->name, phydev->speed,
 164                (phydev->port == PORT_TP) ? "T" : "X",
 165                (phydev->duplex) ? "full" : "half");
 166
 167         return 0;
 168 }
 169
 170 static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
 171 {
 172         struct pic32_emac_regs *emac_p = priv->emac_regs;
 173         u32 stat = 0, v;
 174         u64 expire;
 175
 176         v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
 177         writel(v, &emac_p->cfg1.raw);
 178
 179         v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
 180             EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
 181         writel(v, &emac_p->cfg2.raw);
 182
 183         /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
 184         writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
 185
 186         /* recommended non-back-to-back interpacket gap is 0xc12 */
 187         writel(0xc12, &emac_p->ipgr.raw);
 188
 189         /* recommended collision window retry limit is 0x370F */
 190         writel(0x370f, &emac_p->clrt.raw);
 191
 192         /* set maximum frame length: allow VLAN tagged frame */
 193         writel(0x600, &emac_p->maxf.raw);
 194
 195         /* set the mac address */
 196         writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
 197         writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
 198         writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
 199
 200         /* default, enable 10 Mbps operation */
 201         writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
 202
 203         /* wait until link status UP or deadline elapsed */
 204         expire = get_ticks() + get_tbclk() * 2;
 205         for (; get_ticks() < expire;) {
 206                 stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
 207                 if (stat & BMSR_LSTATUS)
 208                         break;
 209         }
 210
 211         if (!(stat & BMSR_LSTATUS))
 212                 printf("MAC: Link is DOWN!\n");
 213
 214         /* delay to stabilize before any tx/rx */
 215         mdelay(10);
 216 }
 217
 218 static void pic32_mac_reset(struct pic32eth_dev *priv)
 219 {
 220         struct pic32_emac_regs *emac_p = priv->emac_regs;
 221         struct mii_dev *mii;
 222
 223         /* Reset MAC */
 224         writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
 225         mdelay(10);
 226
 227         /* clear reset */
 228         writel(0, &emac_p->cfg1.raw);
 229
 230         /* Reset MII */
 231         mii = priv->phydev->bus;
 232         if (mii && mii->reset)
 233                 mii->reset(mii);
 234 }
 235
 236 /* initializes the MAC and PHY, then establishes a link */
 237 static void pic32_ctrl_reset(struct pic32eth_dev *priv)
 238 {
 239         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 240         u32 v;
 241
 242         /* disable RX, TX & any other transactions */
 243         writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 244
 245         /* wait till busy */
 246         wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
 247                           CONFIG_SYS_HZ, false);
 248         /* decrement received buffcnt to zero. */
 249         while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
 250                 writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
 251
 252         /* clear any existing interrupt event */
 253         writel(0xffffffff, &ectl_p->irq.clr);
 254
 255         /* clear RX/TX start address */
 256         writel(0xffffffff, &ectl_p->txst.clr);
 257         writel(0xffffffff, &ectl_p->rxst.clr);
 258
 259         /* clear the receive filters */
 260         writel(0x00ff, &ectl_p->rxfc.clr);
 261
 262         /* set the receive filters
 263          * ETH_FILT_CRC_ERR_REJECT
 264          * ETH_FILT_RUNT_REJECT
 265          * ETH_FILT_UCAST_ACCEPT
 266          * ETH_FILT_MCAST_ACCEPT
 267          * ETH_FILT_BCAST_ACCEPT
 268          */
 269         v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
 270             ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
 271         writel(v, &ectl_p->rxfc.set);
 272
 273         /* turn controller ON to access PHY over MII */
 274         writel(ETHCON_ON, &ectl_p->con1.set);
 275 }
 276
 277 static void pic32_rx_desc_init(struct pic32eth_dev *priv)
 278 {
 279         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 280         struct eth_dma_desc *rxd;
 281         u32 idx, bufsz;
 282
 283         priv->rxd_idx = 0;
 284         for (idx = 0; idx < MAX_RX_DESCR; idx++) {
 285                 rxd = &priv->rxd_ring[idx];
 286
 287                 /* hw owned */
 288                 rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
 289
 290                 /* packet buffer address */
 291                 rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
 292
 293                 /* link to next desc */
 294                 rxd->next_ed = virt_to_phys(rxd + 1);
 295
 296                 /* reset status */
 297                 rxd->stat1 = 0;
 298                 rxd->stat2 = 0;
 299
 300                 /* decrement bufcnt */
 301                 writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
 302         }
 303
 304         /* link last descr to beginning of list */
 305         rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
 306
 307         /* flush rx ring */
 308         flush_dcache_range((ulong)priv->rxd_ring,
 309                            (ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
 310
 311         /* set rx desc-ring start address */
 312         writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
 313
 314         /* RX Buffer size */
 315         bufsz = readl(&ectl_p->con2.raw);
 316         bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
 317         bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
 318         writel(bufsz, &ectl_p->con2.raw);
 319
 320         /* enable the receiver in hardware which allows hardware
 321          * to DMA received pkts to the descriptor pointer address.
 322          */
 323         writel(ETHCON_RXEN, &ectl_p->con1.set);
 324 }
 325
 326 static int pic32_eth_start(struct udevice *dev)
 327 {
 328         struct eth_pdata *pdata = dev_get_platdata(dev);
 329         struct pic32eth_dev *priv = dev_get_priv(dev);
 330
 331         /* controller */
 332         pic32_ctrl_reset(priv);
 333
 334         /* reset MAC */
 335         pic32_mac_reset(priv);
 336
 337         /* configure PHY */
 338         phy_config(priv->phydev);
 339
 340         /* initialize MAC */
 341         pic32_mac_init(priv, &pdata->enetaddr[0]);
 342
 343         /* init RX descriptor; TX descriptors are handled in xmit */
 344         pic32_rx_desc_init(priv);
 345
 346         /* Start up & update link status of PHY */
 347         phy_startup(priv->phydev);
 348
 349         /* adjust mac with phy link status */
 350         return pic32_mac_adjust_link(priv);
 351 }
 352
 353 static void pic32_eth_stop(struct udevice *dev)
 354 {
 355         struct pic32eth_dev *priv = dev_get_priv(dev);
 356         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 357         struct pic32_emac_regs *emac_p = priv->emac_regs;
 358
 359         /* Reset the phy if the controller is enabled */
 360         if (readl(&ectl_p->con1.raw) & ETHCON_ON)
 361                 phy_reset(priv->phydev);
 362
 363         /* Shut down the PHY */
 364         phy_shutdown(priv->phydev);
 365
 366         /* Stop rx/tx */
 367         writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 368         mdelay(10);
 369
 370         /* reset MAC */
 371         writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
 372
 373         /* clear reset */
 374         writel(0, &emac_p->cfg1.raw);
 375         mdelay(10);
 376
 377         /* disable controller */
 378         writel(ETHCON_ON, &ectl_p->con1.clr);
 379         mdelay(10);
 380
 381         /* wait until everything is down */
 382         wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
 383                           2 * CONFIG_SYS_HZ, false);
 384
 385         /* clear any existing interrupt event */
 386         writel(0xffffffff, &ectl_p->irq.clr);
 387 }
 388
 389 static int pic32_eth_send(struct udevice *dev, void *packet, int length)
 390 {
 391         struct pic32eth_dev *priv = dev_get_priv(dev);
 392         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 393         struct eth_dma_desc *txd;
 394         u64 deadline;
 395
 396         txd = &priv->txd_ring[0];
 397
 398         /* set proper flags & length in descriptor header */
 399         txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
 400
 401         /* pass buffer address to hardware */
 402         txd->data_buff = virt_to_phys(packet);
 403
 404         debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
 405               __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
 406               txd->next_ed);
 407
 408         /* cache flush (packet) */
 409         flush_dcache_range((ulong)packet, (ulong)packet + length);
 410
 411         /* cache flush (txd) */
 412         flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
 413
 414         /* pass descriptor table base to h/w */
 415         writel(virt_to_phys(txd), &ectl_p->txst.raw);
 416
 417         /* ready to send enabled, hardware can now send the packet(s) */
 418         writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
 419
 420         /* wait until tx has completed and h/w has released ownership
 421          * of the tx descriptor or timeout elapsed.
 422          */
 423         deadline = get_ticks() + get_tbclk();
 424         for (;;) {
 425                 /* check timeout */
 426                 if (get_ticks() > deadline)
 427                         return -ETIMEDOUT;
 428
 429                 if (ctrlc())
 430                         return -EINTR;
 431
 432                 /* tx completed ? */
 433                 if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
 434                         udelay(1);
 435                         continue;
 436                 }
 437
 438                 /* h/w not released ownership yet? */
 439                 invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
 440                 if (!(txd->hdr & EDH_EOWN))
 441                         break;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 448 {
 449         struct pic32eth_dev *priv = dev_get_priv(dev);
 450         struct eth_dma_desc *rxd;
 451         u32 idx = priv->rxd_idx;
 452         u32 rx_count;
 453
 454         /* find the next ready to receive */
 455         rxd = &priv->rxd_ring[idx];
 456
 457         invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
 458         /* check if owned by MAC */
 459         if (rxd->hdr & EDH_EOWN)
 460                 return -EAGAIN;
 461
 462         /* Sanity check on header: SOP and EOP  */
 463         if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
 464                 printf("%s: %s, rx pkt across multiple descr\n",
 465                        __FILE__, __func__);
 466                 return 0;
 467         }
 468
 469         debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
 470               __func__, __LINE__, idx, rxd->hdr,
 471               rxd->data_buff, rxd->stat2, rxd->next_ed);
 472
 473         /* Sanity check on rx_stat: OK, CRC */
 474         if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
 475                 debug("%s: %s: Error, rx problem detected\n",
 476                       __FILE__, __func__);
 477                 return 0;
 478         }
 479
 480         /* invalidate dcache */
 481         rx_count = RSV_RX_COUNT(rxd->stat2);
 482         invalidate_dcache_range((ulong)net_rx_packets[idx],
 483                                 (ulong)net_rx_packets[idx] + rx_count);
 484
 485         /* Pass the packet to protocol layer */
 486         *packetp = net_rx_packets[idx];
 487
 488         /* increment number of bytes rcvd (ignore CRC) */
 489         return rx_count - 4;
 490 }
 491
 492 static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
 493 {
 494         struct pic32eth_dev *priv = dev_get_priv(dev);
 495         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 496         struct eth_dma_desc *rxd;
 497         int idx = priv->rxd_idx;
 498
 499         /* sanity check */
 500         if (packet != net_rx_packets[idx]) {
 501                 printf("rxd_id %d: packet is not matched,\n", idx);
 502                 return -EAGAIN;
 503         }
 504
 505         /* prepare for receive */
 506         rxd = &priv->rxd_ring[idx];
 507         rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
 508
 509         flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
 510
 511         /* decrement rx pkt count */
 512         writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
 513
 514         debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
 515               __func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
 516               rxd->stat2, rxd->next_ed);
 517
 518         priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
 519
 520         return 0;
 521 }
 522
 523 static const struct eth_ops pic32_eth_ops = {
 524         .start          = pic32_eth_start,
 525         .send           = pic32_eth_send,
 526         .recv           = pic32_eth_recv,
 527         .free_pkt       = pic32_eth_free_pkt,
 528         .stop           = pic32_eth_stop,
 529 };
 530
 531 static int pic32_eth_probe(struct udevice *dev)
 532 {
 533         struct eth_pdata *pdata = dev_get_platdata(dev);
 534         struct pic32eth_dev *priv = dev_get_priv(dev);
 535         const char *phy_mode;
 536         void __iomem *iobase;
 537         fdt_addr_t addr;
 538         fdt_size_t size;
 539         int offset = 0;
 540         int phy_addr = -1;
 541
 542         addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
 543                                     &size);
 544         if (addr == FDT_ADDR_T_NONE)
 545                 return -EINVAL;
 546
 547         iobase = ioremap(addr, size);
 548         pdata->iobase = (phys_addr_t)addr;
 549
 550         /* get phy mode */
 551         pdata->phy_interface = -1;
 552         phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 553                                NULL);
 554         if (phy_mode)
 555                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 556         if (pdata->phy_interface == -1) {
 557                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 558                 return -EINVAL;
 559         }
 560
 561         /* get phy addr */
 562         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
 563                                        "phy-handle");
 564         if (offset > 0)
 565                 phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 566
 567         /* phy reset gpio */
 568         gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
 569                                    &priv->rst_gpio, GPIOD_IS_OUT);
 570
 571         priv->phyif     = pdata->phy_interface;
 572         priv->phy_addr  = phy_addr;
 573         priv->ectl_regs = iobase;
 574         priv->emac_regs = iobase + PIC32_EMAC1CFG1;
 575
 576         pic32_mii_init(priv);
 577
 578         return pic32_phy_init(priv, dev);
 579 }
 580
 581 static int pic32_eth_remove(struct udevice *dev)
 582 {
 583         struct pic32eth_dev *priv = dev_get_priv(dev);
 584         struct mii_dev *bus;
 585
 586         dm_gpio_free(dev, &priv->rst_gpio);
 587         phy_shutdown(priv->phydev);
 588         free(priv->phydev);
 589         bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
 590         mdio_unregister(bus);
 591         mdio_free(bus);
 592         iounmap(priv->ectl_regs);
 593         return 0;
 594 }
 595
 596 static const struct udevice_id pic32_eth_ids[] = {
 597         { .compatible = "microchip,pic32mzda-eth" },
 598         { }
 599 };
 600
 601 U_BOOT_DRIVER(pic32_ethernet) = {
 602         .name                   = "pic32_ethernet",
 603         .id                     = UCLASS_ETH,
 604         .of_match               = pic32_eth_ids,
 605         .probe                  = pic32_eth_probe,
 606         .remove                 = pic32_eth_remove,
 607         .ops                    = &pic32_eth_ops,
 608         .priv_auto_alloc_size   = sizeof(struct pic32eth_dev),
 609         .platdata_auto_alloc_size       = sizeof(struct eth_pdata),
 610 };