1 // SPDX-License-Identifier: GPL-2.0+
4 * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
11 #include <linux/errno.h>
12 #include <mv88e6352.h>
14 #define SMI_HDR ((0x8 | 0x1) << 12)
15 #define SMI_BUSY_MASK (0x8000)
16 #define SMIRD_OP (0x2 << 10)
17 #define SMIWR_OP (0x1 << 10)
24 /* global registers */
27 #define GLOBAL_STATUS 0x00
28 #define PPU_STATE 0x8000
30 #define GLOBAL_CTRL 0x04
31 #define SW_RESET 0x8000
32 #define PPU_ENABLE 0x4000
34 static int sw_wait_rdy(const char *devname, u8 phy_addr)
40 /* wait till the SMI is not busy */
42 /* read command register */
43 ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command);
45 printf("%s: Error reading command register\n",
50 printf("Err..(%s) SMI busy timeout\n", __func__);
53 } while (command & SMI_BUSY_MASK);
58 static int sw_reg_read(const char *devname, u8 phy_addr, u8 port,
64 ret = sw_wait_rdy(devname, phy_addr);
68 command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) |
70 debug("%s: write to command: %#x\n", __func__, command);
71 ret = miiphy_write(devname, phy_addr, COMMAND_REG, command);
75 ret = sw_wait_rdy(devname, phy_addr);
79 ret = miiphy_read(devname, phy_addr, DATA_REG, data);
84 static int sw_reg_write(const char *devname, u8 phy_addr, u8 port,
90 ret = sw_wait_rdy(devname, phy_addr);
94 debug("%s: write to data: %#x\n", __func__, data);
95 ret = miiphy_write(devname, phy_addr, DATA_REG, data);
99 value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) |
101 debug("%s: write to command: %#x\n", __func__, value);
102 ret = miiphy_write(devname, phy_addr, COMMAND_REG, value);
106 ret = sw_wait_rdy(devname, phy_addr);
113 static int ppu_enable(const char *devname, u8 phy_addr)
118 ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
120 printf("%s: Error reading global ctrl reg\n", __func__);
126 ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
128 printf("%s: Error writing global ctrl reg\n", __func__);
132 for (i = 0; i < 1000; i++) {
133 sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
135 if ((reg & 0xc000) == 0xc000)
143 static int ppu_disable(const char *devname, u8 phy_addr)
148 ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
150 printf("%s: Error reading global ctrl reg\n", __func__);
156 ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
158 printf("%s: Error writing global ctrl reg\n", __func__);
162 for (i = 0; i < 1000; i++) {
163 sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
165 if ((reg & 0xc000) != 0xc000)
173 int mv88e_sw_program(const char *devname, u8 phy_addr,
174 struct mv88e_sw_reg *regs, int regs_nb)
178 /* first we need to disable the PPU */
179 ret = ppu_disable(devname, phy_addr);
181 printf("%s: Error disabling PPU\n", __func__);
185 for (i = 0; i < regs_nb; i++) {
186 ret = sw_reg_write(devname, phy_addr, regs[i].port,
187 regs[i].reg, regs[i].value);
189 printf("%s: Error configuring switch\n", __func__);
190 ppu_enable(devname, phy_addr);
195 /* re-enable the PPU */
196 ret = ppu_enable(devname, phy_addr);
198 printf("%s: Error enabling PPU\n", __func__);
205 int mv88e_sw_reset(const char *devname, u8 phy_addr)
210 ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
212 printf("%s: Error reading global ctrl reg\n", __func__);
216 reg = SW_RESET | PPU_ENABLE | 0x0400;
218 ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
220 printf("%s: Error writing global ctrl reg\n", __func__);
224 for (i = 0; i < 1000; i++) {
225 sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
227 if ((reg & 0xc800) != 0xc800)
235 int do_mvsw_reg_read(const char *name, int argc, char *const argv[])
237 u16 value = 0, phyaddr, reg, port;
240 phyaddr = simple_strtoul(argv[1], NULL, 10);
241 port = simple_strtoul(argv[2], NULL, 10);
242 reg = simple_strtoul(argv[3], NULL, 10);
244 ret = sw_reg_read(name, phyaddr, port, reg, &value);
245 printf("%#x\n", value);
250 int do_mvsw_reg_write(const char *name, int argc, char *const argv[])
252 u16 value = 0, phyaddr, reg, port;
255 phyaddr = simple_strtoul(argv[1], NULL, 10);
256 port = simple_strtoul(argv[2], NULL, 10);
257 reg = simple_strtoul(argv[3], NULL, 10);
258 value = simple_strtoul(argv[4], NULL, 16);
260 ret = sw_reg_write(name, phyaddr, port, reg, value);
266 int do_mvsw_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
269 const char *cmd, *ethname;
272 return cmd_usage(cmdtp);
278 if (strcmp(cmd, "read") == 0) {
280 return cmd_usage(cmdtp);
284 ret = do_mvsw_reg_read(ethname, argc, argv);
285 } else if (strcmp(cmd, "write") == 0) {
287 return cmd_usage(cmdtp);
291 ret = do_mvsw_reg_write(ethname, argc, argv);
293 return cmd_usage(cmdtp);
299 mvsw_reg, 7, 1, do_mvsw_reg,
300 "marvell 88e6352 switch register access",
301 "write ethname phyaddr port reg value\n"
302 "mvsw_reg read ethname phyaddr port reg\n"