1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
12 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
14 #define MII_MARVELL_PHY_PAGE 22
16 /* 88E1011 PHY Status Register */
17 #define MIIM_88E1xxx_PHY_STATUS 0x11
18 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
19 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
20 #define MIIM_88E1xxx_PHYSTAT_100 0x4000
21 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
22 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
23 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
25 #define MIIM_88E1xxx_PHY_SCR 0x10
26 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
28 /* 88E1111 PHY LED Control Register */
29 #define MIIM_88E1111_PHY_LED_CONTROL 24
30 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
31 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
33 /* 88E1111 Extended PHY Specific Control Register */
34 #define MIIM_88E1111_PHY_EXT_CR 0x14
35 #define MIIM_88E1111_RX_DELAY 0x80
36 #define MIIM_88E1111_TX_DELAY 0x2
38 /* 88E1111 Extended PHY Specific Status Register */
39 #define MIIM_88E1111_PHY_EXT_SR 0x1b
40 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
41 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
42 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
43 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
44 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
46 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
48 #define MIIM_88E1111_COPPER 0
49 #define MIIM_88E1111_FIBER 1
51 /* 88E1118 PHY defines */
52 #define MIIM_88E1118_PHY_PAGE 22
53 #define MIIM_88E1118_PHY_LED_PAGE 3
55 /* 88E1121 PHY LED Control Register */
56 #define MIIM_88E1121_PHY_LED_CTRL 16
57 #define MIIM_88E1121_PHY_LED_PAGE 3
58 #define MIIM_88E1121_PHY_LED_DEF 0x0030
60 /* 88E1121 PHY IRQ Enable/Status Register */
61 #define MIIM_88E1121_PHY_IRQ_EN 18
62 #define MIIM_88E1121_PHY_IRQ_STATUS 19
64 #define MIIM_88E1121_PHY_PAGE 22
66 /* 88E1145 Extended PHY Specific Control Register */
67 #define MIIM_88E1145_PHY_EXT_CR 20
68 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
69 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
71 #define MIIM_88E1145_PHY_LED_CONTROL 24
72 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
74 #define MIIM_88E1145_PHY_PAGE 29
75 #define MIIM_88E1145_PHY_CAL_OV 30
77 #define MIIM_88E1149_PHY_PAGE 29
79 /* 88E1310 PHY defines */
80 #define MIIM_88E1310_PHY_LED_CTRL 16
81 #define MIIM_88E1310_PHY_IRQ_EN 18
82 #define MIIM_88E1310_PHY_RGMII_CTRL 21
83 #define MIIM_88E1310_PHY_PAGE 22
85 /* 88E151x PHY defines */
86 /* Page 2 registers */
87 #define MIIM_88E151x_PHY_MSCR 21
88 #define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
89 #define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
90 #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
91 /* Page 3 registers */
92 #define MIIM_88E151x_LED_FUNC_CTRL 16
93 #define MIIM_88E151x_LED_FLD_SZ 4
94 #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ)
95 #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ)
96 #define MIIM_88E151x_LED0_ACT 3
97 #define MIIM_88E151x_LED1_100_1000_LINK 6
98 #define MIIM_88E151x_LED_TIMER_CTRL 18
99 #define MIIM_88E151x_INT_EN_OFFS 7
100 /* Page 18 registers */
101 #define MIIM_88E151x_GENERAL_CTRL 20
102 #define MIIM_88E151x_MODE_SGMII 1
103 #define MIIM_88E151x_RESET_OFFS 15
105 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
106 int devaddr, int regnum)
108 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
111 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
112 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
113 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
118 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
119 int devaddr, int regnum, u16 val)
121 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
123 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
124 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
130 /* Marvell 88E1011S */
131 static int m88e1011s_config(struct phy_device *phydev)
133 /* Reset and configure the PHY */
134 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
136 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
137 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
140 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
142 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
144 genphy_config_aneg(phydev);
149 /* Parse the 88E1011's status register for speed and duplex
152 static int m88e1xxx_parse_status(struct phy_device *phydev)
155 unsigned int mii_reg;
157 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
159 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
160 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
163 puts("Waiting for PHY realtime link");
164 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
165 /* Timeout reached ? */
166 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
167 puts(" TIMEOUT !\n");
172 if ((i++ % 1000) == 0)
175 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
176 MIIM_88E1xxx_PHY_STATUS);
179 mdelay(500); /* another 500 ms (results in faster booting) */
181 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
187 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
188 phydev->duplex = DUPLEX_FULL;
190 phydev->duplex = DUPLEX_HALF;
192 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
195 case MIIM_88E1xxx_PHYSTAT_GBIT:
196 phydev->speed = SPEED_1000;
198 case MIIM_88E1xxx_PHYSTAT_100:
199 phydev->speed = SPEED_100;
202 phydev->speed = SPEED_10;
209 static int m88e1011s_startup(struct phy_device *phydev)
213 ret = genphy_update_link(phydev);
217 return m88e1xxx_parse_status(phydev);
220 /* Marvell 88E1111S */
221 static int m88e1111s_config(struct phy_device *phydev)
225 if (phy_interface_is_rgmii(phydev)) {
226 reg = phy_read(phydev,
227 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
228 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
229 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
230 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
231 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
232 reg &= ~MIIM_88E1111_TX_DELAY;
233 reg |= MIIM_88E1111_RX_DELAY;
234 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
235 reg &= ~MIIM_88E1111_RX_DELAY;
236 reg |= MIIM_88E1111_TX_DELAY;
240 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
242 reg = phy_read(phydev,
243 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
245 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
247 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
248 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
250 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
253 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
256 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
257 reg = phy_read(phydev,
258 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
260 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
261 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
262 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
264 phy_write(phydev, MDIO_DEVAD_NONE,
265 MIIM_88E1111_PHY_EXT_SR, reg);
268 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
269 reg = phy_read(phydev,
270 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
271 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
273 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
275 reg = phy_read(phydev, MDIO_DEVAD_NONE,
276 MIIM_88E1111_PHY_EXT_SR);
277 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
278 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
279 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
280 phy_write(phydev, MDIO_DEVAD_NONE,
281 MIIM_88E1111_PHY_EXT_SR, reg);
286 reg = phy_read(phydev, MDIO_DEVAD_NONE,
287 MIIM_88E1111_PHY_EXT_SR);
288 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
289 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
290 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
291 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
292 phy_write(phydev, MDIO_DEVAD_NONE,
293 MIIM_88E1111_PHY_EXT_SR, reg);
299 genphy_config_aneg(phydev);
300 genphy_restart_aneg(phydev);
306 * m88e151x_phy_writebits - write bits to a register
308 void m88e151x_phy_writebits(struct phy_device *phydev,
309 u8 reg_num, u16 offset, u16 len, u16 data)
313 if ((len + offset) >= 16)
314 mask = 0 - (1 << offset);
316 mask = (1 << (len + offset)) - (1 << offset);
318 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
321 reg |= data << offset;
323 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
326 static int m88e151x_config(struct phy_device *phydev)
331 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
332 * /88E1514 Rev A0, Errata Section 3.1
335 /* EEE initialization */
336 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
337 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
338 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
339 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
340 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
341 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
342 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
343 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
344 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
345 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
347 /* SGMII-to-Copper mode initialization */
348 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
350 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
352 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
353 m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
354 0, 3, MIIM_88E151x_MODE_SGMII);
356 /* PHY reset is necessary after changing MODE[2:0] */
357 m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
358 MIIM_88E151x_RESET_OFFS, 1, 1);
360 /* Reset page selection */
361 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
366 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
367 reg = phy_read(phydev, MDIO_DEVAD_NONE,
368 MIIM_88E1111_PHY_EXT_SR);
370 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
371 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
372 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
374 phy_write(phydev, MDIO_DEVAD_NONE,
375 MIIM_88E1111_PHY_EXT_SR, reg);
378 if (phy_interface_is_rgmii(phydev)) {
379 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
381 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
382 reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
383 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
384 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
385 reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
386 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
387 reg |= MIIM_88E151x_RGMII_RX_DELAY;
388 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
389 reg |= MIIM_88E151x_RGMII_TX_DELAY;
390 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
392 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
398 genphy_config_aneg(phydev);
399 genphy_restart_aneg(phydev);
404 /* Marvell 88E1118 */
405 static int m88e1118_config(struct phy_device *phydev)
407 /* Change Page Number */
408 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
409 /* Delay RGMII TX and RX */
410 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
411 /* Change Page Number */
412 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
413 /* Adjust LED control */
414 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
415 /* Change Page Number */
416 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
418 return genphy_config_aneg(phydev);
421 static int m88e1118_startup(struct phy_device *phydev)
425 /* Change Page Number */
426 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
428 ret = genphy_update_link(phydev);
432 return m88e1xxx_parse_status(phydev);
435 /* Marvell 88E1121R */
436 static int m88e1121_config(struct phy_device *phydev)
440 /* Configure the PHY */
441 genphy_config_aneg(phydev);
443 /* Switch the page to access the led register */
444 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
445 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
446 MIIM_88E1121_PHY_LED_PAGE);
448 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
449 MIIM_88E1121_PHY_LED_DEF);
450 /* Restore the page pointer */
451 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
453 /* Disable IRQs and de-assert interrupt */
454 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
455 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
460 /* Marvell 88E1145 */
461 static int m88e1145_config(struct phy_device *phydev)
466 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
467 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
468 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
471 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
472 MIIM_88E1xxx_PHY_MDI_X_AUTO);
474 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
475 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
476 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
477 MIIM_M88E1145_RGMII_TX_DELAY;
478 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
480 genphy_config_aneg(phydev);
483 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
485 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
490 static int m88e1145_startup(struct phy_device *phydev)
494 ret = genphy_update_link(phydev);
498 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
499 MIIM_88E1145_PHY_LED_DIRECT);
500 return m88e1xxx_parse_status(phydev);
503 /* Marvell 88E1149S */
504 static int m88e1149_config(struct phy_device *phydev)
506 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
507 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
508 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
509 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
510 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
512 genphy_config_aneg(phydev);
519 /* Marvell 88E1310 */
520 static int m88e1310_config(struct phy_device *phydev)
524 /* LED link and activity */
525 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
526 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
527 reg = (reg & ~0xf) | 0x1;
528 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
530 /* Set LED2/INT to INT mode, low active */
531 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
532 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
533 reg = (reg & 0x77ff) | 0x0880;
534 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
536 /* Set RGMII delay */
537 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
538 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
540 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
542 /* Ensure to return to page 0 */
543 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
545 return genphy_config_aneg(phydev);
548 static int m88e1680_config(struct phy_device *phydev)
551 * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
557 /* Matrix LED mode (not neede if single LED mode is used */
558 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
559 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
561 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
563 /* QSGMII TX amplitude change */
564 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
565 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
566 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
567 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
569 /* EEE initialization */
570 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
571 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
572 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
573 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
574 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
575 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
576 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
577 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
579 res = genphy_config_aneg(phydev);
584 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
586 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
591 static struct phy_driver M88E1011S_driver = {
592 .name = "Marvell 88E1011S",
595 .features = PHY_GBIT_FEATURES,
596 .config = &m88e1011s_config,
597 .startup = &m88e1011s_startup,
598 .shutdown = &genphy_shutdown,
601 static struct phy_driver M88E1111S_driver = {
602 .name = "Marvell 88E1111S",
605 .features = PHY_GBIT_FEATURES,
606 .config = &m88e1111s_config,
607 .startup = &m88e1011s_startup,
608 .shutdown = &genphy_shutdown,
611 static struct phy_driver M88E1118_driver = {
612 .name = "Marvell 88E1118",
615 .features = PHY_GBIT_FEATURES,
616 .config = &m88e1118_config,
617 .startup = &m88e1118_startup,
618 .shutdown = &genphy_shutdown,
621 static struct phy_driver M88E1118R_driver = {
622 .name = "Marvell 88E1118R",
625 .features = PHY_GBIT_FEATURES,
626 .config = &m88e1118_config,
627 .startup = &m88e1118_startup,
628 .shutdown = &genphy_shutdown,
631 static struct phy_driver M88E1121R_driver = {
632 .name = "Marvell 88E1121R",
635 .features = PHY_GBIT_FEATURES,
636 .config = &m88e1121_config,
637 .startup = &genphy_startup,
638 .shutdown = &genphy_shutdown,
641 static struct phy_driver M88E1145_driver = {
642 .name = "Marvell 88E1145",
645 .features = PHY_GBIT_FEATURES,
646 .config = &m88e1145_config,
647 .startup = &m88e1145_startup,
648 .shutdown = &genphy_shutdown,
651 static struct phy_driver M88E1149S_driver = {
652 .name = "Marvell 88E1149S",
655 .features = PHY_GBIT_FEATURES,
656 .config = &m88e1149_config,
657 .startup = &m88e1011s_startup,
658 .shutdown = &genphy_shutdown,
661 static struct phy_driver M88E151x_driver = {
662 .name = "Marvell 88E151x",
665 .features = PHY_GBIT_FEATURES,
666 .config = &m88e151x_config,
667 .startup = &m88e1011s_startup,
668 .shutdown = &genphy_shutdown,
669 .readext = &m88e1xxx_phy_extread,
670 .writeext = &m88e1xxx_phy_extwrite,
673 static struct phy_driver M88E1310_driver = {
674 .name = "Marvell 88E1310",
677 .features = PHY_GBIT_FEATURES,
678 .config = &m88e1310_config,
679 .startup = &m88e1011s_startup,
680 .shutdown = &genphy_shutdown,
683 static struct phy_driver M88E1680_driver = {
684 .name = "Marvell 88E1680",
687 .features = PHY_GBIT_FEATURES,
688 .config = &m88e1680_config,
689 .startup = &genphy_startup,
690 .shutdown = &genphy_shutdown,
693 int phy_marvell_init(void)
695 phy_register(&M88E1310_driver);
696 phy_register(&M88E1149S_driver);
697 phy_register(&M88E1145_driver);
698 phy_register(&M88E1121R_driver);
699 phy_register(&M88E1118_driver);
700 phy_register(&M88E1118R_driver);
701 phy_register(&M88E1111S_driver);
702 phy_register(&M88E1011S_driver);
703 phy_register(&M88E151x_driver);
704 phy_register(&M88E1680_driver);