drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <dm/devres.h>
   9 #include <linux/compat.h>
  10 #include <malloc.h>
  11
  12 #include <dm.h>
  13 #include <dt-bindings/net/ti-dp83867.h>
  14
  15
  16 /* TI DP83867 */
  17 #define DP83867_DEVADDR         0x1f
  18
  19 #define MII_DP83867_PHYCTRL     0x10
  20 #define MII_DP83867_MICR        0x12
  21 #define MII_DP83867_CFG2        0x14
  22 #define MII_DP83867_BISCR       0x16
  23 #define DP83867_CTRL            0x1f
  24
  25 /* Extended Registers */
  26 #define DP83867_CFG4            0x0031
  27 #define DP83867_RGMIICTL        0x0032
  28 #define DP83867_STRAP_STS1      0x006E
  29 #define DP83867_STRAP_STS2      0x006f
  30 #define DP83867_RGMIIDCTL       0x0086
  31 #define DP83867_IO_MUX_CFG      0x0170
  32 #define DP83867_SGMIICTL        0x00D3
  33
  34 #define DP83867_SW_RESET        BIT(15)
  35 #define DP83867_SW_RESTART      BIT(14)
  36
  37 /* MICR Interrupt bits */
  38 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  39 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  40 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  41 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  42 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  43 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  44 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  45 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  46 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  47 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  48 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  49 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  50
  51 /* RGMIICTL bits */
  52 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  53 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  54
  55 /* STRAP_STS1 bits */
  56 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  57
  58 /* STRAP_STS2 bits */
  59 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  60 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  61 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  62 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  63 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  64
  65 /* PHY CTRL bits */
  66 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  67 #define DP83867_PHYCR_FIFO_DEPTH_MASK           GENMASK(15, 14)
  68 #define DP83867_PHYCR_RESERVED_MASK     BIT(11)
  69 #define DP83867_PHYCR_FORCE_LINK_GOOD   BIT(10)
  70 #define DP83867_MDI_CROSSOVER           5
  71 #define DP83867_MDI_CROSSOVER_MDIX      2
  72 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  73 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  74 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  75
  76 /* RGMIIDCTL bits */
  77 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
  78 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  79 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
  80
  81 /* CFG2 bits */
  82 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  83 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  84 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  85 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  86 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  87 #define MII_DP83867_CFG2_MASK                   0x003F
  88
  89 /* User setting - can be taken from DTS */
  90 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  91
  92 /* IO_MUX_CFG bits */
  93 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  94
  95 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  96 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  97 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
  98 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  99 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       \
 100                 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
 101
 102 /* CFG4 bits */
 103 #define DP83867_CFG4_PORT_MIRROR_EN             BIT(0)
 104
 105 /* SGMIICTL bits */
 106 #define DP83867_SGMII_TYPE                      BIT(14)
 107
 108 enum {
 109         DP83867_PORT_MIRRORING_KEEP,
 110         DP83867_PORT_MIRRORING_EN,
 111         DP83867_PORT_MIRRORING_DIS,
 112 };
 113
 114 struct dp83867_private {
 115         u32 rx_id_delay;
 116         u32 tx_id_delay;
 117         int fifo_depth;
 118         int io_impedance;
 119         bool rxctrl_strap_quirk;
 120         int port_mirroring;
 121         bool set_clk_output;
 122         unsigned int clk_output_sel;
 123         bool sgmii_ref_clk_en;
 124 };
 125
 126 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 127 {
 128         struct dp83867_private *dp83867 =
 129                 (struct dp83867_private *)phydev->priv;
 130         u16 val;
 131
 132         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 133
 134         if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
 135                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 136         else
 137                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 138
 139         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 140
 141         return 0;
 142 }
 143
 144 #if defined(CONFIG_DM_ETH)
 145 /**
 146  * dp83867_data_init - Convenience function for setting PHY specific data
 147  *
 148  * @phydev: the phy_device struct
 149  */
 150 static int dp83867_of_init(struct phy_device *phydev)
 151 {
 152         struct dp83867_private *dp83867 = phydev->priv;
 153         ofnode node;
 154         int ret;
 155
 156         node = phy_get_ofnode(phydev);
 157         if (!ofnode_valid(node))
 158                 return -EINVAL;
 159
 160         /* Optional configuration */
 161         ret = ofnode_read_u32(node, "ti,clk-output-sel",
 162                               &dp83867->clk_output_sel);
 163         /* If not set, keep default */
 164         if (!ret) {
 165                 dp83867->set_clk_output = true;
 166                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 167                  * DP83867_CLK_O_SEL_OFF.
 168                  */
 169                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 170                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 171                         pr_debug("ti,clk-output-sel value %u out of range\n",
 172                                  dp83867->clk_output_sel);
 173                         return -EINVAL;
 174                 }
 175         }
 176
 177         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 178                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 179         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 180                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 181         else
 182                 dp83867->io_impedance = -EINVAL;
 183
 184         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 185                 dp83867->rxctrl_strap_quirk = true;
 186
 187         /* Existing behavior was to use default pin strapping delay in rgmii
 188          * mode, but rgmii should have meant no delay.  Warn existing users.
 189          */
 190         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 191                 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 192                                        DP83867_STRAP_STS2);
 193                 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 194                              DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 195                 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 196                              DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 197
 198                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 199                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 200                         pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 201                                 "Should be 'rgmii-id' to use internal delays\n");
 202         }
 203
 204         /* RX delay *must* be specified if internal delay of RX is used. */
 205         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 206             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 207                 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
 208                                       &dp83867->rx_id_delay);
 209                 if (ret) {
 210                         pr_debug("ti,rx-internal-delay must be specified\n");
 211                         return ret;
 212                 }
 213                 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 214                         pr_debug("ti,rx-internal-delay value of %u out of range\n",
 215                                  dp83867->rx_id_delay);
 216                         return -EINVAL;
 217                 }
 218         }
 219
 220         /* TX delay *must* be specified if internal delay of RX is used. */
 221         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 222             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 223                 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
 224                                       &dp83867->tx_id_delay);
 225                 if (ret) {
 226                         debug("ti,tx-internal-delay must be specified\n");
 227                         return ret;
 228                 }
 229                 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 230                         pr_debug("ti,tx-internal-delay value of %u out of range\n",
 231                                  dp83867->tx_id_delay);
 232                         return -EINVAL;
 233                 }
 234         }
 235
 236         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 237                                                       DEFAULT_FIFO_DEPTH);
 238         if (ofnode_read_bool(node, "enet-phy-lane-swap"))
 239                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
 240
 241         if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 242                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 243
 244         if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
 245                 dp83867->sgmii_ref_clk_en = true;
 246
 247         return 0;
 248 }
 249 #else
 250 static int dp83867_of_init(struct phy_device *phydev)
 251 {
 252         struct dp83867_private *dp83867 = phydev->priv;
 253
 254         dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
 255         dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
 256         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 257         dp83867->io_impedance = -EINVAL;
 258
 259         return 0;
 260 }
 261 #endif
 262
 263 static int dp83867_config(struct phy_device *phydev)
 264 {
 265         struct dp83867_private *dp83867;
 266         unsigned int val, delay, cfg2;
 267         int ret, bs;
 268
 269         dp83867 = (struct dp83867_private *)phydev->priv;
 270
 271         ret = dp83867_of_init(phydev);
 272         if (ret)
 273                 return ret;
 274
 275         /* Restart the PHY.  */
 276         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 277         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 278                   val | DP83867_SW_RESTART);
 279
 280         /* Mode 1 or 2 workaround */
 281         if (dp83867->rxctrl_strap_quirk) {
 282                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 283                                    DP83867_CFG4);
 284                 val &= ~BIT(7);
 285                 phy_write_mmd(phydev, DP83867_DEVADDR,
 286                               DP83867_CFG4, val);
 287         }
 288
 289         if (phy_interface_is_rgmii(phydev)) {
 290                 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
 291                 if (val < 0)
 292                         goto err_out;
 293                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 294                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 295
 296                 /* Do not force link good */
 297                 val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
 298
 299                 /* The code below checks if "port mirroring" N/A MODE4 has been
 300                  * enabled during power on bootstrap.
 301                  *
 302                  * Such N/A mode enabled by mistake can put PHY IC in some
 303                  * internal testing mode and disable RGMII transmission.
 304                  *
 305                  * In this particular case one needs to check STRAP_STS1
 306                  * register's bit 11 (marked as RESERVED).
 307                  */
 308
 309                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 310                 if (bs & DP83867_STRAP_STS1_RESERVED)
 311                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 312
 313                 ret = phy_write(phydev, MDIO_DEVAD_NONE,
 314                                 MII_DP83867_PHYCTRL, val);
 315
 316                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 317                                    DP83867_RGMIICTL);
 318
 319                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
 320                          DP83867_RGMII_RX_CLK_DELAY_EN);
 321                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 322                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 323                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 324
 325                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 326                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 327
 328                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 329                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 330
 331                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 332
 333                 delay = (dp83867->rx_id_delay |
 334                         (dp83867->tx_id_delay <<
 335                         DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 336
 337                 phy_write_mmd(phydev, DP83867_DEVADDR,
 338                               DP83867_RGMIIDCTL, delay);
 339         }
 340
 341         if (phy_interface_is_sgmii(phydev)) {
 342                 if (dp83867->sgmii_ref_clk_en)
 343                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
 344                                       DP83867_SGMII_TYPE);
 345
 346                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 347                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 348
 349                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 350                 cfg2 &= MII_DP83867_CFG2_MASK;
 351                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 352                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 353                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 354                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 355                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 356                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 357
 358                 phy_write_mmd(phydev, DP83867_DEVADDR,
 359                               DP83867_RGMIICTL, 0x0);
 360
 361                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 362                           DP83867_PHYCTRL_SGMIIEN |
 363                           (DP83867_MDI_CROSSOVER_MDIX <<
 364                           DP83867_MDI_CROSSOVER) |
 365                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 366                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 367                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 368         }
 369
 370         if (dp83867->io_impedance >= 0) {
 371                 val = phy_read_mmd(phydev,
 372                                    DP83867_DEVADDR,
 373                                    DP83867_IO_MUX_CFG);
 374                 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 375                 val |= dp83867->io_impedance &
 376                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 377                 phy_write_mmd(phydev, DP83867_DEVADDR,
 378                               DP83867_IO_MUX_CFG, val);
 379         }
 380
 381         if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
 382                 dp83867_config_port_mirroring(phydev);
 383
 384         /* Clock output selection if muxing property is set */
 385         if (dp83867->set_clk_output) {
 386                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 387                                    DP83867_IO_MUX_CFG);
 388
 389                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 390                         val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 391                 } else {
 392                         val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
 393                                  DP83867_IO_MUX_CFG_CLK_O_DISABLE);
 394                         val |= dp83867->clk_output_sel <<
 395                                DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 396                 }
 397                 phy_write_mmd(phydev, DP83867_DEVADDR,
 398                               DP83867_IO_MUX_CFG, val);
 399         }
 400
 401         genphy_config_aneg(phydev);
 402         return 0;
 403
 404 err_out:
 405         return ret;
 406 }
 407
 408 static int dp83867_probe(struct phy_device *phydev)
 409 {
 410         struct dp83867_private *dp83867;
 411
 412         dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 413         if (!dp83867)
 414                 return -ENOMEM;
 415
 416         phydev->priv = dp83867;
 417         return 0;
 418 }
 419
 420 static struct phy_driver DP83867_driver = {
 421         .name = "TI DP83867",
 422         .uid = 0x2000a231,
 423         .mask = 0xfffffff0,
 424         .features = PHY_GBIT_FEATURES,
 425         .probe = dp83867_probe,
 426         .config = &dp83867_config,
 427         .startup = &genphy_startup,
 428         .shutdown = &genphy_shutdown,
 429 };
 430
 431 int phy_ti_init(void)
 432 {
 433         phy_register(&DP83867_driver);
 434         return 0;
 435 }