1 // SPDX-License-Identifier: GPL-2.0+
3 * Cortina CS4315/CS4340 10G PHY drivers
5 * Copyright 2014 Freescale Semiconductor, Inc.
14 #include <linux/ctype.h>
15 #include <linux/string.h>
16 #include <linux/err.h>
19 #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
21 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
22 #include <spi_flash.h>
23 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
27 #ifndef CONFIG_PHYLIB_10G
28 #error The Cortina PHY needs 10G support
31 #ifndef CORTINA_NO_FW_UPLOAD
32 struct cortina_reg_config cortina_reg_cfg[] = {
33 /* CS4315_enable_sr_mode */
34 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
35 {VILLA_MSEQ_OPTIONS, 0xf},
37 {VILLA_MSEQ_BANKSELECT, 0x4},
38 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
39 {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
40 {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
41 {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
42 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
43 {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
44 {VILLA_MSEQ_ENABLE_MSB, 0x0000},
45 {VILLA_MSEQ_SPARE21_LSB, 0x6},
46 {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
47 {VILLA_MSEQ_SPARE12_MSB, 0x0000},
49 * to invert the receiver path, uncomment the next line
50 * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
52 * SPARE2_LSB is used to configure the device while in sr mode to
53 * enable power savings and to use the optical module LOS signal.
54 * in power savings mode, the internal prbs checker can not be used.
55 * if the optical module LOS signal is used as an input to the micro
56 * code, then the micro code will wait until the optical module
57 * LOS = 0 before turning on the adaptive equalizer.
58 * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
59 * while setting bit 0 to 0 disables power savings mode.
60 * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
61 * optical module LOS signal while setting bit 2 to 1 configures the
62 * device so that it will ignore the optical module LOS SPARE2_LSB = 0
65 /* enable power savings, ignore optical module LOS */
66 {VILLA_MSEQ_SPARE2_LSB, 0x5},
68 {VILLA_MSEQ_SPARE7_LSB, 0x1e},
69 {VILLA_MSEQ_BANKSELECT, 0x4},
70 {VILLA_MSEQ_SPARE9_LSB, 0x2},
71 {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
72 {VILLA_MSEQ_SPARE3_MSB, 0x2006},
73 {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
74 {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
75 {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
76 {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
77 {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
78 {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
79 {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
80 {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
81 {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
82 {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
83 {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
84 {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
85 {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
86 {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
87 {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
88 {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
89 {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
90 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
91 {VILLA_MSEQ_OPTIONS, 0x7},
93 /* set up min value for ffe1 */
94 {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
95 {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
97 /* CS4315_sr_rx_pre_eq_set_4in */
98 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
99 {VILLA_MSEQ_OPTIONS, 0xf},
100 {VILLA_MSEQ_BANKSELECT, 0x4},
101 {VILLA_MSEQ_PC, 0x0},
103 /* for lengths from 3.5 to 4.5inches */
104 {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
105 {VILLA_MSEQ_SPARE25_LSB, 0x0306},
106 {VILLA_MSEQ_SPARE21_LSB, 0x2},
107 {VILLA_MSEQ_SPARE23_LSB, 0x2},
108 {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
110 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
111 {VILLA_MSEQ_OPTIONS, 0x7},
113 /* CS4315_rx_drive_4inch */
114 /* for length 4inches */
115 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
116 {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
117 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
119 /* CS4315_tx_drive_4inch */
120 /* for length 4inches */
121 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
122 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
123 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
126 void cs4340_upload_firmware(struct phy_device *phydev)
128 char line_temp[0x50] = {0};
129 char reg_addr[0x50] = {0};
130 char reg_data[0x50] = {0};
131 int i, line_cnt = 0, column_cnt = 0;
132 struct cortina_reg_config fw_temp;
135 #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
136 defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
138 addr = (char *)CONFIG_CORTINA_FW_ADDR;
139 #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
141 size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
143 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
144 ret = nand_read(get_nand_dev_by_index(0),
145 (loff_t)CONFIG_CORTINA_FW_ADDR,
146 &fw_length, (u_char *)addr);
147 if (ret == -EUCLEAN) {
148 printf("NAND read of Cortina firmware at 0x%x failed %d\n",
149 CONFIG_CORTINA_FW_ADDR, ret);
151 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
153 struct spi_flash *ucode_flash;
155 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
156 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
157 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
159 puts("SF: probe for Cortina ucode failed\n");
161 ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
162 CONFIG_CORTINA_FW_LENGTH, addr);
164 puts("SF: read for Cortina ucode failed\n");
165 spi_flash_free(ucode_flash);
167 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
168 int dev = CONFIG_SYS_MMC_ENV_DEV;
169 u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
170 u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
171 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
174 puts("Failed to find MMC device for Cortina ucode\n");
176 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
177 printf("MMC read: dev # %u, block # %u, count %u ...\n",
181 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
184 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
190 while (*addr != 'Q') {
193 while (*addr != 0x0a) {
194 line_temp[i++] = *addr++;
196 printf("Not found Cortina PHY ucode at 0x%p\n",
197 (char *)CONFIG_CORTINA_FW_ADDR);
202 addr++; /* skip '\n' */
205 line_temp[column_cnt] = '\0';
207 if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
210 for (i = 0; i < column_cnt; i++) {
211 if (isspace(line_temp[i++]))
215 memcpy(reg_addr, line_temp, i);
216 memcpy(reg_data, &line_temp[i], column_cnt - i);
219 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
220 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
222 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
227 int cs4340_phy_init(struct phy_device *phydev)
229 #ifndef CORTINA_NO_FW_UPLOAD
230 int timeout = 100; /* 100ms */
235 * Cortina phy has provision to store
236 * phy firmware in attached dedicated EEPROM.
237 * Boards designed with EEPROM attached to Cortina
238 * does not require FW upload.
240 #ifndef CORTINA_NO_FW_UPLOAD
241 /* step1: BIST test */
242 phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
243 phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
244 phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
246 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
247 if (reg_value & mseq_edc_bist_done) {
248 if (0 == (reg_value & mseq_edc_bist_fail))
255 printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
259 /* setp2: upload ucode */
260 cs4340_upload_firmware(phydev);
262 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
264 debug("%s checksum status failed.\n", __func__);
271 int cs4340_config(struct phy_device *phydev)
273 cs4340_phy_init(phydev);
277 int cs4340_probe(struct phy_device *phydev)
279 phydev->flags = PHY_FLAG_BROKEN_RESET;
283 int cs4340_startup(struct phy_device *phydev)
287 /* For now just lie and say it's 10G all the time */
288 phydev->speed = SPEED_10000;
289 phydev->duplex = DUPLEX_FULL;
293 int cs4223_phy_init(struct phy_device *phydev)
297 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
298 if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
299 printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
306 int cs4223_config(struct phy_device *phydev)
308 return cs4223_phy_init(phydev);
311 int cs4223_probe(struct phy_device *phydev)
313 phydev->flags = PHY_FLAG_BROKEN_RESET;
317 int cs4223_startup(struct phy_device *phydev)
320 phydev->speed = SPEED_10000;
321 phydev->duplex = DUPLEX_FULL;
325 struct phy_driver cs4340_driver = {
326 .name = "Cortina CS4315/CS4340",
327 .uid = PHY_UID_CS4340,
329 .features = PHY_10G_FEATURES,
330 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
331 MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
332 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
333 .config = &cs4340_config,
334 .probe = &cs4340_probe,
335 .startup = &cs4340_startup,
336 .shutdown = &gen10g_shutdown,
339 struct phy_driver cs4223_driver = {
340 .name = "Cortina CS4223",
341 .uid = PHY_UID_CS4223,
343 .features = PHY_10G_FEATURES,
344 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
346 .config = &cs4223_config,
347 .probe = &cs4223_probe,
348 .startup = &cs4223_startup,
349 .shutdown = &gen10g_shutdown,
352 int phy_cortina_init(void)
354 phy_register(&cs4340_driver);
355 phy_register(&cs4223_driver);
359 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
363 /* Cortina PHY has non-standard offset of PHY ID registers */
364 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
367 *phy_id = (phy_reg & 0xffff) << 16;
369 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
372 *phy_id |= (phy_reg & 0xffff);
374 if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
378 * If Cortina PHY not detected,
379 * try generic way to find PHY ID registers
381 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
384 *phy_id = (phy_reg & 0xffff) << 16;
386 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
389 *phy_id |= (phy_reg & 0xffff);