drivers/net/phy/atheros.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Atheros PHY drivers
   4  *
   5  * Copyright 2011, 2013 Freescale Semiconductor, Inc.
   6  * author Andy Fleming
   7  */
   8 #include <common.h>
   9 #include <phy.h>
  10
  11 #define AR803x_PHY_DEBUG_ADDR_REG       0x1d
  12 #define AR803x_PHY_DEBUG_DATA_REG       0x1e
  13
  14 #define AR803x_DEBUG_REG_5              0x5
  15 #define AR803x_RGMII_TX_CLK_DLY         BIT(8)
  16
  17 #define AR803x_DEBUG_REG_0              0x0
  18 #define AR803x_RGMII_RX_CLK_DLY         BIT(15)
  19
  20 /* CLK_25M register is at MMD 7, address 0x8016 */
  21 #define AR803x_CLK_25M_SEL_REG          0x8016
  22 /* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
  23 #define AR8035_CLK_25M_FREQ_25M         (0 | 0)
  24 #define AR8035_CLK_25M_FREQ_50M         (0 | BIT(3))
  25 #define AR8035_CLK_25M_FREQ_62M         (BIT(4) | 0)
  26 #define AR8035_CLK_25M_FREQ_125M        (BIT(4) | BIT(3))
  27 #define AR8035_CLK_25M_MASK             GENMASK(4, 3)
  28
  29 static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
  30 {
  31         int regval;
  32
  33         phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
  34                   AR803x_DEBUG_REG_0);
  35         regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
  36         if (on)
  37                 regval |= AR803x_RGMII_RX_CLK_DLY;
  38         else
  39                 regval &= ~AR803x_RGMII_RX_CLK_DLY;
  40         phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
  41 }
  42
  43 static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
  44 {
  45         int regval;
  46
  47         phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
  48                   AR803x_DEBUG_REG_5);
  49         regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
  50         if (on)
  51                 regval |= AR803x_RGMII_TX_CLK_DLY;
  52         else
  53                 regval &= ~AR803x_RGMII_TX_CLK_DLY;
  54         phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
  55 }
  56
  57 static int ar8021_config(struct phy_device *phydev)
  58 {
  59         phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
  60                   BMCR_ANENABLE | BMCR_ANRESTART);
  61
  62         ar803x_enable_tx_delay(phydev, true);
  63
  64         phydev->supported = phydev->drv->features;
  65         return 0;
  66 }
  67
  68 static int ar8031_config(struct phy_device *phydev)
  69 {
  70         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
  71             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  72                 ar803x_enable_tx_delay(phydev, true);
  73         else
  74                 ar803x_enable_tx_delay(phydev, false);
  75
  76         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
  77             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  78                 ar803x_enable_rx_delay(phydev, true);
  79         else
  80                 ar803x_enable_rx_delay(phydev, false);
  81
  82         phydev->supported = phydev->drv->features;
  83
  84         genphy_config_aneg(phydev);
  85         genphy_restart_aneg(phydev);
  86
  87         return 0;
  88 }
  89
  90 static int ar8035_config(struct phy_device *phydev)
  91 {
  92         int regval;
  93
  94         /* Configure CLK_25M output clock at 125 MHz */
  95         regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
  96         regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
  97         regval |= AR8035_CLK_25M_FREQ_125M;
  98         phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
  99
 100         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 101             (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 102                 ar803x_enable_tx_delay(phydev, true);
 103         else
 104                 ar803x_enable_tx_delay(phydev, false);
 105
 106         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 107             (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 108                 ar803x_enable_rx_delay(phydev, true);
 109         else
 110                 ar803x_enable_rx_delay(phydev, false);
 111
 112         phydev->supported = phydev->drv->features;
 113
 114         genphy_config_aneg(phydev);
 115         genphy_restart_aneg(phydev);
 116
 117         return 0;
 118 }
 119
 120 static struct phy_driver AR8021_driver =  {
 121         .name = "AR8021",
 122         .uid = 0x4dd040,
 123         .mask = 0x4ffff0,
 124         .features = PHY_GBIT_FEATURES,
 125         .config = ar8021_config,
 126         .startup = genphy_startup,
 127         .shutdown = genphy_shutdown,
 128 };
 129
 130 static struct phy_driver AR8031_driver =  {
 131         .name = "AR8031/AR8033",
 132         .uid = 0x4dd074,
 133         .mask = 0xffffffef,
 134         .features = PHY_GBIT_FEATURES,
 135         .config = ar8031_config,
 136         .startup = genphy_startup,
 137         .shutdown = genphy_shutdown,
 138 };
 139
 140 static struct phy_driver AR8035_driver =  {
 141         .name = "AR8035",
 142         .uid = 0x4dd072,
 143         .mask = 0xffffffef,
 144         .features = PHY_GBIT_FEATURES,
 145         .config = ar8035_config,
 146         .startup = genphy_startup,
 147         .shutdown = genphy_shutdown,
 148 };
 149
 150 int phy_atheros_init(void)
 151 {
 152         phy_register(&AR8021_driver);
 153         phy_register(&AR8031_driver);
 154         phy_register(&AR8035_driver);
 155
 156         return 0;
 157 }