drivers/net/phy/aquantia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Aquantia PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8 #include <config.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <net.h>
  13 #include <phy.h>
  14 #include <u-boot/crc.h>
  15 #include <malloc.h>
  16 #include <asm/byteorder.h>
  17 #include <fs.h>
  18
  19 #define AQUNTIA_10G_CTL         0x20
  20 #define AQUNTIA_VENDOR_P1       0xc400
  21
  22 #define AQUNTIA_SPEED_LSB_MASK  0x2000
  23 #define AQUNTIA_SPEED_MSB_MASK  0x40
  24
  25 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
  26 #define  AQUANTIA_SYSTEM_INTERFACE_SR_READY     BIT(0)
  27 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  28 #define AQUANTIA_FIRMWARE_ID             0x20
  29 #define AQUANTIA_RESERVED_STATUS         0xc885
  30 #define AQUANTIA_FIRMWARE_MAJOR_MASK     0xff00
  31 #define AQUANTIA_FIRMWARE_MINOR_MASK     0xff
  32 #define AQUANTIA_FIRMWARE_BUILD_MASK     0xf0
  33
  34 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  35 #define AQUANTIA_SI_IN_USE_MASK          0x0078
  36 #define AQUANTIA_SI_USXGMII              0x0018
  37
  38 /* registers in MDIO_MMD_VEND1 region */
  39 #define AQUANTIA_VND1_GLOBAL_SC                 0x000
  40 #define  AQUANTIA_VND1_GLOBAL_SC_LP             BIT(0xb)
  41
  42 #define GLOBAL_FIRMWARE_ID 0x20
  43 #define GLOBAL_FAULT 0xc850
  44 #define GLOBAL_RSTATUS_1 0xc885
  45
  46 #define GLOBAL_ALARM_1 0xcc00
  47 #define SYSTEM_READY_BIT 0x40
  48
  49 #define GLOBAL_STANDARD_CONTROL 0x0
  50 #define SOFT_RESET BIT(15)
  51 #define LOW_POWER BIT(11)
  52
  53 #define MAILBOX_CONTROL 0x0200
  54 #define MAILBOX_EXECUTE BIT(15)
  55 #define MAILBOX_WRITE BIT(14)
  56 #define MAILBOX_RESET_CRC BIT(12)
  57 #define MAILBOX_BUSY BIT(8)
  58
  59 #define MAILBOX_CRC 0x0201
  60
  61 #define MAILBOX_ADDR_MSW 0x0202
  62 #define MAILBOX_ADDR_LSW 0x0203
  63
  64 #define MAILBOX_DATA_MSW 0x0204
  65 #define MAILBOX_DATA_LSW 0x0205
  66
  67 #define UP_CONTROL 0xc001
  68 #define UP_RESET BIT(15)
  69 #define UP_RUN_STALL_OVERRIDE BIT(6)
  70 #define UP_RUN_STALL BIT(0)
  71
  72 #define AQUANTIA_PMA_RX_VENDOR_P1               0xe400
  73 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK      GENMASK(1, 0)
  74 /* MDI reversal configured through registers */
  75 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG      BIT(1)
  76 /* MDI reversal enabled */
  77 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV      BIT(0)
  78
  79 /*
  80  * global start rate, the protocol associated with this speed is used by default
  81  * on SI.
  82  */
  83 #define AQUANTIA_VND1_GSTART_RATE               0x31a
  84 #define  AQUANTIA_VND1_GSTART_RATE_OFF          0
  85 #define  AQUANTIA_VND1_GSTART_RATE_100M         1
  86 #define  AQUANTIA_VND1_GSTART_RATE_1G           2
  87 #define  AQUANTIA_VND1_GSTART_RATE_10G          3
  88 #define  AQUANTIA_VND1_GSTART_RATE_2_5G         4
  89 #define  AQUANTIA_VND1_GSTART_RATE_5G           5
  90
  91 /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  92 #define AQUANTIA_VND1_GSYSCFG_BASE              0x31b
  93 #define AQUANTIA_VND1_GSYSCFG_100M              0
  94 #define AQUANTIA_VND1_GSYSCFG_1G                1
  95 #define AQUANTIA_VND1_GSYSCFG_2_5G              2
  96 #define AQUANTIA_VND1_GSYSCFG_5G                3
  97 #define AQUANTIA_VND1_GSYSCFG_10G               4
  98
  99 #define AQUANTIA_VND1_SMBUS0                    0xc485
 100 #define AQUANTIA_VND1_SMBUS1                    0xc495
 101
 102 /* addresses of memory segments in the phy */
 103 #define DRAM_BASE_ADDR 0x3FFE0000
 104 #define IRAM_BASE_ADDR 0x40000000
 105
 106 /* firmware image format constants */
 107 #define VERSION_STRING_SIZE 0x40
 108 #define VERSION_STRING_OFFSET 0x0200
 109 #define HEADER_OFFSET 0x300
 110
 111 /* driver private data */
 112 #define AQUANTIA_NA             0
 113 #define AQUANTIA_GEN1           1
 114 #define AQUANTIA_GEN2           2
 115 #define AQUANTIA_GEN3           3
 116
 117 #pragma pack(1)
 118 struct fw_header {
 119         u8 padding[4];
 120         u8 iram_offset[3];
 121         u8 iram_size[3];
 122         u8 dram_offset[3];
 123         u8 dram_size[3];
 124 };
 125
 126 #pragma pack()
 127
 128 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
 129 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
 130 {
 131         loff_t length, read;
 132         int ret;
 133         void *addr = NULL;
 134
 135         *fw_addr = NULL;
 136         *fw_length = 0;
 137         debug("Loading Acquantia microcode from %s %s\n",
 138               CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
 139         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 140         if (ret < 0)
 141                 goto cleanup;
 142
 143         ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
 144         if (ret < 0)
 145                 goto cleanup;
 146
 147         addr = malloc(length);
 148         if (!addr) {
 149                 ret = -ENOMEM;
 150                 goto cleanup;
 151         }
 152
 153         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 154         if (ret < 0)
 155                 goto cleanup;
 156
 157         ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
 158                       &read);
 159         if (ret < 0)
 160                 goto cleanup;
 161
 162         *fw_addr = addr;
 163         *fw_length = length;
 164         debug("Found Acquantia microcode.\n");
 165
 166 cleanup:
 167         if (ret < 0) {
 168                 printf("loading firmware file %s %s failed with error %d\n",
 169                        CONFIG_PHY_AQUANTIA_FW_PART,
 170                        CONFIG_PHY_AQUANTIA_FW_NAME, ret);
 171                 free(addr);
 172         }
 173         return ret;
 174 }
 175
 176 /* load data into the phy's memory */
 177 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
 178                                 const u8 *data, size_t len)
 179 {
 180         size_t pos;
 181         u16 crc = 0, up_crc;
 182
 183         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
 184         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
 185         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
 186
 187         for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
 188                 u32 word = 0;
 189
 190                 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
 191
 192                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
 193                           (word >> 16));
 194                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
 195                           word & 0xffff);
 196
 197                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
 198                           MAILBOX_EXECUTE | MAILBOX_WRITE);
 199
 200                 /* keep a big endian CRC to match the phy processor */
 201                 word = cpu_to_be32(word);
 202                 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
 203         }
 204
 205         up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
 206         if (crc != up_crc) {
 207                 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
 208                        phydev->dev->name, crc, up_crc);
 209                 return -EINVAL;
 210         }
 211         return 0;
 212 }
 213
 214 static u32 unpack_u24(const u8 *data)
 215 {
 216         return (data[2] << 16) + (data[1] << 8) + data[0];
 217 }
 218
 219 static int aquantia_upload_firmware(struct phy_device *phydev)
 220 {
 221         int ret;
 222         u8 *addr = NULL;
 223         size_t fw_length = 0;
 224         u16 calculated_crc, read_crc;
 225         char version[VERSION_STRING_SIZE];
 226         u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
 227         const struct fw_header *header;
 228
 229         ret = aquantia_read_fw(&addr, &fw_length);
 230         if (ret != 0)
 231                 return ret;
 232
 233         read_crc = (addr[fw_length - 2] << 8)  | addr[fw_length - 1];
 234         calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
 235         if (read_crc != calculated_crc) {
 236                 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
 237                        phydev->dev->name, read_crc, calculated_crc);
 238                 ret = -EINVAL;
 239                 goto done;
 240         }
 241
 242         /* Find the DRAM and IRAM sections within the firmware file. */
 243         primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
 244
 245         header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
 246
 247         iram_offset = primary_offset + unpack_u24(header->iram_offset);
 248         iram_size = unpack_u24(header->iram_size);
 249
 250         dram_offset = primary_offset + unpack_u24(header->dram_offset);
 251         dram_size = unpack_u24(header->dram_size);
 252
 253         debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
 254               primary_offset, iram_offset, iram_size, dram_offset, dram_size);
 255
 256         strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
 257                 VERSION_STRING_SIZE);
 258         printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
 259
 260         /* stall the microcprocessor */
 261         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 262                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
 263
 264         debug("loading dram 0x%08x from offset=%d size=%d\n",
 265               DRAM_BASE_ADDR, dram_offset, dram_size);
 266         ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
 267                                    dram_size);
 268         if (ret != 0)
 269                 goto done;
 270
 271         debug("loading iram 0x%08x from offset=%d size=%d\n",
 272               IRAM_BASE_ADDR, iram_offset, iram_size);
 273         ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
 274                                    iram_size);
 275         if (ret != 0)
 276                 goto done;
 277
 278         /* make sure soft reset and low power mode are clear */
 279         phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
 280
 281         /* Release the microprocessor. UP_RESET must be held for 100 usec. */
 282         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 283                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
 284
 285         udelay(100);
 286
 287         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
 288
 289         printf("%s firmare loading done.\n", phydev->dev->name);
 290 done:
 291         free(addr);
 292         return ret;
 293 }
 294 #else
 295 static int aquantia_upload_firmware(struct phy_device *phydev)
 296 {
 297         printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
 298         return -1;
 299 }
 300 #endif
 301
 302 struct {
 303         u16 syscfg;
 304         int cnt;
 305         u16 start_rate;
 306 } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
 307         [PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
 308                                            AQUANTIA_VND1_GSTART_RATE_1G},
 309         [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
 310                                            AQUANTIA_VND1_GSTART_RATE_2_5G},
 311         [PHY_INTERFACE_MODE_XFI] =        {0x100, AQUANTIA_VND1_GSYSCFG_10G,
 312                                            AQUANTIA_VND1_GSTART_RATE_10G},
 313         [PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
 314                                            AQUANTIA_VND1_GSTART_RATE_10G},
 315 };
 316
 317 static int aquantia_set_proto(struct phy_device *phydev,
 318                               phy_interface_t interface)
 319 {
 320         int i;
 321
 322         if (!aquantia_syscfg[interface].cnt)
 323                 return 0;
 324
 325         /* set the default rate to enable the SI link */
 326         phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
 327                   aquantia_syscfg[interface].start_rate);
 328
 329         /* set selected protocol for all relevant line side link speeds */
 330         for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
 331                 phy_write(phydev, MDIO_MMD_VEND1,
 332                           AQUANTIA_VND1_GSYSCFG_BASE + i,
 333                           aquantia_syscfg[interface].syscfg);
 334         return 0;
 335 }
 336
 337 static int aquantia_dts_config(struct phy_device *phydev)
 338 {
 339 #ifdef CONFIG_DM_ETH
 340         ofnode node = phydev->node;
 341         u32 prop;
 342         u16 reg;
 343
 344         /* this code only works on gen2 and gen3 PHYs */
 345         if (phydev->drv->data != AQUANTIA_GEN2 &&
 346             phydev->drv->data != AQUANTIA_GEN3)
 347                 return -ENOTSUPP;
 348
 349         if (!ofnode_valid(node))
 350                 return 0;
 351
 352         if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
 353                 debug("mdi-reversal = %d\n", (int)prop);
 354                 reg =  phy_read(phydev, MDIO_MMD_PMAPMD,
 355                                 AQUANTIA_PMA_RX_VENDOR_P1);
 356                 reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
 357                 reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
 358                 reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
 359                 phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
 360                           reg);
 361         }
 362         if (!ofnode_read_u32(node, "smb-addr", &prop)) {
 363                 debug("smb-addr = %x\n", (int)prop);
 364                 /*
 365                  * there are two addresses here, normally just one bus would
 366                  * be in use so we're setting both regs using the same DT
 367                  * property.
 368                  */
 369                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
 370                           (u16)(prop << 1));
 371                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
 372                           (u16)(prop << 1));
 373         }
 374
 375 #endif
 376         return 0;
 377 }
 378
 379 static bool aquantia_link_is_up(struct phy_device *phydev)
 380 {
 381         u16 reg, regmask;
 382         int devad, regnum;
 383
 384         /*
 385          * On Gen 2 and 3 we have a bit that indicates that both system and
 386          * line side are ready for data, use that if possible.
 387          */
 388         if (phydev->drv->data == AQUANTIA_GEN2 ||
 389             phydev->drv->data == AQUANTIA_GEN3) {
 390                 devad = MDIO_MMD_PHYXS;
 391                 regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
 392                 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
 393         } else {
 394                 devad = MDIO_MMD_AN;
 395                 regnum = MDIO_STAT1;
 396                 regmask = MDIO_AN_STAT1_COMPLETE;
 397         }
 398         /* the register should be latched, do a double read */
 399         phy_read(phydev, devad, regnum);
 400         reg = phy_read(phydev, devad, regnum);
 401
 402         return !!(reg & regmask);
 403 }
 404
 405 int aquantia_config(struct phy_device *phydev)
 406 {
 407         int interface = phydev->interface;
 408         u32 val, id, rstatus, fault;
 409         u32 reg_val1 = 0;
 410         int num_retries = 5;
 411         int usx_an = 0;
 412
 413         /*
 414          * check if the system is out of reset and init sequence completed.
 415          * chip-wide reset for gen1 quad phys takes longer
 416          */
 417         while (--num_retries) {
 418                 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
 419                 if (rstatus & SYSTEM_READY_BIT)
 420                         break;
 421                 mdelay(10);
 422         }
 423
 424         id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
 425         rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
 426         fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
 427
 428         if (id != 0)
 429                 debug("%s running firmware version %X.%X.%X\n",
 430                       phydev->dev->name, (id >> 8), id & 0xff,
 431                       (rstatus >> 4) & 0xf);
 432
 433         if (fault != 0)
 434                 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
 435
 436         if (id == 0 || fault != 0) {
 437                 int ret;
 438
 439                 ret = aquantia_upload_firmware(phydev);
 440                 if (ret != 0)
 441                         return ret;
 442         }
 443         /*
 444          * for backward compatibility convert XGMII into either XFI or USX based
 445          * on FW config
 446          */
 447         if (interface == PHY_INTERFACE_MODE_XGMII) {
 448                 debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
 449
 450                 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
 451                                     AQUANTIA_SYSTEM_INTERFACE_SR);
 452                 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
 453                         interface = PHY_INTERFACE_MODE_USXGMII;
 454                 else
 455                         interface = PHY_INTERFACE_MODE_XFI;
 456         }
 457
 458         /*
 459          * if link is up already we can just use it, otherwise configure
 460          * the protocols in the PHY.  If link is down set the system
 461          * interface protocol to use based on phydev->interface
 462          */
 463         if (!aquantia_link_is_up(phydev) &&
 464             (phydev->drv->data == AQUANTIA_GEN2 ||
 465              phydev->drv->data == AQUANTIA_GEN3)) {
 466                 /* set PHY in low power mode so we can configure protocols */
 467                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
 468                           AQUANTIA_VND1_GLOBAL_SC_LP);
 469                 mdelay(10);
 470
 471                 /* configure protocol based on phydev->interface */
 472                 aquantia_set_proto(phydev, interface);
 473                 /* apply custom configuration based on DT */
 474                 aquantia_dts_config(phydev);
 475
 476                 /* wake PHY back up */
 477                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
 478                 mdelay(10);
 479         }
 480
 481         val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 482
 483         switch (interface) {
 484         case PHY_INTERFACE_MODE_SGMII:
 485                 /* 1000BASE-T mode */
 486                 phydev->advertising = SUPPORTED_1000baseT_Full;
 487                 phydev->supported = phydev->advertising;
 488
 489                 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
 490                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 491                 break;
 492         case PHY_INTERFACE_MODE_USXGMII:
 493                 usx_an = 1;
 494                 /* FALLTHROUGH */
 495         case PHY_INTERFACE_MODE_XFI:
 496                 /* 10GBASE-T mode */
 497                 phydev->advertising = SUPPORTED_10000baseT_Full;
 498                 phydev->supported = phydev->advertising;
 499
 500                 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
 501                     !(val & AQUNTIA_SPEED_MSB_MASK))
 502                         phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
 503                                   AQUNTIA_SPEED_LSB_MASK |
 504                                   AQUNTIA_SPEED_MSB_MASK);
 505
 506                 /* If SI is USXGMII then start USXGMII autoneg */
 507                 reg_val1 =  phy_read(phydev, MDIO_MMD_PHYXS,
 508                                      AQUANTIA_VENDOR_PROVISIONING_REG);
 509
 510                 if (usx_an) {
 511                         reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 512                         debug("%s: system interface USXGMII\n",
 513                               phydev->dev->name);
 514                 } else {
 515                         reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 516                         debug("%s: system interface XFI\n",
 517                               phydev->dev->name);
 518                 }
 519
 520                 phy_write(phydev, MDIO_MMD_PHYXS,
 521                           AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
 522                 break;
 523         case PHY_INTERFACE_MODE_SGMII_2500:
 524                 /* 2.5GBASE-T mode */
 525                 phydev->advertising = SUPPORTED_1000baseT_Full;
 526                 phydev->supported = phydev->advertising;
 527
 528                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
 529                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
 530                 break;
 531         case PHY_INTERFACE_MODE_MII:
 532                 /* 100BASE-TX mode */
 533                 phydev->advertising = SUPPORTED_100baseT_Full;
 534                 phydev->supported = phydev->advertising;
 535
 536                 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
 537                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 538                 break;
 539         };
 540
 541         val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
 542         reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
 543
 544         debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
 545               phydev->drv->name,
 546               (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
 547               reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
 548               (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
 549
 550         return 0;
 551 }
 552
 553 int aquantia_startup(struct phy_device *phydev)
 554 {
 555         u32 reg, speed;
 556         int i = 0;
 557
 558         phydev->duplex = DUPLEX_FULL;
 559
 560         /* if the AN is still in progress, wait till timeout. */
 561         if (!aquantia_link_is_up(phydev)) {
 562                 printf("%s Waiting for PHY auto negotiation to complete",
 563                        phydev->dev->name);
 564                 do {
 565                         udelay(1000);
 566                         if ((i++ % 500) == 0)
 567                                 printf(".");
 568                 } while (!aquantia_link_is_up(phydev) &&
 569                          i < (4 * PHY_ANEG_TIMEOUT));
 570
 571                 if (i > PHY_ANEG_TIMEOUT)
 572                         printf(" TIMEOUT !\n");
 573         }
 574
 575         /* Read twice because link state is latched and a
 576          * read moves the current state into the register */
 577         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 578         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 579         if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
 580                 phydev->link = 0;
 581         else
 582                 phydev->link = 1;
 583
 584         speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 585         if (speed & AQUNTIA_SPEED_MSB_MASK) {
 586                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 587                         phydev->speed = SPEED_10000;
 588                 else
 589                         phydev->speed = SPEED_1000;
 590         } else {
 591                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 592                         phydev->speed = SPEED_100;
 593                 else
 594                         phydev->speed = SPEED_10;
 595         }
 596
 597         return 0;
 598 }
 599
 600 struct phy_driver aq1202_driver = {
 601         .name = "Aquantia AQ1202",
 602         .uid = 0x3a1b445,
 603         .mask = 0xfffffff0,
 604         .features = PHY_10G_FEATURES,
 605         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 606                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 607                         MDIO_MMD_VEND1),
 608         .config = &aquantia_config,
 609         .startup = &aquantia_startup,
 610         .shutdown = &gen10g_shutdown,
 611 };
 612
 613 struct phy_driver aq2104_driver = {
 614         .name = "Aquantia AQ2104",
 615         .uid = 0x3a1b460,
 616         .mask = 0xfffffff0,
 617         .features = PHY_10G_FEATURES,
 618         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 619                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 620                         MDIO_MMD_VEND1),
 621         .config = &aquantia_config,
 622         .startup = &aquantia_startup,
 623         .shutdown = &gen10g_shutdown,
 624 };
 625
 626 struct phy_driver aqr105_driver = {
 627         .name = "Aquantia AQR105",
 628         .uid = 0x3a1b4a2,
 629         .mask = 0xfffffff0,
 630         .features = PHY_10G_FEATURES,
 631         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 632                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 633                         MDIO_MMD_VEND1),
 634         .config = &aquantia_config,
 635         .startup = &aquantia_startup,
 636         .shutdown = &gen10g_shutdown,
 637         .data = AQUANTIA_GEN1,
 638 };
 639
 640 struct phy_driver aqr106_driver = {
 641         .name = "Aquantia AQR106",
 642         .uid = 0x3a1b4d0,
 643         .mask = 0xfffffff0,
 644         .features = PHY_10G_FEATURES,
 645         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 646                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 647                         MDIO_MMD_VEND1),
 648         .config = &aquantia_config,
 649         .startup = &aquantia_startup,
 650         .shutdown = &gen10g_shutdown,
 651 };
 652
 653 struct phy_driver aqr107_driver = {
 654         .name = "Aquantia AQR107",
 655         .uid = 0x3a1b4e0,
 656         .mask = 0xfffffff0,
 657         .features = PHY_10G_FEATURES,
 658         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 659                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 660                         MDIO_MMD_VEND1),
 661         .config = &aquantia_config,
 662         .startup = &aquantia_startup,
 663         .shutdown = &gen10g_shutdown,
 664         .data = AQUANTIA_GEN2,
 665 };
 666
 667 struct phy_driver aqr112_driver = {
 668         .name = "Aquantia AQR112",
 669         .uid = 0x3a1b660,
 670         .mask = 0xfffffff0,
 671         .features = PHY_10G_FEATURES,
 672         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 673                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 674                  MDIO_MMD_VEND1),
 675         .config = &aquantia_config,
 676         .startup = &aquantia_startup,
 677         .shutdown = &gen10g_shutdown,
 678         .data = AQUANTIA_GEN3,
 679 };
 680
 681 struct phy_driver aqr405_driver = {
 682         .name = "Aquantia AQR405",
 683         .uid = 0x3a1b4b2,
 684         .mask = 0xfffffff0,
 685         .features = PHY_10G_FEATURES,
 686         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 687                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 688                  MDIO_MMD_VEND1),
 689         .config = &aquantia_config,
 690         .startup = &aquantia_startup,
 691         .shutdown = &gen10g_shutdown,
 692         .data = AQUANTIA_GEN1,
 693 };
 694
 695 struct phy_driver aqr412_driver = {
 696         .name = "Aquantia AQR412",
 697         .uid = 0x3a1b710,
 698         .mask = 0xfffffff0,
 699         .features = PHY_10G_FEATURES,
 700         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 701                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 702                  MDIO_MMD_VEND1),
 703         .config = &aquantia_config,
 704         .startup = &aquantia_startup,
 705         .shutdown = &gen10g_shutdown,
 706         .data = AQUANTIA_GEN3,
 707 };
 708
 709 int phy_aquantia_init(void)
 710 {
 711         phy_register(&aq1202_driver);
 712         phy_register(&aq2104_driver);
 713         phy_register(&aqr105_driver);
 714         phy_register(&aqr106_driver);
 715         phy_register(&aqr107_driver);
 716         phy_register(&aqr112_driver);
 717         phy_register(&aqr405_driver);
 718         phy_register(&aqr412_driver);
 719
 720         return 0;
 721 }