1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
9 #include <net/pfe_eth/pfe_eth.h>
10 #include <net/pfe_eth/pfe_firmware.h>
12 static struct tx_desc_s *g_tx_desc;
13 static struct rx_desc_s *g_rx_desc;
16 * HIF Rx interface function
17 * Reads the rx descriptor from the current location (rx_to_read).
18 * - If the descriptor has a valid data/pkt, then get the data pointer
19 * - check for the input rx phy number
20 * - increment the rx data pointer by pkt_head_room_size
21 * - decrement the data length by pkt_head_room_size
22 * - handover the packet to caller.
24 * @param[out] pkt_ptr - Pointer to store rx packet
25 * @param[out] phy_port - Pointer to store recv phy port
27 * @return -1 if no packet, else return length of packet.
29 int pfe_recv(uchar **pkt_ptr, int *phy_port)
31 struct rx_desc_s *rx_desc = g_rx_desc;
35 struct hif_header_s *hif_header;
37 bd = rx_desc->rx_base + rx_desc->rx_to_read;
39 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
40 return len; /* No pending Rx packet */
42 /* this len include hif_header(8 bytes) */
43 len = readl(&bd->ctrl) & 0xFFFF;
45 hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
47 /* Get the receive port info from the packet */
48 debug("Pkt received:");
49 debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
50 hif_header, len, hif_header->port_no, readl(&bd->status));
54 unsigned char *p = (unsigned char *)hif_header;
56 for (i = 0; i < len; i++) {
59 printf(" %02x", p[i]);
65 *pkt_ptr = (uchar *)(hif_header + 1);
66 *phy_port = hif_header->port_no;
67 len -= sizeof(struct hif_header_s);
73 * HIF function to check the Rx done
74 * This function will check the rx done indication of the current rx_to_read
76 * if success, moves the rx_to_read to next location.
78 int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
80 struct rx_desc_s *rx_desc = g_rx_desc;
83 debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
86 bd = rx_desc->rx_base + rx_desc->rx_to_read;
88 /* reset the control field */
89 writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
90 | BD_CTRL_DIR), &bd->ctrl);
91 writel(0, &bd->status);
93 debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
96 /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
97 * BDP need not wait for rx_poll_cycle time to fetch the descriptor,
98 * In idle state (ie., no rx pkt), BDP will not fetch
99 * the descriptor even if strobe is given.
101 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
103 /* increment the rx_to_read index to next location */
104 rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
105 & (rx_desc->rx_ring_size - 1);
107 debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
113 * HIF Tx interface function
114 * This function sends a single packet to PFE from HIF interface.
115 * - No interrupt indication on tx completion.
116 * - Data is copied to tx buffers before tx descriptor is updated
117 * and TX DMA is enabled.
119 * @param[in] phy_port Phy port number to send out this packet
120 * @param[in] data Pointer to the data
121 * @param[in] length Length of the ethernet packet to be transferred.
123 * @return -1 if tx Q is full, else returns the tx location where the pkt is
126 int pfe_send(int phy_port, void *data, int length)
128 struct tx_desc_s *tx_desc = g_tx_desc;
130 struct hif_header_s hif_header;
133 debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
134 data, length, tx_desc->tx_base, tx_desc->tx_to_send);
136 bd = tx_desc->tx_base + tx_desc->tx_to_send;
138 /* check queue-full condition */
139 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
142 /* PFE checks for min pkt size */
143 if (length < MIN_PKT_SIZE)
144 length = MIN_PKT_SIZE;
146 tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
147 debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
150 /* Fill the gemac/phy port number to send this packet out */
151 memset(&hif_header, 0, sizeof(struct hif_header_s));
152 hif_header.port_no = phy_port;
154 memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
155 memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
156 length += sizeof(struct hif_header_s);
161 unsigned char *p = (unsigned char *)tx_buf_va;
163 for (i = 0; i < length; i++) {
166 printf("%02x ", p[i]);
171 debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
174 /* fill the tx desc */
175 writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
177 writel(0, &bd->status);
179 writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
183 return tx_desc->tx_to_send;
187 * HIF function to check the Tx done
188 * This function will check the tx done indication of the current tx_to_send
190 * if success, moves the tx_to_send to next location.
192 * @return -1 if TX ownership bit is not cleared by hw.
193 * else on success (tx done completion) return zero.
195 int pfe_tx_done(void)
197 struct tx_desc_s *tx_desc = g_tx_desc;
200 debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
201 tx_desc->tx_to_send);
203 bd = tx_desc->tx_base + tx_desc->tx_to_send;
205 /* check queue-full condition */
206 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
209 /* reset the control field */
210 writel(0, &bd->ctrl);
211 writel(0, &bd->status);
213 debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
216 /* increment the txtosend index to next location */
217 tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
218 & (tx_desc->tx_ring_size - 1);
220 debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
226 * Helper function to dump Rx descriptors.
228 static inline void hif_rx_desc_dump(void)
230 struct buf_desc *bd_va;
232 struct rx_desc_s *rx_desc;
235 printf("%s: HIF Rx desc no init\n", __func__);
240 bd_va = rx_desc->rx_base;
242 debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
243 rx_desc->rx_base_pa);
244 for (i = 0; i < rx_desc->rx_ring_size; i++) {
245 debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
246 readl(&bd_va->status),
249 readl(&bd_va->next));
255 * This function mark all Rx descriptors as LAST_BD.
257 void hif_rx_desc_disable(void)
260 struct rx_desc_s *rx_desc;
261 struct buf_desc *bd_va;
264 printf("%s: HIF Rx desc not initialized\n", __func__);
269 bd_va = rx_desc->rx_base;
271 for (i = 0; i < rx_desc->rx_ring_size; i++) {
272 writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
278 * HIF Rx Desc initialization function.
280 static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
283 struct buf_desc *bd_va;
284 struct buf_desc *bd_pa;
285 struct rx_desc_s *rx_desc;
291 printf("%s: HIF Rx desc re-init request\n", __func__);
295 rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
297 printf("%s: Memory allocation failure\n", __func__);
300 memset(rx_desc, 0, sizeof(struct rx_desc_s));
302 /* init: Rx ring buffer */
303 rx_desc->rx_ring_size = HIF_RX_DESC_NT;
305 /* NOTE: must be 64bit aligned */
306 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
308 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
311 rx_desc->rx_base = bd_va;
312 rx_desc->rx_base_pa = (unsigned long)bd_pa;
314 rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
316 debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
317 __func__, rx_desc->rx_base, rx_desc->rx_base_pa,
318 rx_desc->rx_ring_size);
320 memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
322 ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
324 for (i = 0; i < rx_desc->rx_ring_size; i++) {
325 writel((unsigned long)(bd_pa + 1), &bd_va->next);
326 writel(ctrl, &bd_va->ctrl);
327 writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
332 writel((u32)rx_desc->rx_base_pa, &bd_va->next);
334 writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
335 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
343 * Helper function to dump Tx Descriptors.
345 static inline void hif_tx_desc_dump(void)
347 struct tx_desc_s *tx_desc;
349 struct buf_desc *bd_va;
352 printf("%s: HIF Tx desc no init\n", __func__);
357 bd_va = tx_desc->tx_base;
359 debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
360 tx_desc->tx_base_pa);
362 for (i = 0; i < tx_desc->tx_ring_size; i++)
367 * HIF Tx descriptor initialization function.
369 static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
371 struct buf_desc *bd_va;
372 struct buf_desc *bd_pa;
374 struct tx_desc_s *tx_desc;
379 printf("%s: HIF Tx desc re-init request\n", __func__);
383 tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
385 printf("%s:%d:Memory allocation failure\n", __func__,
389 memset(tx_desc, 0, sizeof(struct tx_desc_s));
391 /* init: Tx ring buffer */
392 tx_desc->tx_ring_size = HIF_TX_DESC_NT;
394 /* NOTE: must be 64bit aligned */
395 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
397 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
400 tx_desc->tx_base_pa = (unsigned long)bd_pa;
401 tx_desc->tx_base = bd_va;
403 debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
404 __func__, tx_desc->tx_base, tx_desc->tx_base_pa,
405 tx_desc->tx_ring_size);
407 memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
409 tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
411 for (i = 0; i < tx_desc->tx_ring_size; i++) {
412 writel((unsigned long)(bd_pa + 1), &bd_va->next);
413 writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
418 writel((u32)tx_desc->tx_base_pa, &bd_va->next);
420 writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
428 * PFE/Class initialization.
430 static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
432 struct class_cfg class_cfg = {
433 .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
434 ROUTE_TABLE_BASEADDR,
435 .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
438 class_init(&class_cfg);
440 debug("class init complete\n");
444 * PFE/TMU initialization.
446 static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
448 struct tmu_cfg tmu_cfg = {
449 .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
451 .llm_queue_len = TMU_LLM_QUEUE_LEN,
456 debug("tmu init complete\n");
460 * PFE/BMU (both BMU1 & BMU2) initialization.
462 static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
464 struct bmu_cfg bmu1_cfg = {
465 .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
467 .count = BMU1_BUF_COUNT,
468 .size = BMU1_BUF_SIZE,
471 struct bmu_cfg bmu2_cfg = {
472 .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
473 .count = BMU2_BUF_COUNT,
474 .size = BMU2_BUF_SIZE,
477 bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
478 debug("bmu1 init: done\n");
480 bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
481 debug("bmu2 init: done\n");
485 * PFE/GPI initialization function.
486 * - egpi1, egpi2, egpi3, hgpi
488 static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
490 struct gpi_cfg egpi1_cfg = {
491 .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
492 .tmlf_txthres = EGPI1_TMLF_TXTHRES,
493 .aseq_len = EGPI1_ASEQ_LEN,
496 struct gpi_cfg egpi2_cfg = {
497 .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
498 .tmlf_txthres = EGPI2_TMLF_TXTHRES,
499 .aseq_len = EGPI2_ASEQ_LEN,
502 struct gpi_cfg hgpi_cfg = {
503 .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
504 .tmlf_txthres = HGPI_TMLF_TXTHRES,
505 .aseq_len = HGPI_ASEQ_LEN,
508 gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
509 debug("GPI1 init complete\n");
511 gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
512 debug("GPI2 init complete\n");
514 gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
515 debug("HGPI init complete\n");
519 * PFE/HIF initialization function.
521 static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
528 ret = hif_tx_desc_init(pfe_addr);
531 ret = hif_rx_desc_init(pfe_addr);
543 debug("HIF init complete\n");
549 * - Firmware loading (CLASS-PE and TMU-PE)
550 * - BMU1 and BMU2 init
555 * - HIF tx and rx descriptors init
557 * @param[in] edev Pointer to eth device structure.
559 * @return 0, on success.
561 static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
565 debug("%s: start\n", __func__);
567 writel(0x3, CLASS_PE_SYS_CLK_RATIO);
568 writel(0x3, TMU_PE_SYS_CLK_RATIO);
569 writel(0x3, UTIL_PE_SYS_CLK_RATIO);
572 pfe_class_init(pfe_addr);
574 pfe_tmu_init(pfe_addr);
576 pfe_bmu_init(pfe_addr);
578 pfe_gpi_init(pfe_addr);
580 ret = pfe_hif_init(pfe_addr);
584 bmu_enable(BMU1_BASE_ADDR);
585 debug("bmu1 enabled\n");
587 bmu_enable(BMU2_BASE_ADDR);
588 debug("bmu2 enabled\n");
590 debug("%s: done\n", __func__);
596 * PFE driver init function.
597 * - Initializes pfe_lib
599 * - fw loading and enables PEs
600 * - should be executed once.
602 * @param[in] pfe Pointer the pfe control block
604 int pfe_drv_init(struct pfe_ddr_address *pfe_addr)
610 ret = pfe_hw_init(pfe_addr);
614 /* Load the class,TM, Util fw.
616 * - out of reset + disabled + configured.
617 * Fw loading should be done after pfe_hw_init()
619 /* It loads default inbuilt sbl firmware */
626 * PFE remove function
628 * - frees tx/rx descriptor resources
629 * - should be called once.
631 * @param[in] pfe Pointer to pfe control block.
633 int pfe_eth_remove(struct udevice *dev)