1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
9 #include <linux/delay.h>
10 #include <net/pfe_eth/pfe_eth.h>
11 #include <net/pfe_eth/pfe_firmware.h>
13 static struct tx_desc_s *g_tx_desc;
14 static struct rx_desc_s *g_rx_desc;
17 * HIF Rx interface function
18 * Reads the rx descriptor from the current location (rx_to_read).
19 * - If the descriptor has a valid data/pkt, then get the data pointer
20 * - check for the input rx phy number
21 * - increment the rx data pointer by pkt_head_room_size
22 * - decrement the data length by pkt_head_room_size
23 * - handover the packet to caller.
25 * @param[out] pkt_ptr - Pointer to store rx packet
26 * @param[out] phy_port - Pointer to store recv phy port
28 * @return -1 if no packet, else return length of packet.
30 int pfe_recv(uchar **pkt_ptr, int *phy_port)
32 struct rx_desc_s *rx_desc = g_rx_desc;
36 struct hif_header_s *hif_header;
38 bd = rx_desc->rx_base + rx_desc->rx_to_read;
40 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
41 return len; /* No pending Rx packet */
43 /* this len include hif_header(8 bytes) */
44 len = readl(&bd->ctrl) & 0xFFFF;
46 hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
48 /* Get the receive port info from the packet */
49 debug("Pkt received:");
50 debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
51 hif_header, len, hif_header->port_no, readl(&bd->status));
55 unsigned char *p = (unsigned char *)hif_header;
57 for (i = 0; i < len; i++) {
60 printf(" %02x", p[i]);
66 *pkt_ptr = (uchar *)(hif_header + 1);
67 *phy_port = hif_header->port_no;
68 len -= sizeof(struct hif_header_s);
74 * HIF function to check the Rx done
75 * This function will check the rx done indication of the current rx_to_read
77 * if success, moves the rx_to_read to next location.
79 int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
81 struct rx_desc_s *rx_desc = g_rx_desc;
84 debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
87 bd = rx_desc->rx_base + rx_desc->rx_to_read;
89 /* reset the control field */
90 writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
91 | BD_CTRL_DIR), &bd->ctrl);
92 writel(0, &bd->status);
94 debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
97 /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
98 * BDP need not wait for rx_poll_cycle time to fetch the descriptor,
99 * In idle state (ie., no rx pkt), BDP will not fetch
100 * the descriptor even if strobe is given.
102 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
104 /* increment the rx_to_read index to next location */
105 rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
106 & (rx_desc->rx_ring_size - 1);
108 debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
114 * HIF Tx interface function
115 * This function sends a single packet to PFE from HIF interface.
116 * - No interrupt indication on tx completion.
117 * - Data is copied to tx buffers before tx descriptor is updated
118 * and TX DMA is enabled.
120 * @param[in] phy_port Phy port number to send out this packet
121 * @param[in] data Pointer to the data
122 * @param[in] length Length of the ethernet packet to be transferred.
124 * @return -1 if tx Q is full, else returns the tx location where the pkt is
127 int pfe_send(int phy_port, void *data, int length)
129 struct tx_desc_s *tx_desc = g_tx_desc;
131 struct hif_header_s hif_header;
134 debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
135 data, length, tx_desc->tx_base, tx_desc->tx_to_send);
137 bd = tx_desc->tx_base + tx_desc->tx_to_send;
139 /* check queue-full condition */
140 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
143 /* PFE checks for min pkt size */
144 if (length < MIN_PKT_SIZE)
145 length = MIN_PKT_SIZE;
147 tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
148 debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
151 /* Fill the gemac/phy port number to send this packet out */
152 memset(&hif_header, 0, sizeof(struct hif_header_s));
153 hif_header.port_no = phy_port;
155 memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
156 memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
157 length += sizeof(struct hif_header_s);
162 unsigned char *p = (unsigned char *)tx_buf_va;
164 for (i = 0; i < length; i++) {
167 printf("%02x ", p[i]);
172 debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
175 /* fill the tx desc */
176 writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
178 writel(0, &bd->status);
180 writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
184 return tx_desc->tx_to_send;
188 * HIF function to check the Tx done
189 * This function will check the tx done indication of the current tx_to_send
191 * if success, moves the tx_to_send to next location.
193 * @return -1 if TX ownership bit is not cleared by hw.
194 * else on success (tx done completion) return zero.
196 int pfe_tx_done(void)
198 struct tx_desc_s *tx_desc = g_tx_desc;
201 debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
202 tx_desc->tx_to_send);
204 bd = tx_desc->tx_base + tx_desc->tx_to_send;
206 /* check queue-full condition */
207 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
210 /* reset the control field */
211 writel(0, &bd->ctrl);
212 writel(0, &bd->status);
214 debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
217 /* increment the txtosend index to next location */
218 tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
219 & (tx_desc->tx_ring_size - 1);
221 debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
227 * Helper function to dump Rx descriptors.
229 static inline void hif_rx_desc_dump(void)
231 struct buf_desc *bd_va;
233 struct rx_desc_s *rx_desc;
236 printf("%s: HIF Rx desc no init\n", __func__);
241 bd_va = rx_desc->rx_base;
243 debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
244 rx_desc->rx_base_pa);
245 for (i = 0; i < rx_desc->rx_ring_size; i++) {
246 debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
247 readl(&bd_va->status),
250 readl(&bd_va->next));
256 * This function mark all Rx descriptors as LAST_BD.
258 void hif_rx_desc_disable(void)
261 struct rx_desc_s *rx_desc;
262 struct buf_desc *bd_va;
265 printf("%s: HIF Rx desc not initialized\n", __func__);
270 bd_va = rx_desc->rx_base;
272 for (i = 0; i < rx_desc->rx_ring_size; i++) {
273 writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
279 * HIF Rx Desc initialization function.
281 static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
284 struct buf_desc *bd_va;
285 struct buf_desc *bd_pa;
286 struct rx_desc_s *rx_desc;
292 printf("%s: HIF Rx desc re-init request\n", __func__);
296 rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
298 printf("%s: Memory allocation failure\n", __func__);
301 memset(rx_desc, 0, sizeof(struct rx_desc_s));
303 /* init: Rx ring buffer */
304 rx_desc->rx_ring_size = HIF_RX_DESC_NT;
306 /* NOTE: must be 64bit aligned */
307 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
309 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
312 rx_desc->rx_base = bd_va;
313 rx_desc->rx_base_pa = (unsigned long)bd_pa;
315 rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
317 debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
318 __func__, rx_desc->rx_base, rx_desc->rx_base_pa,
319 rx_desc->rx_ring_size);
321 memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
323 ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
325 for (i = 0; i < rx_desc->rx_ring_size; i++) {
326 writel((unsigned long)(bd_pa + 1), &bd_va->next);
327 writel(ctrl, &bd_va->ctrl);
328 writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
333 writel((u32)rx_desc->rx_base_pa, &bd_va->next);
335 writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
336 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
344 * Helper function to dump Tx Descriptors.
346 static inline void hif_tx_desc_dump(void)
348 struct tx_desc_s *tx_desc;
350 struct buf_desc *bd_va;
353 printf("%s: HIF Tx desc no init\n", __func__);
358 bd_va = tx_desc->tx_base;
360 debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
361 tx_desc->tx_base_pa);
363 for (i = 0; i < tx_desc->tx_ring_size; i++)
368 * HIF Tx descriptor initialization function.
370 static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
372 struct buf_desc *bd_va;
373 struct buf_desc *bd_pa;
375 struct tx_desc_s *tx_desc;
380 printf("%s: HIF Tx desc re-init request\n", __func__);
384 tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
386 printf("%s:%d:Memory allocation failure\n", __func__,
390 memset(tx_desc, 0, sizeof(struct tx_desc_s));
392 /* init: Tx ring buffer */
393 tx_desc->tx_ring_size = HIF_TX_DESC_NT;
395 /* NOTE: must be 64bit aligned */
396 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
398 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
401 tx_desc->tx_base_pa = (unsigned long)bd_pa;
402 tx_desc->tx_base = bd_va;
404 debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
405 __func__, tx_desc->tx_base, tx_desc->tx_base_pa,
406 tx_desc->tx_ring_size);
408 memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
410 tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
412 for (i = 0; i < tx_desc->tx_ring_size; i++) {
413 writel((unsigned long)(bd_pa + 1), &bd_va->next);
414 writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
419 writel((u32)tx_desc->tx_base_pa, &bd_va->next);
421 writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
429 * PFE/Class initialization.
431 static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
433 struct class_cfg class_cfg = {
434 .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
435 ROUTE_TABLE_BASEADDR,
436 .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
439 class_init(&class_cfg);
441 debug("class init complete\n");
445 * PFE/TMU initialization.
447 static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
449 struct tmu_cfg tmu_cfg = {
450 .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
452 .llm_queue_len = TMU_LLM_QUEUE_LEN,
457 debug("tmu init complete\n");
461 * PFE/BMU (both BMU1 & BMU2) initialization.
463 static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
465 struct bmu_cfg bmu1_cfg = {
466 .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
468 .count = BMU1_BUF_COUNT,
469 .size = BMU1_BUF_SIZE,
472 struct bmu_cfg bmu2_cfg = {
473 .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
474 .count = BMU2_BUF_COUNT,
475 .size = BMU2_BUF_SIZE,
478 bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
479 debug("bmu1 init: done\n");
481 bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
482 debug("bmu2 init: done\n");
486 * PFE/GPI initialization function.
487 * - egpi1, egpi2, egpi3, hgpi
489 static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
491 struct gpi_cfg egpi1_cfg = {
492 .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
493 .tmlf_txthres = EGPI1_TMLF_TXTHRES,
494 .aseq_len = EGPI1_ASEQ_LEN,
497 struct gpi_cfg egpi2_cfg = {
498 .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
499 .tmlf_txthres = EGPI2_TMLF_TXTHRES,
500 .aseq_len = EGPI2_ASEQ_LEN,
503 struct gpi_cfg hgpi_cfg = {
504 .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
505 .tmlf_txthres = HGPI_TMLF_TXTHRES,
506 .aseq_len = HGPI_ASEQ_LEN,
509 gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
510 debug("GPI1 init complete\n");
512 gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
513 debug("GPI2 init complete\n");
515 gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
516 debug("HGPI init complete\n");
520 * PFE/HIF initialization function.
522 static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
529 ret = hif_tx_desc_init(pfe_addr);
532 ret = hif_rx_desc_init(pfe_addr);
544 debug("HIF init complete\n");
550 * - Firmware loading (CLASS-PE and TMU-PE)
551 * - BMU1 and BMU2 init
556 * - HIF tx and rx descriptors init
558 * @param[in] edev Pointer to eth device structure.
560 * @return 0, on success.
562 static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
566 debug("%s: start\n", __func__);
568 writel(0x3, CLASS_PE_SYS_CLK_RATIO);
569 writel(0x3, TMU_PE_SYS_CLK_RATIO);
570 writel(0x3, UTIL_PE_SYS_CLK_RATIO);
573 pfe_class_init(pfe_addr);
575 pfe_tmu_init(pfe_addr);
577 pfe_bmu_init(pfe_addr);
579 pfe_gpi_init(pfe_addr);
581 ret = pfe_hif_init(pfe_addr);
585 bmu_enable(BMU1_BASE_ADDR);
586 debug("bmu1 enabled\n");
588 bmu_enable(BMU2_BASE_ADDR);
589 debug("bmu2 enabled\n");
591 debug("%s: done\n", __func__);
597 * PFE driver init function.
598 * - Initializes pfe_lib
600 * - fw loading and enables PEs
601 * - should be executed once.
603 * @param[in] pfe Pointer the pfe control block
605 int pfe_drv_init(struct pfe_ddr_address *pfe_addr)
611 ret = pfe_hw_init(pfe_addr);
615 /* Load the class,TM, Util fw.
617 * - out of reset + disabled + configured.
618 * Fw loading should be done after pfe_hw_init()
620 /* It loads default inbuilt sbl firmware */
627 * PFE remove function
629 * - frees tx/rx descriptor resources
630 * - should be called once.
632 * @param[in] pfe Pointer to pfe control block.
634 int pfe_eth_remove(struct udevice *dev)