drivers/net/pcnet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
   4  *
   5  * This driver for AMD PCnet network controllers is derived from the
   6  * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <net.h>
  14 #include <netdev.h>
  15 #include <asm/cache.h>
  16 #include <asm/io.h>
  17 #include <pci.h>
  18
  19 #define PCNET_DEBUG_LEVEL       0       /* 0=off, 1=init, 2=rx/tx */
  20
  21 #define PCNET_DEBUG1(fmt,args...)       \
  22         debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
  23 #define PCNET_DEBUG2(fmt,args...)       \
  24         debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
  25
  26 /*
  27  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  28  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  29  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  30  */
  31 #define PCNET_LOG_TX_BUFFERS    0
  32 #define PCNET_LOG_RX_BUFFERS    2
  33
  34 #define TX_RING_SIZE            (1 << (PCNET_LOG_TX_BUFFERS))
  35 #define TX_RING_LEN_BITS        ((PCNET_LOG_TX_BUFFERS) << 12)
  36
  37 #define RX_RING_SIZE            (1 << (PCNET_LOG_RX_BUFFERS))
  38 #define RX_RING_LEN_BITS        ((PCNET_LOG_RX_BUFFERS) << 4)
  39
  40 #define PKT_BUF_SZ              1544
  41
  42 /* The PCNET Rx and Tx ring descriptors. */
  43 struct pcnet_rx_head {
  44         u32 base;
  45         s16 buf_length;
  46         s16 status;
  47         u32 msg_length;
  48         u32 reserved;
  49 };
  50
  51 struct pcnet_tx_head {
  52         u32 base;
  53         s16 length;
  54         s16 status;
  55         u32 misc;
  56         u32 reserved;
  57 };
  58
  59 /* The PCNET 32-Bit initialization block, described in databook. */
  60 struct pcnet_init_block {
  61         u16 mode;
  62         u16 tlen_rlen;
  63         u8 phys_addr[6];
  64         u16 reserved;
  65         u32 filter[2];
  66         /* Receive and transmit ring base, along with extra bits. */
  67         u32 rx_ring;
  68         u32 tx_ring;
  69         u32 reserved2;
  70 };
  71
  72 struct pcnet_uncached_priv {
  73         struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  74         struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  75         struct pcnet_init_block init_block;
  76 };
  77
  78 typedef struct pcnet_priv {
  79         struct pcnet_uncached_priv *uc;
  80         /* Receive Buffer space */
  81         unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
  82         int cur_rx;
  83         int cur_tx;
  84 } pcnet_priv_t;
  85
  86 static pcnet_priv_t *lp;
  87
  88 /* Offsets from base I/O address for WIO mode */
  89 #define PCNET_RDP               0x10
  90 #define PCNET_RAP               0x12
  91 #define PCNET_RESET             0x14
  92 #define PCNET_BDP               0x16
  93
  94 static u16 pcnet_read_csr(struct eth_device *dev, int index)
  95 {
  96         void __iomem *base = (void __iomem *)dev->iobase;
  97
  98         writew(index, base + PCNET_RAP);
  99         return readw(base + PCNET_RDP);
 100 }
 101
 102 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
 103 {
 104         void __iomem *base = (void __iomem *)dev->iobase;
 105
 106         writew(index, base + PCNET_RAP);
 107         writew(val, base + PCNET_RDP);
 108 }
 109
 110 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
 111 {
 112         void __iomem *base = (void __iomem *)dev->iobase;
 113
 114         writew(index, base + PCNET_RAP);
 115         return readw(base + PCNET_BDP);
 116 }
 117
 118 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
 119 {
 120         void __iomem *base = (void __iomem *)dev->iobase;
 121
 122         writew(index, base + PCNET_RAP);
 123         writew(val, base + PCNET_BDP);
 124 }
 125
 126 static void pcnet_reset(struct eth_device *dev)
 127 {
 128         void __iomem *base = (void __iomem *)dev->iobase;
 129
 130         readw(base + PCNET_RESET);
 131 }
 132
 133 static int pcnet_check(struct eth_device *dev)
 134 {
 135         void __iomem *base = (void __iomem *)dev->iobase;
 136
 137         writew(88, base + PCNET_RAP);
 138         return readw(base + PCNET_RAP) == 88;
 139 }
 140
 141 static int pcnet_init (struct eth_device *dev, bd_t * bis);
 142 static int pcnet_send(struct eth_device *dev, void *packet, int length);
 143 static int pcnet_recv (struct eth_device *dev);
 144 static void pcnet_halt (struct eth_device *dev);
 145 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 146
 147 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
 148                                                 void *addr)
 149 {
 150         pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
 151         void *virt_addr = addr;
 152
 153         return pci_virt_to_mem(devbusfn, virt_addr);
 154 }
 155
 156 static struct pci_device_id supported[] = {
 157         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
 158         {}
 159 };
 160
 161
 162 int pcnet_initialize(bd_t *bis)
 163 {
 164         pci_dev_t devbusfn;
 165         struct eth_device *dev;
 166         u16 command, status;
 167         int dev_nr = 0;
 168         u32 bar;
 169
 170         PCNET_DEBUG1("\npcnet_initialize...\n");
 171
 172         for (dev_nr = 0;; dev_nr++) {
 173
 174                 /*
 175                  * Find the PCnet PCI device(s).
 176                  */
 177                 devbusfn = pci_find_devices(supported, dev_nr);
 178                 if (devbusfn < 0)
 179                         break;
 180
 181                 /*
 182                  * Allocate and pre-fill the device structure.
 183                  */
 184                 dev = (struct eth_device *)malloc(sizeof(*dev));
 185                 if (!dev) {
 186                         printf("pcnet: Can not allocate memory\n");
 187                         break;
 188                 }
 189                 memset(dev, 0, sizeof(*dev));
 190                 dev->priv = (void *)(unsigned long)devbusfn;
 191                 sprintf(dev->name, "pcnet#%d", dev_nr);
 192
 193                 /*
 194                  * Setup the PCI device.
 195                  */
 196                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
 197                 dev->iobase = pci_mem_to_phys(devbusfn, bar);
 198                 dev->iobase &= ~0xf;
 199
 200                 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
 201                              dev->name, devbusfn, (unsigned long)dev->iobase);
 202
 203                 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 204                 pci_write_config_word(devbusfn, PCI_COMMAND, command);
 205                 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 206                 if ((status & command) != command) {
 207                         printf("%s: Couldn't enable IO access or Bus Mastering\n",
 208                                dev->name);
 209                         free(dev);
 210                         continue;
 211                 }
 212
 213                 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
 214
 215                 /*
 216                  * Probe the PCnet chip.
 217                  */
 218                 if (pcnet_probe(dev, bis, dev_nr) < 0) {
 219                         free(dev);
 220                         continue;
 221                 }
 222
 223                 /*
 224                  * Setup device structure and register the driver.
 225                  */
 226                 dev->init = pcnet_init;
 227                 dev->halt = pcnet_halt;
 228                 dev->send = pcnet_send;
 229                 dev->recv = pcnet_recv;
 230
 231                 eth_register(dev);
 232         }
 233
 234         udelay(10 * 1000);
 235
 236         return dev_nr;
 237 }
 238
 239 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
 240 {
 241         int chip_version;
 242         char *chipname;
 243
 244 #ifdef PCNET_HAS_PROM
 245         int i;
 246 #endif
 247
 248         /* Reset the PCnet controller */
 249         pcnet_reset(dev);
 250
 251         /* Check if register access is working */
 252         if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
 253                 printf("%s: CSR register access check failed\n", dev->name);
 254                 return -1;
 255         }
 256
 257         /* Identify the chip */
 258         chip_version =
 259                 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
 260         if ((chip_version & 0xfff) != 0x003)
 261                 return -1;
 262         chip_version = (chip_version >> 12) & 0xffff;
 263         switch (chip_version) {
 264         case 0x2621:
 265                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
 266                 break;
 267         case 0x2625:
 268                 chipname = "PCnet/FAST III 79C973";     /* PCI */
 269                 break;
 270         case 0x2627:
 271                 chipname = "PCnet/FAST III 79C975";     /* PCI */
 272                 break;
 273         default:
 274                 printf("%s: PCnet version %#x not supported\n",
 275                        dev->name, chip_version);
 276                 return -1;
 277         }
 278
 279         PCNET_DEBUG1("AMD %s\n", chipname);
 280
 281 #ifdef PCNET_HAS_PROM
 282         /*
 283          * In most chips, after a chip reset, the ethernet address is read from
 284          * the station address PROM at the base address and programmed into the
 285          * "Physical Address Registers" CSR12-14.
 286          */
 287         for (i = 0; i < 3; i++) {
 288                 unsigned int val;
 289
 290                 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
 291                 /* There may be endianness issues here. */
 292                 dev->enetaddr[2 * i] = val & 0x0ff;
 293                 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
 294         }
 295 #endif /* PCNET_HAS_PROM */
 296
 297         return 0;
 298 }
 299
 300 static int pcnet_init(struct eth_device *dev, bd_t *bis)
 301 {
 302         struct pcnet_uncached_priv *uc;
 303         int i, val;
 304         unsigned long addr;
 305
 306         PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 307
 308         /* Switch pcnet to 32bit mode */
 309         pcnet_write_bcr(dev, 20, 2);
 310
 311         /* Set/reset autoselect bit */
 312         val = pcnet_read_bcr(dev, 2) & ~2;
 313         val |= 2;
 314         pcnet_write_bcr(dev, 2, val);
 315
 316         /* Enable auto negotiate, setup, disable fd */
 317         val = pcnet_read_bcr(dev, 32) & ~0x98;
 318         val |= 0x20;
 319         pcnet_write_bcr(dev, 32, val);
 320
 321         /*
 322          * Enable NOUFLO on supported controllers, with the transmit
 323          * start point set to the full packet. This will cause entire
 324          * packets to be buffered by the ethernet controller before
 325          * transmission, eliminating underflows which are common on
 326          * slower devices. Controllers which do not support NOUFLO will
 327          * simply be left with a larger transmit FIFO threshold.
 328          */
 329         val = pcnet_read_bcr(dev, 18);
 330         val |= 1 << 11;
 331         pcnet_write_bcr(dev, 18, val);
 332         val = pcnet_read_csr(dev, 80);
 333         val |= 0x3 << 10;
 334         pcnet_write_csr(dev, 80, val);
 335
 336         /*
 337          * We only maintain one structure because the drivers will never
 338          * be used concurrently. In 32bit mode the RX and TX ring entries
 339          * must be aligned on 16-byte boundaries.
 340          */
 341         if (lp == NULL) {
 342                 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
 343                 addr = (addr + 0xf) & ~0xf;
 344                 lp = (pcnet_priv_t *)addr;
 345
 346                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 347                                                sizeof(*lp->uc));
 348                 flush_dcache_range(addr, addr + sizeof(*lp->uc));
 349                 addr = (unsigned long)map_physmem(addr,
 350                                 roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
 351                                 MAP_NOCACHE);
 352                 lp->uc = (struct pcnet_uncached_priv *)addr;
 353
 354                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 355                                                sizeof(*lp->rx_buf));
 356                 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
 357                 lp->rx_buf = (void *)addr;
 358         }
 359
 360         uc = lp->uc;
 361
 362         uc->init_block.mode = cpu_to_le16(0x0000);
 363         uc->init_block.filter[0] = 0x00000000;
 364         uc->init_block.filter[1] = 0x00000000;
 365
 366         /*
 367          * Initialize the Rx ring.
 368          */
 369         lp->cur_rx = 0;
 370         for (i = 0; i < RX_RING_SIZE; i++) {
 371                 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
 372                 uc->rx_ring[i].base = cpu_to_le32(addr);
 373                 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 374                 uc->rx_ring[i].status = cpu_to_le16(0x8000);
 375                 PCNET_DEBUG1
 376                         ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
 377                          uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
 378                          uc->rx_ring[i].status);
 379         }
 380
 381         /*
 382          * Initialize the Tx ring. The Tx buffer address is filled in as
 383          * needed, but we do need to clear the upper ownership bit.
 384          */
 385         lp->cur_tx = 0;
 386         for (i = 0; i < TX_RING_SIZE; i++) {
 387                 uc->tx_ring[i].base = 0;
 388                 uc->tx_ring[i].status = 0;
 389         }
 390
 391         /*
 392          * Setup Init Block.
 393          */
 394         PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
 395
 396         for (i = 0; i < 6; i++) {
 397                 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
 398                 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
 399         }
 400
 401         uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 402                                                RX_RING_LEN_BITS);
 403         addr = pcnet_virt_to_mem(dev, uc->rx_ring);
 404         uc->init_block.rx_ring = cpu_to_le32(addr);
 405         addr = pcnet_virt_to_mem(dev, uc->tx_ring);
 406         uc->init_block.tx_ring = cpu_to_le32(addr);
 407
 408         PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
 409                      uc->init_block.tlen_rlen,
 410                      uc->init_block.rx_ring, uc->init_block.tx_ring);
 411
 412         /*
 413          * Tell the controller where the Init Block is located.
 414          */
 415         barrier();
 416         addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
 417         pcnet_write_csr(dev, 1, addr & 0xffff);
 418         pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 419
 420         pcnet_write_csr(dev, 4, 0x0915);
 421         pcnet_write_csr(dev, 0, 0x0001);        /* start */
 422
 423         /* Wait for Init Done bit */
 424         for (i = 10000; i > 0; i--) {
 425                 if (pcnet_read_csr(dev, 0) & 0x0100)
 426                         break;
 427                 udelay(10);
 428         }
 429         if (i <= 0) {
 430                 printf("%s: TIMEOUT: controller init failed\n", dev->name);
 431                 pcnet_reset(dev);
 432                 return -1;
 433         }
 434
 435         /*
 436          * Finally start network controller operation.
 437          */
 438         pcnet_write_csr(dev, 0, 0x0002);
 439
 440         return 0;
 441 }
 442
 443 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 444 {
 445         int i, status;
 446         u32 addr;
 447         struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
 448
 449         PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
 450                      packet);
 451
 452         flush_dcache_range((unsigned long)packet,
 453                            (unsigned long)packet + pkt_len);
 454
 455         /* Wait for completion by testing the OWN bit */
 456         for (i = 1000; i > 0; i--) {
 457                 status = readw(&entry->status);
 458                 if ((status & 0x8000) == 0)
 459                         break;
 460                 udelay(100);
 461                 PCNET_DEBUG2(".");
 462         }
 463         if (i <= 0) {
 464                 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
 465                        dev->name, lp->cur_tx, status);
 466                 pkt_len = 0;
 467                 goto failure;
 468         }
 469
 470         /*
 471          * Setup Tx ring. Caution: the write order is important here,
 472          * set the status with the "ownership" bits last.
 473          */
 474         addr = pcnet_virt_to_mem(dev, packet);
 475         writew(-pkt_len, &entry->length);
 476         writel(0, &entry->misc);
 477         writel(addr, &entry->base);
 478         writew(0x8300, &entry->status);
 479
 480         /* Trigger an immediate send poll. */
 481         pcnet_write_csr(dev, 0, 0x0008);
 482
 483       failure:
 484         if (++lp->cur_tx >= TX_RING_SIZE)
 485                 lp->cur_tx = 0;
 486
 487         PCNET_DEBUG2("done\n");
 488         return pkt_len;
 489 }
 490
 491 static int pcnet_recv (struct eth_device *dev)
 492 {
 493         struct pcnet_rx_head *entry;
 494         unsigned char *buf;
 495         int pkt_len = 0;
 496         u16 status, err_status;
 497
 498         while (1) {
 499                 entry = &lp->uc->rx_ring[lp->cur_rx];
 500                 /*
 501                  * If we own the next entry, it's a new packet. Send it up.
 502                  */
 503                 status = readw(&entry->status);
 504                 if ((status & 0x8000) != 0)
 505                         break;
 506                 err_status = status >> 8;
 507
 508                 if (err_status != 0x03) {       /* There was an error. */
 509                         printf("%s: Rx%d", dev->name, lp->cur_rx);
 510                         PCNET_DEBUG1(" (status=0x%x)", err_status);
 511                         if (err_status & 0x20)
 512                                 printf(" Frame");
 513                         if (err_status & 0x10)
 514                                 printf(" Overflow");
 515                         if (err_status & 0x08)
 516                                 printf(" CRC");
 517                         if (err_status & 0x04)
 518                                 printf(" Fifo");
 519                         printf(" Error\n");
 520                         status &= 0x03ff;
 521
 522                 } else {
 523                         pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
 524                         if (pkt_len < 60) {
 525                                 printf("%s: Rx%d: invalid packet length %d\n",
 526                                        dev->name, lp->cur_rx, pkt_len);
 527                         } else {
 528                                 buf = (*lp->rx_buf)[lp->cur_rx];
 529                                 invalidate_dcache_range((unsigned long)buf,
 530                                         (unsigned long)buf + pkt_len);
 531                                 net_process_received_packet(buf, pkt_len);
 532                                 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
 533                                              lp->cur_rx, pkt_len, buf);
 534                         }
 535                 }
 536
 537                 status |= 0x8000;
 538                 writew(status, &entry->status);
 539
 540                 if (++lp->cur_rx >= RX_RING_SIZE)
 541                         lp->cur_rx = 0;
 542         }
 543         return pkt_len;
 544 }
 545
 546 static void pcnet_halt(struct eth_device *dev)
 547 {
 548         int i;
 549
 550         PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
 551
 552         /* Reset the PCnet controller */
 553         pcnet_reset(dev);
 554
 555         /* Wait for Stop bit */
 556         for (i = 1000; i > 0; i--) {
 557                 if (pcnet_read_csr(dev, 0) & 0x4)
 558                         break;
 559                 udelay(10);
 560         }
 561         if (i <= 0)
 562                 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
 563 }