drivers/net/pcnet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
   4  *
   5  * This driver for AMD PCnet network controllers is derived from the
   6  * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <malloc.h>
  12 #include <net.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15 #include <pci.h>
  16
  17 #define PCNET_DEBUG_LEVEL       0       /* 0=off, 1=init, 2=rx/tx */
  18
  19 #define PCNET_DEBUG1(fmt,args...)       \
  20         debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
  21 #define PCNET_DEBUG2(fmt,args...)       \
  22         debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
  23
  24 /*
  25  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  26  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  27  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  28  */
  29 #define PCNET_LOG_TX_BUFFERS    0
  30 #define PCNET_LOG_RX_BUFFERS    2
  31
  32 #define TX_RING_SIZE            (1 << (PCNET_LOG_TX_BUFFERS))
  33 #define TX_RING_LEN_BITS        ((PCNET_LOG_TX_BUFFERS) << 12)
  34
  35 #define RX_RING_SIZE            (1 << (PCNET_LOG_RX_BUFFERS))
  36 #define RX_RING_LEN_BITS        ((PCNET_LOG_RX_BUFFERS) << 4)
  37
  38 #define PKT_BUF_SZ              1544
  39
  40 /* The PCNET Rx and Tx ring descriptors. */
  41 struct pcnet_rx_head {
  42         u32 base;
  43         s16 buf_length;
  44         s16 status;
  45         u32 msg_length;
  46         u32 reserved;
  47 };
  48
  49 struct pcnet_tx_head {
  50         u32 base;
  51         s16 length;
  52         s16 status;
  53         u32 misc;
  54         u32 reserved;
  55 };
  56
  57 /* The PCNET 32-Bit initialization block, described in databook. */
  58 struct pcnet_init_block {
  59         u16 mode;
  60         u16 tlen_rlen;
  61         u8 phys_addr[6];
  62         u16 reserved;
  63         u32 filter[2];
  64         /* Receive and transmit ring base, along with extra bits. */
  65         u32 rx_ring;
  66         u32 tx_ring;
  67         u32 reserved2;
  68 };
  69
  70 struct pcnet_uncached_priv {
  71         struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  72         struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  73         struct pcnet_init_block init_block;
  74 };
  75
  76 typedef struct pcnet_priv {
  77         struct pcnet_uncached_priv *uc;
  78         /* Receive Buffer space */
  79         unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
  80         int cur_rx;
  81         int cur_tx;
  82 } pcnet_priv_t;
  83
  84 static pcnet_priv_t *lp;
  85
  86 /* Offsets from base I/O address for WIO mode */
  87 #define PCNET_RDP               0x10
  88 #define PCNET_RAP               0x12
  89 #define PCNET_RESET             0x14
  90 #define PCNET_BDP               0x16
  91
  92 static u16 pcnet_read_csr(struct eth_device *dev, int index)
  93 {
  94         outw(index, dev->iobase + PCNET_RAP);
  95         return inw(dev->iobase + PCNET_RDP);
  96 }
  97
  98 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
  99 {
 100         outw(index, dev->iobase + PCNET_RAP);
 101         outw(val, dev->iobase + PCNET_RDP);
 102 }
 103
 104 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
 105 {
 106         outw(index, dev->iobase + PCNET_RAP);
 107         return inw(dev->iobase + PCNET_BDP);
 108 }
 109
 110 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
 111 {
 112         outw(index, dev->iobase + PCNET_RAP);
 113         outw(val, dev->iobase + PCNET_BDP);
 114 }
 115
 116 static void pcnet_reset(struct eth_device *dev)
 117 {
 118         inw(dev->iobase + PCNET_RESET);
 119 }
 120
 121 static int pcnet_check(struct eth_device *dev)
 122 {
 123         outw(88, dev->iobase + PCNET_RAP);
 124         return inw(dev->iobase + PCNET_RAP) == 88;
 125 }
 126
 127 static int pcnet_init (struct eth_device *dev, bd_t * bis);
 128 static int pcnet_send(struct eth_device *dev, void *packet, int length);
 129 static int pcnet_recv (struct eth_device *dev);
 130 static void pcnet_halt (struct eth_device *dev);
 131 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 132
 133 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
 134                                                 void *addr)
 135 {
 136         pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
 137         void *virt_addr = addr;
 138
 139         return pci_virt_to_mem(devbusfn, virt_addr);
 140 }
 141
 142 static struct pci_device_id supported[] = {
 143         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
 144         {}
 145 };
 146
 147
 148 int pcnet_initialize(bd_t *bis)
 149 {
 150         pci_dev_t devbusfn;
 151         struct eth_device *dev;
 152         u16 command, status;
 153         int dev_nr = 0;
 154         u32 bar;
 155
 156         PCNET_DEBUG1("\npcnet_initialize...\n");
 157
 158         for (dev_nr = 0;; dev_nr++) {
 159
 160                 /*
 161                  * Find the PCnet PCI device(s).
 162                  */
 163                 devbusfn = pci_find_devices(supported, dev_nr);
 164                 if (devbusfn < 0)
 165                         break;
 166
 167                 /*
 168                  * Allocate and pre-fill the device structure.
 169                  */
 170                 dev = (struct eth_device *)malloc(sizeof(*dev));
 171                 if (!dev) {
 172                         printf("pcnet: Can not allocate memory\n");
 173                         break;
 174                 }
 175                 memset(dev, 0, sizeof(*dev));
 176                 dev->priv = (void *)(unsigned long)devbusfn;
 177                 sprintf(dev->name, "pcnet#%d", dev_nr);
 178
 179                 /*
 180                  * Setup the PCI device.
 181                  */
 182                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
 183                 dev->iobase = pci_mem_to_phys(devbusfn, bar);
 184                 dev->iobase &= ~0xf;
 185
 186                 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
 187                              dev->name, devbusfn, (unsigned long)dev->iobase);
 188
 189                 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 190                 pci_write_config_word(devbusfn, PCI_COMMAND, command);
 191                 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 192                 if ((status & command) != command) {
 193                         printf("%s: Couldn't enable IO access or Bus Mastering\n",
 194                                dev->name);
 195                         free(dev);
 196                         continue;
 197                 }
 198
 199                 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
 200
 201                 /*
 202                  * Probe the PCnet chip.
 203                  */
 204                 if (pcnet_probe(dev, bis, dev_nr) < 0) {
 205                         free(dev);
 206                         continue;
 207                 }
 208
 209                 /*
 210                  * Setup device structure and register the driver.
 211                  */
 212                 dev->init = pcnet_init;
 213                 dev->halt = pcnet_halt;
 214                 dev->send = pcnet_send;
 215                 dev->recv = pcnet_recv;
 216
 217                 eth_register(dev);
 218         }
 219
 220         udelay(10 * 1000);
 221
 222         return dev_nr;
 223 }
 224
 225 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
 226 {
 227         int chip_version;
 228         char *chipname;
 229
 230 #ifdef PCNET_HAS_PROM
 231         int i;
 232 #endif
 233
 234         /* Reset the PCnet controller */
 235         pcnet_reset(dev);
 236
 237         /* Check if register access is working */
 238         if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
 239                 printf("%s: CSR register access check failed\n", dev->name);
 240                 return -1;
 241         }
 242
 243         /* Identify the chip */
 244         chip_version =
 245                 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
 246         if ((chip_version & 0xfff) != 0x003)
 247                 return -1;
 248         chip_version = (chip_version >> 12) & 0xffff;
 249         switch (chip_version) {
 250         case 0x2621:
 251                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
 252                 break;
 253         case 0x2625:
 254                 chipname = "PCnet/FAST III 79C973";     /* PCI */
 255                 break;
 256         case 0x2627:
 257                 chipname = "PCnet/FAST III 79C975";     /* PCI */
 258                 break;
 259         default:
 260                 printf("%s: PCnet version %#x not supported\n",
 261                        dev->name, chip_version);
 262                 return -1;
 263         }
 264
 265         PCNET_DEBUG1("AMD %s\n", chipname);
 266
 267 #ifdef PCNET_HAS_PROM
 268         /*
 269          * In most chips, after a chip reset, the ethernet address is read from
 270          * the station address PROM at the base address and programmed into the
 271          * "Physical Address Registers" CSR12-14.
 272          */
 273         for (i = 0; i < 3; i++) {
 274                 unsigned int val;
 275
 276                 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
 277                 /* There may be endianness issues here. */
 278                 dev->enetaddr[2 * i] = val & 0x0ff;
 279                 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
 280         }
 281 #endif /* PCNET_HAS_PROM */
 282
 283         return 0;
 284 }
 285
 286 static int pcnet_init(struct eth_device *dev, bd_t *bis)
 287 {
 288         struct pcnet_uncached_priv *uc;
 289         int i, val;
 290         unsigned long addr;
 291
 292         PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 293
 294         /* Switch pcnet to 32bit mode */
 295         pcnet_write_bcr(dev, 20, 2);
 296
 297         /* Set/reset autoselect bit */
 298         val = pcnet_read_bcr(dev, 2) & ~2;
 299         val |= 2;
 300         pcnet_write_bcr(dev, 2, val);
 301
 302         /* Enable auto negotiate, setup, disable fd */
 303         val = pcnet_read_bcr(dev, 32) & ~0x98;
 304         val |= 0x20;
 305         pcnet_write_bcr(dev, 32, val);
 306
 307         /*
 308          * Enable NOUFLO on supported controllers, with the transmit
 309          * start point set to the full packet. This will cause entire
 310          * packets to be buffered by the ethernet controller before
 311          * transmission, eliminating underflows which are common on
 312          * slower devices. Controllers which do not support NOUFLO will
 313          * simply be left with a larger transmit FIFO threshold.
 314          */
 315         val = pcnet_read_bcr(dev, 18);
 316         val |= 1 << 11;
 317         pcnet_write_bcr(dev, 18, val);
 318         val = pcnet_read_csr(dev, 80);
 319         val |= 0x3 << 10;
 320         pcnet_write_csr(dev, 80, val);
 321
 322         /*
 323          * We only maintain one structure because the drivers will never
 324          * be used concurrently. In 32bit mode the RX and TX ring entries
 325          * must be aligned on 16-byte boundaries.
 326          */
 327         if (lp == NULL) {
 328                 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
 329                 addr = (addr + 0xf) & ~0xf;
 330                 lp = (pcnet_priv_t *)addr;
 331
 332                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 333                                                sizeof(*lp->uc));
 334                 flush_dcache_range(addr, addr + sizeof(*lp->uc));
 335                 addr = (unsigned long)map_physmem(addr,
 336                                 roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
 337                                 MAP_NOCACHE);
 338                 lp->uc = (struct pcnet_uncached_priv *)addr;
 339
 340                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 341                                                sizeof(*lp->rx_buf));
 342                 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
 343                 lp->rx_buf = (void *)addr;
 344         }
 345
 346         uc = lp->uc;
 347
 348         uc->init_block.mode = cpu_to_le16(0x0000);
 349         uc->init_block.filter[0] = 0x00000000;
 350         uc->init_block.filter[1] = 0x00000000;
 351
 352         /*
 353          * Initialize the Rx ring.
 354          */
 355         lp->cur_rx = 0;
 356         for (i = 0; i < RX_RING_SIZE; i++) {
 357                 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
 358                 uc->rx_ring[i].base = cpu_to_le32(addr);
 359                 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 360                 uc->rx_ring[i].status = cpu_to_le16(0x8000);
 361                 PCNET_DEBUG1
 362                         ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
 363                          uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
 364                          uc->rx_ring[i].status);
 365         }
 366
 367         /*
 368          * Initialize the Tx ring. The Tx buffer address is filled in as
 369          * needed, but we do need to clear the upper ownership bit.
 370          */
 371         lp->cur_tx = 0;
 372         for (i = 0; i < TX_RING_SIZE; i++) {
 373                 uc->tx_ring[i].base = 0;
 374                 uc->tx_ring[i].status = 0;
 375         }
 376
 377         /*
 378          * Setup Init Block.
 379          */
 380         PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
 381
 382         for (i = 0; i < 6; i++) {
 383                 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
 384                 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
 385         }
 386
 387         uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 388                                                RX_RING_LEN_BITS);
 389         addr = pcnet_virt_to_mem(dev, uc->rx_ring);
 390         uc->init_block.rx_ring = cpu_to_le32(addr);
 391         addr = pcnet_virt_to_mem(dev, uc->tx_ring);
 392         uc->init_block.tx_ring = cpu_to_le32(addr);
 393
 394         PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
 395                      uc->init_block.tlen_rlen,
 396                      uc->init_block.rx_ring, uc->init_block.tx_ring);
 397
 398         /*
 399          * Tell the controller where the Init Block is located.
 400          */
 401         barrier();
 402         addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
 403         pcnet_write_csr(dev, 1, addr & 0xffff);
 404         pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 405
 406         pcnet_write_csr(dev, 4, 0x0915);
 407         pcnet_write_csr(dev, 0, 0x0001);        /* start */
 408
 409         /* Wait for Init Done bit */
 410         for (i = 10000; i > 0; i--) {
 411                 if (pcnet_read_csr(dev, 0) & 0x0100)
 412                         break;
 413                 udelay(10);
 414         }
 415         if (i <= 0) {
 416                 printf("%s: TIMEOUT: controller init failed\n", dev->name);
 417                 pcnet_reset(dev);
 418                 return -1;
 419         }
 420
 421         /*
 422          * Finally start network controller operation.
 423          */
 424         pcnet_write_csr(dev, 0, 0x0002);
 425
 426         return 0;
 427 }
 428
 429 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 430 {
 431         int i, status;
 432         u32 addr;
 433         struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
 434
 435         PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
 436                      packet);
 437
 438         flush_dcache_range((unsigned long)packet,
 439                            (unsigned long)packet + pkt_len);
 440
 441         /* Wait for completion by testing the OWN bit */
 442         for (i = 1000; i > 0; i--) {
 443                 status = readw(&entry->status);
 444                 if ((status & 0x8000) == 0)
 445                         break;
 446                 udelay(100);
 447                 PCNET_DEBUG2(".");
 448         }
 449         if (i <= 0) {
 450                 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
 451                        dev->name, lp->cur_tx, status);
 452                 pkt_len = 0;
 453                 goto failure;
 454         }
 455
 456         /*
 457          * Setup Tx ring. Caution: the write order is important here,
 458          * set the status with the "ownership" bits last.
 459          */
 460         addr = pcnet_virt_to_mem(dev, packet);
 461         writew(-pkt_len, &entry->length);
 462         writel(0, &entry->misc);
 463         writel(addr, &entry->base);
 464         writew(0x8300, &entry->status);
 465
 466         /* Trigger an immediate send poll. */
 467         pcnet_write_csr(dev, 0, 0x0008);
 468
 469       failure:
 470         if (++lp->cur_tx >= TX_RING_SIZE)
 471                 lp->cur_tx = 0;
 472
 473         PCNET_DEBUG2("done\n");
 474         return pkt_len;
 475 }
 476
 477 static int pcnet_recv (struct eth_device *dev)
 478 {
 479         struct pcnet_rx_head *entry;
 480         unsigned char *buf;
 481         int pkt_len = 0;
 482         u16 status, err_status;
 483
 484         while (1) {
 485                 entry = &lp->uc->rx_ring[lp->cur_rx];
 486                 /*
 487                  * If we own the next entry, it's a new packet. Send it up.
 488                  */
 489                 status = readw(&entry->status);
 490                 if ((status & 0x8000) != 0)
 491                         break;
 492                 err_status = status >> 8;
 493
 494                 if (err_status != 0x03) {       /* There was an error. */
 495                         printf("%s: Rx%d", dev->name, lp->cur_rx);
 496                         PCNET_DEBUG1(" (status=0x%x)", err_status);
 497                         if (err_status & 0x20)
 498                                 printf(" Frame");
 499                         if (err_status & 0x10)
 500                                 printf(" Overflow");
 501                         if (err_status & 0x08)
 502                                 printf(" CRC");
 503                         if (err_status & 0x04)
 504                                 printf(" Fifo");
 505                         printf(" Error\n");
 506                         status &= 0x03ff;
 507
 508                 } else {
 509                         pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
 510                         if (pkt_len < 60) {
 511                                 printf("%s: Rx%d: invalid packet length %d\n",
 512                                        dev->name, lp->cur_rx, pkt_len);
 513                         } else {
 514                                 buf = (*lp->rx_buf)[lp->cur_rx];
 515                                 invalidate_dcache_range((unsigned long)buf,
 516                                         (unsigned long)buf + pkt_len);
 517                                 net_process_received_packet(buf, pkt_len);
 518                                 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
 519                                              lp->cur_rx, pkt_len, buf);
 520                         }
 521                 }
 522
 523                 status |= 0x8000;
 524                 writew(status, &entry->status);
 525
 526                 if (++lp->cur_rx >= RX_RING_SIZE)
 527                         lp->cur_rx = 0;
 528         }
 529         return pkt_len;
 530 }
 531
 532 static void pcnet_halt(struct eth_device *dev)
 533 {
 534         int i;
 535
 536         PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
 537
 538         /* Reset the PCnet controller */
 539         pcnet_reset(dev);
 540
 541         /* Wait for Stop bit */
 542         for (i = 1000; i > 0; i--) {
 543                 if (pcnet_read_csr(dev, 0) & 0x4)
 544                         break;
 545                 udelay(10);
 546         }
 547         if (i <= 0)
 548                 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
 549 }