1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
15 #include <asm/cache.h>
18 #include <linux/delay.h>
20 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
22 #define PCNET_DEBUG1(fmt,args...) \
23 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
24 #define PCNET_DEBUG2(fmt,args...) \
25 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
28 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
29 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
30 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
32 #define PCNET_LOG_TX_BUFFERS 0
33 #define PCNET_LOG_RX_BUFFERS 2
35 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
36 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
38 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
39 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
41 #define PKT_BUF_SZ 1544
43 /* The PCNET Rx and Tx ring descriptors. */
44 struct pcnet_rx_head {
52 struct pcnet_tx_head {
60 /* The PCNET 32-Bit initialization block, described in databook. */
61 struct pcnet_init_block {
67 /* Receive and transmit ring base, along with extra bits. */
73 struct pcnet_uncached_priv {
74 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
75 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
76 struct pcnet_init_block init_block;
79 typedef struct pcnet_priv {
80 struct pcnet_uncached_priv *uc;
81 /* Receive Buffer space */
82 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
87 static pcnet_priv_t *lp;
89 /* Offsets from base I/O address for WIO mode */
90 #define PCNET_RDP 0x10
91 #define PCNET_RAP 0x12
92 #define PCNET_RESET 0x14
93 #define PCNET_BDP 0x16
95 static u16 pcnet_read_csr(struct eth_device *dev, int index)
97 void __iomem *base = (void __iomem *)dev->iobase;
99 writew(index, base + PCNET_RAP);
100 return readw(base + PCNET_RDP);
103 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
105 void __iomem *base = (void __iomem *)dev->iobase;
107 writew(index, base + PCNET_RAP);
108 writew(val, base + PCNET_RDP);
111 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
113 void __iomem *base = (void __iomem *)dev->iobase;
115 writew(index, base + PCNET_RAP);
116 return readw(base + PCNET_BDP);
119 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
121 void __iomem *base = (void __iomem *)dev->iobase;
123 writew(index, base + PCNET_RAP);
124 writew(val, base + PCNET_BDP);
127 static void pcnet_reset(struct eth_device *dev)
129 void __iomem *base = (void __iomem *)dev->iobase;
131 readw(base + PCNET_RESET);
134 static int pcnet_check(struct eth_device *dev)
136 void __iomem *base = (void __iomem *)dev->iobase;
138 writew(88, base + PCNET_RAP);
139 return readw(base + PCNET_RAP) == 88;
142 static int pcnet_init (struct eth_device *dev, bd_t * bis);
143 static int pcnet_send(struct eth_device *dev, void *packet, int length);
144 static int pcnet_recv (struct eth_device *dev);
145 static void pcnet_halt (struct eth_device *dev);
146 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
148 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
151 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
152 void *virt_addr = addr;
154 return pci_virt_to_mem(devbusfn, virt_addr);
157 static struct pci_device_id supported[] = {
158 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
163 int pcnet_initialize(bd_t *bis)
166 struct eth_device *dev;
171 PCNET_DEBUG1("\npcnet_initialize...\n");
173 for (dev_nr = 0;; dev_nr++) {
176 * Find the PCnet PCI device(s).
178 devbusfn = pci_find_devices(supported, dev_nr);
183 * Allocate and pre-fill the device structure.
185 dev = (struct eth_device *)malloc(sizeof(*dev));
187 printf("pcnet: Can not allocate memory\n");
190 memset(dev, 0, sizeof(*dev));
191 dev->priv = (void *)(unsigned long)devbusfn;
192 sprintf(dev->name, "pcnet#%d", dev_nr);
195 * Setup the PCI device.
197 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
198 dev->iobase = pci_mem_to_phys(devbusfn, bar);
201 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
202 dev->name, devbusfn, (unsigned long)dev->iobase);
204 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
205 pci_write_config_word(devbusfn, PCI_COMMAND, command);
206 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
207 if ((status & command) != command) {
208 printf("%s: Couldn't enable IO access or Bus Mastering\n",
214 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
217 * Probe the PCnet chip.
219 if (pcnet_probe(dev, bis, dev_nr) < 0) {
225 * Setup device structure and register the driver.
227 dev->init = pcnet_init;
228 dev->halt = pcnet_halt;
229 dev->send = pcnet_send;
230 dev->recv = pcnet_recv;
240 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
245 #ifdef PCNET_HAS_PROM
249 /* Reset the PCnet controller */
252 /* Check if register access is working */
253 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
254 printf("%s: CSR register access check failed\n", dev->name);
258 /* Identify the chip */
260 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
261 if ((chip_version & 0xfff) != 0x003)
263 chip_version = (chip_version >> 12) & 0xffff;
264 switch (chip_version) {
266 chipname = "PCnet/PCI II 79C970A"; /* PCI */
269 chipname = "PCnet/FAST III 79C973"; /* PCI */
272 chipname = "PCnet/FAST III 79C975"; /* PCI */
275 printf("%s: PCnet version %#x not supported\n",
276 dev->name, chip_version);
280 PCNET_DEBUG1("AMD %s\n", chipname);
282 #ifdef PCNET_HAS_PROM
284 * In most chips, after a chip reset, the ethernet address is read from
285 * the station address PROM at the base address and programmed into the
286 * "Physical Address Registers" CSR12-14.
288 for (i = 0; i < 3; i++) {
291 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
292 /* There may be endianness issues here. */
293 dev->enetaddr[2 * i] = val & 0x0ff;
294 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
296 #endif /* PCNET_HAS_PROM */
301 static int pcnet_init(struct eth_device *dev, bd_t *bis)
303 struct pcnet_uncached_priv *uc;
307 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
309 /* Switch pcnet to 32bit mode */
310 pcnet_write_bcr(dev, 20, 2);
312 /* Set/reset autoselect bit */
313 val = pcnet_read_bcr(dev, 2) & ~2;
315 pcnet_write_bcr(dev, 2, val);
317 /* Enable auto negotiate, setup, disable fd */
318 val = pcnet_read_bcr(dev, 32) & ~0x98;
320 pcnet_write_bcr(dev, 32, val);
323 * Enable NOUFLO on supported controllers, with the transmit
324 * start point set to the full packet. This will cause entire
325 * packets to be buffered by the ethernet controller before
326 * transmission, eliminating underflows which are common on
327 * slower devices. Controllers which do not support NOUFLO will
328 * simply be left with a larger transmit FIFO threshold.
330 val = pcnet_read_bcr(dev, 18);
332 pcnet_write_bcr(dev, 18, val);
333 val = pcnet_read_csr(dev, 80);
335 pcnet_write_csr(dev, 80, val);
338 * We only maintain one structure because the drivers will never
339 * be used concurrently. In 32bit mode the RX and TX ring entries
340 * must be aligned on 16-byte boundaries.
343 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
344 addr = (addr + 0xf) & ~0xf;
345 lp = (pcnet_priv_t *)addr;
347 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
349 flush_dcache_range(addr, addr + sizeof(*lp->uc));
350 addr = (unsigned long)map_physmem(addr,
351 roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
353 lp->uc = (struct pcnet_uncached_priv *)addr;
355 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
356 sizeof(*lp->rx_buf));
357 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
358 lp->rx_buf = (void *)addr;
363 uc->init_block.mode = cpu_to_le16(0x0000);
364 uc->init_block.filter[0] = 0x00000000;
365 uc->init_block.filter[1] = 0x00000000;
368 * Initialize the Rx ring.
371 for (i = 0; i < RX_RING_SIZE; i++) {
372 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
373 uc->rx_ring[i].base = cpu_to_le32(addr);
374 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
375 uc->rx_ring[i].status = cpu_to_le16(0x8000);
377 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
378 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
379 uc->rx_ring[i].status);
383 * Initialize the Tx ring. The Tx buffer address is filled in as
384 * needed, but we do need to clear the upper ownership bit.
387 for (i = 0; i < TX_RING_SIZE; i++) {
388 uc->tx_ring[i].base = 0;
389 uc->tx_ring[i].status = 0;
395 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
397 for (i = 0; i < 6; i++) {
398 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
399 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
402 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
404 addr = pcnet_virt_to_mem(dev, uc->rx_ring);
405 uc->init_block.rx_ring = cpu_to_le32(addr);
406 addr = pcnet_virt_to_mem(dev, uc->tx_ring);
407 uc->init_block.tx_ring = cpu_to_le32(addr);
409 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
410 uc->init_block.tlen_rlen,
411 uc->init_block.rx_ring, uc->init_block.tx_ring);
414 * Tell the controller where the Init Block is located.
417 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
418 pcnet_write_csr(dev, 1, addr & 0xffff);
419 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
421 pcnet_write_csr(dev, 4, 0x0915);
422 pcnet_write_csr(dev, 0, 0x0001); /* start */
424 /* Wait for Init Done bit */
425 for (i = 10000; i > 0; i--) {
426 if (pcnet_read_csr(dev, 0) & 0x0100)
431 printf("%s: TIMEOUT: controller init failed\n", dev->name);
437 * Finally start network controller operation.
439 pcnet_write_csr(dev, 0, 0x0002);
444 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
448 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
450 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
453 flush_dcache_range((unsigned long)packet,
454 (unsigned long)packet + pkt_len);
456 /* Wait for completion by testing the OWN bit */
457 for (i = 1000; i > 0; i--) {
458 status = readw(&entry->status);
459 if ((status & 0x8000) == 0)
465 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
466 dev->name, lp->cur_tx, status);
472 * Setup Tx ring. Caution: the write order is important here,
473 * set the status with the "ownership" bits last.
475 addr = pcnet_virt_to_mem(dev, packet);
476 writew(-pkt_len, &entry->length);
477 writel(0, &entry->misc);
478 writel(addr, &entry->base);
479 writew(0x8300, &entry->status);
481 /* Trigger an immediate send poll. */
482 pcnet_write_csr(dev, 0, 0x0008);
485 if (++lp->cur_tx >= TX_RING_SIZE)
488 PCNET_DEBUG2("done\n");
492 static int pcnet_recv (struct eth_device *dev)
494 struct pcnet_rx_head *entry;
497 u16 status, err_status;
500 entry = &lp->uc->rx_ring[lp->cur_rx];
502 * If we own the next entry, it's a new packet. Send it up.
504 status = readw(&entry->status);
505 if ((status & 0x8000) != 0)
507 err_status = status >> 8;
509 if (err_status != 0x03) { /* There was an error. */
510 printf("%s: Rx%d", dev->name, lp->cur_rx);
511 PCNET_DEBUG1(" (status=0x%x)", err_status);
512 if (err_status & 0x20)
514 if (err_status & 0x10)
516 if (err_status & 0x08)
518 if (err_status & 0x04)
524 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
526 printf("%s: Rx%d: invalid packet length %d\n",
527 dev->name, lp->cur_rx, pkt_len);
529 buf = (*lp->rx_buf)[lp->cur_rx];
530 invalidate_dcache_range((unsigned long)buf,
531 (unsigned long)buf + pkt_len);
532 net_process_received_packet(buf, pkt_len);
533 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
534 lp->cur_rx, pkt_len, buf);
539 writew(status, &entry->status);
541 if (++lp->cur_rx >= RX_RING_SIZE)
547 static void pcnet_halt(struct eth_device *dev)
551 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
553 /* Reset the PCnet controller */
556 /* Wait for Stop bit */
557 for (i = 1000; i > 0; i--) {
558 if (pcnet_read_csr(dev, 0) & 0x4)
563 printf("%s: TIMEOUT: controller reset failed\n", dev->name);