drivers/net/pch_gbe.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   4  *
   5  * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <asm/io.h>
  15 #include <pci.h>
  16 #include <miiphy.h>
  17 #include "pch_gbe.h"
  18
  19 #if !defined(CONFIG_PHYLIB)
  20 # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
  21 #endif
  22
  23 static struct pci_device_id supported[] = {
  24         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
  25         { }
  26 };
  27
  28 static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
  29 {
  30         u32 macid_hi, macid_lo;
  31
  32         macid_hi = readl(&mac_regs->mac_adr[0].high);
  33         macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
  34         debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
  35
  36         addr[0] = (u8)(macid_hi & 0xff);
  37         addr[1] = (u8)((macid_hi >> 8) & 0xff);
  38         addr[2] = (u8)((macid_hi >> 16) & 0xff);
  39         addr[3] = (u8)((macid_hi >> 24) & 0xff);
  40         addr[4] = (u8)(macid_lo & 0xff);
  41         addr[5] = (u8)((macid_lo >> 8) & 0xff);
  42 }
  43
  44 static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
  45 {
  46         u32 macid_hi, macid_lo;
  47         ulong start;
  48
  49         macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
  50         macid_lo = addr[4] + (addr[5] << 8);
  51
  52         writel(macid_hi, &mac_regs->mac_adr[0].high);
  53         writel(macid_lo, &mac_regs->mac_adr[0].low);
  54         writel(0xfffe, &mac_regs->addr_mask);
  55
  56         start = get_timer(0);
  57         while (get_timer(start) < PCH_GBE_TIMEOUT) {
  58                 if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
  59                         return 0;
  60
  61                 udelay(10);
  62         }
  63
  64         return -ETIME;
  65 }
  66
  67 static int pch_gbe_reset(struct udevice *dev)
  68 {
  69         struct pch_gbe_priv *priv = dev_get_priv(dev);
  70         struct eth_pdata *plat = dev_get_platdata(dev);
  71         struct pch_gbe_regs *mac_regs = priv->mac_regs;
  72         ulong start;
  73
  74         priv->rx_idx = 0;
  75         priv->tx_idx = 0;
  76
  77         writel(PCH_GBE_ALL_RST, &mac_regs->reset);
  78
  79         /*
  80          * Configure the MAC to RGMII mode after reset
  81          *
  82          * For some unknown reason, we must do the configuration here right
  83          * after resetting the whole MAC, otherwise the reset bit in the RESET
  84          * register will never be cleared by the hardware. And there is another
  85          * way of having the same magic, that is to configure the MODE register
  86          * to have the MAC work in MII/GMII mode, which is how current Linux
  87          * pch_gbe driver does. Since anyway we need program the MAC to RGMII
  88          * mode in the driver, we just do it here.
  89          *
  90          * Note: this behavior is not documented in the hardware manual.
  91          */
  92         writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
  93                &mac_regs->rgmii_ctrl);
  94
  95         start = get_timer(0);
  96         while (get_timer(start) < PCH_GBE_TIMEOUT) {
  97                 if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
  98                         /*
  99                          * Soft reset clears hardware MAC address registers,
 100                          * so we have to reload MAC address here in order to
 101                          * make linux pch_gbe driver happy.
 102                          */
 103                         return pch_gbe_mac_write(mac_regs, plat->enetaddr);
 104                 }
 105
 106                 udelay(10);
 107         }
 108
 109         debug("pch_gbe: reset timeout\n");
 110         return -ETIME;
 111 }
 112
 113 static void pch_gbe_rx_descs_init(struct udevice *dev)
 114 {
 115         struct pch_gbe_priv *priv = dev_get_priv(dev);
 116         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 117         struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
 118         int i;
 119
 120         memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
 121         for (i = 0; i < PCH_GBE_DESC_NUM; i++)
 122                 rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
 123                         priv->rx_buff[i]);
 124
 125         flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
 126
 127         writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
 128                &mac_regs->rx_dsc_base);
 129         writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
 130                &mac_regs->rx_dsc_size);
 131
 132         writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
 133                &mac_regs->rx_dsc_sw_p);
 134 }
 135
 136 static void pch_gbe_tx_descs_init(struct udevice *dev)
 137 {
 138         struct pch_gbe_priv *priv = dev_get_priv(dev);
 139         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 140         struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
 141
 142         memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
 143
 144         flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
 145
 146         writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
 147                &mac_regs->tx_dsc_base);
 148         writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
 149                &mac_regs->tx_dsc_size);
 150         writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
 151                &mac_regs->tx_dsc_sw_p);
 152 }
 153
 154 static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
 155                                 struct phy_device *phydev)
 156 {
 157         if (!phydev->link) {
 158                 printf("%s: No link.\n", phydev->dev->name);
 159                 return;
 160         }
 161
 162         clrbits_le32(&mac_regs->rgmii_ctrl,
 163                      PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
 164         clrbits_le32(&mac_regs->mode,
 165                      PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
 166
 167         switch (phydev->speed) {
 168         case 1000:
 169                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
 170                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
 171                 break;
 172         case 100:
 173                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
 174                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
 175                 break;
 176         case 10:
 177                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
 178                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
 179                 break;
 180         }
 181
 182         if (phydev->duplex) {
 183                 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
 184                 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
 185         }
 186
 187         printf("Speed: %d, %s duplex\n", phydev->speed,
 188                (phydev->duplex) ? "full" : "half");
 189
 190         return;
 191 }
 192
 193 static int pch_gbe_start(struct udevice *dev)
 194 {
 195         struct pch_gbe_priv *priv = dev_get_priv(dev);
 196         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 197
 198         if (pch_gbe_reset(dev))
 199                 return -1;
 200
 201         pch_gbe_rx_descs_init(dev);
 202         pch_gbe_tx_descs_init(dev);
 203
 204         /* Enable frame bursting */
 205         writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
 206         /* Disable TCP/IP accelerator */
 207         writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
 208         /* Disable RX flow control */
 209         writel(0, &mac_regs->rx_fctrl);
 210         /* Configure RX/TX mode */
 211         writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
 212                PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
 213         writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
 214                PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
 215                PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
 216
 217         /* Start up the PHY */
 218         if (phy_startup(priv->phydev)) {
 219                 printf("Could not initialize PHY %s\n",
 220                        priv->phydev->dev->name);
 221                 return -1;
 222         }
 223
 224         pch_gbe_adjust_link(mac_regs, priv->phydev);
 225
 226         if (!priv->phydev->link)
 227                 return -1;
 228
 229         /* Enable TX & RX */
 230         writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
 231         writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
 232
 233         return 0;
 234 }
 235
 236 static void pch_gbe_stop(struct udevice *dev)
 237 {
 238         struct pch_gbe_priv *priv = dev_get_priv(dev);
 239
 240         pch_gbe_reset(dev);
 241
 242         phy_shutdown(priv->phydev);
 243 }
 244
 245 static int pch_gbe_send(struct udevice *dev, void *packet, int length)
 246 {
 247         struct pch_gbe_priv *priv = dev_get_priv(dev);
 248         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 249         struct pch_gbe_tx_desc *tx_head, *tx_desc;
 250         u16 frame_ctrl = 0;
 251         u32 int_st;
 252         ulong start;
 253
 254         flush_dcache_range((ulong)packet, (ulong)packet + length);
 255
 256         tx_head = &priv->tx_desc[0];
 257         tx_desc = &priv->tx_desc[priv->tx_idx];
 258
 259         if (length < 64)
 260                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
 261
 262         tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
 263         tx_desc->length = length;
 264         tx_desc->tx_words_eob = length + 3;
 265         tx_desc->tx_frame_ctrl = frame_ctrl;
 266         tx_desc->dma_status = 0;
 267         tx_desc->gbec_status = 0;
 268
 269         flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
 270
 271         /* Test the wrap-around condition */
 272         if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
 273                 priv->tx_idx = 0;
 274
 275         writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
 276                &mac_regs->tx_dsc_sw_p);
 277
 278         start = get_timer(0);
 279         while (get_timer(start) < PCH_GBE_TIMEOUT) {
 280                 int_st = readl(&mac_regs->int_st);
 281                 if (int_st & PCH_GBE_INT_TX_CMPLT)
 282                         return 0;
 283
 284                 udelay(10);
 285         }
 286
 287         debug("pch_gbe: sent failed\n");
 288         return -ETIME;
 289 }
 290
 291 static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
 292 {
 293         struct pch_gbe_priv *priv = dev_get_priv(dev);
 294         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 295         struct pch_gbe_rx_desc *rx_desc;
 296         ulong hw_desc, length;
 297         void *buffer;
 298
 299         rx_desc = &priv->rx_desc[priv->rx_idx];
 300
 301         readl(&mac_regs->int_st);
 302         hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
 303
 304         /* Just return if not receiving any packet */
 305         if (virt_to_phys(rx_desc) == hw_desc)
 306                 return -EAGAIN;
 307
 308         /* Invalidate the descriptor */
 309         invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
 310
 311         length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
 312         buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
 313         invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
 314         *packetp = (uchar *)buffer;
 315
 316         return length;
 317 }
 318
 319 static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
 320 {
 321         struct pch_gbe_priv *priv = dev_get_priv(dev);
 322         struct pch_gbe_regs *mac_regs = priv->mac_regs;
 323         struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
 324         int rx_swp;
 325
 326         /* Test the wrap-around condition */
 327         if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
 328                 priv->rx_idx = 0;
 329         rx_swp = priv->rx_idx;
 330         if (++rx_swp >= PCH_GBE_DESC_NUM)
 331                 rx_swp = 0;
 332
 333         writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
 334                &mac_regs->rx_dsc_sw_p);
 335
 336         return 0;
 337 }
 338
 339 static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
 340 {
 341         ulong start = get_timer(0);
 342
 343         while (get_timer(start) < PCH_GBE_TIMEOUT) {
 344                 if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
 345                         return 0;
 346
 347                 udelay(10);
 348         }
 349
 350         return -ETIME;
 351 }
 352
 353 static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 354 {
 355         struct pch_gbe_regs *mac_regs = bus->priv;
 356         u32 miim;
 357
 358         if (pch_gbe_mdio_ready(mac_regs))
 359                 return -ETIME;
 360
 361         miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 362                (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 363                PCH_GBE_MIIM_OPER_READ;
 364         writel(miim, &mac_regs->miim);
 365
 366         if (pch_gbe_mdio_ready(mac_regs))
 367                 return -ETIME;
 368
 369         return readl(&mac_regs->miim) & 0xffff;
 370 }
 371
 372 static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
 373                               int reg, u16 val)
 374 {
 375         struct pch_gbe_regs *mac_regs = bus->priv;
 376         u32 miim;
 377
 378         if (pch_gbe_mdio_ready(mac_regs))
 379                 return -ETIME;
 380
 381         miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 382                (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 383                PCH_GBE_MIIM_OPER_WRITE | val;
 384         writel(miim, &mac_regs->miim);
 385
 386         if (pch_gbe_mdio_ready(mac_regs))
 387                 return -ETIME;
 388         else
 389                 return 0;
 390 }
 391
 392 static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
 393 {
 394         struct mii_dev *bus;
 395
 396         bus = mdio_alloc();
 397         if (!bus) {
 398                 debug("pch_gbe: failed to allocate MDIO bus\n");
 399                 return -ENOMEM;
 400         }
 401
 402         bus->read = pch_gbe_mdio_read;
 403         bus->write = pch_gbe_mdio_write;
 404         strcpy(bus->name, name);
 405
 406         bus->priv = (void *)mac_regs;
 407
 408         return mdio_register(bus);
 409 }
 410
 411 static int pch_gbe_phy_init(struct udevice *dev)
 412 {
 413         struct pch_gbe_priv *priv = dev_get_priv(dev);
 414         struct eth_pdata *plat = dev_get_platdata(dev);
 415         struct phy_device *phydev;
 416         int mask = 0xffffffff;
 417
 418         phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
 419         if (!phydev) {
 420                 printf("pch_gbe: cannot find the phy\n");
 421                 return -1;
 422         }
 423
 424         phy_connect_dev(phydev, dev);
 425
 426         phydev->supported &= PHY_GBIT_FEATURES;
 427         phydev->advertising = phydev->supported;
 428
 429         priv->phydev = phydev;
 430         phy_config(phydev);
 431
 432         return 0;
 433 }
 434
 435 static int pch_gbe_probe(struct udevice *dev)
 436 {
 437         struct pch_gbe_priv *priv;
 438         struct eth_pdata *plat = dev_get_platdata(dev);
 439         void *iobase;
 440         int err;
 441
 442         /*
 443          * The priv structure contains the descriptors and frame buffers which
 444          * need a strict buswidth alignment (64 bytes). This is guaranteed by
 445          * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
 446          */
 447         priv = dev_get_priv(dev);
 448
 449         priv->dev = dev;
 450
 451         iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
 452
 453         plat->iobase = (ulong)iobase;
 454         priv->mac_regs = (struct pch_gbe_regs *)iobase;
 455
 456         /* Read MAC address from SROM and initialize dev->enetaddr with it */
 457         pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
 458
 459         plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
 460         pch_gbe_mdio_init(dev->name, priv->mac_regs);
 461         priv->bus = miiphy_get_dev_by_name(dev->name);
 462
 463         err = pch_gbe_reset(dev);
 464         if (err)
 465                 return err;
 466
 467         return pch_gbe_phy_init(dev);
 468 }
 469
 470 static int pch_gbe_remove(struct udevice *dev)
 471 {
 472         struct pch_gbe_priv *priv = dev_get_priv(dev);
 473
 474         free(priv->phydev);
 475         mdio_unregister(priv->bus);
 476         mdio_free(priv->bus);
 477
 478         return 0;
 479 }
 480
 481 static const struct eth_ops pch_gbe_ops = {
 482         .start = pch_gbe_start,
 483         .send = pch_gbe_send,
 484         .recv = pch_gbe_recv,
 485         .free_pkt = pch_gbe_free_pkt,
 486         .stop = pch_gbe_stop,
 487 };
 488
 489 static const struct udevice_id pch_gbe_ids[] = {
 490         { .compatible = "intel,pch-gbe" },
 491         { }
 492 };
 493
 494 U_BOOT_DRIVER(eth_pch_gbe) = {
 495         .name = "pch_gbe",
 496         .id = UCLASS_ETH,
 497         .of_match = pch_gbe_ids,
 498         .probe = pch_gbe_probe,
 499         .remove = pch_gbe_remove,
 500         .ops = &pch_gbe_ops,
 501         .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
 502         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 503         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 504 };
 505
 506 U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);