2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
19 #include <asm/cache.h>
20 #include <dm/device-internal.h>
21 #include <dm/device_compat.h>
22 #include <dm/devres.h>
29 #include <linux/bug.h>
30 #include <linux/delay.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
36 #include <asm/arch/cpu.h>
37 #include <asm/arch/soc.h>
38 #include <linux/compat.h>
39 #include <linux/libfdt.h>
40 #include <linux/mbus.h>
41 #include <asm-generic/gpio.h>
42 #include <fdt_support.h>
43 #include <linux/mdio.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 #define __verify_pcpu_ptr(ptr) \
49 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
53 #define VERIFY_PERCPU_PTR(__p) \
55 __verify_pcpu_ptr(__p); \
56 (typeof(*(__p)) __kernel __force *)(__p); \
59 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
60 #define smp_processor_id() 0
61 #define num_present_cpus() 1
62 #define for_each_present_cpu(cpu) \
63 for ((cpu) = 0; (cpu) < 1; (cpu)++)
65 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
67 #define CONFIG_NR_CPUS 1
69 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
70 #define WRAP (2 + ETH_HLEN + 4 + 32)
72 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
74 /* RX Fifo Registers */
75 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
76 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
77 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
78 #define MVPP2_RX_FIFO_INIT_REG 0x64
80 /* RX DMA Top Registers */
81 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
82 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
83 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
84 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
85 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
86 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
87 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
88 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
89 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
90 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
91 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
92 #define MVPP2_RXQ_POOL_LONG_OFFS 24
93 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
94 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
95 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
96 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
97 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
99 /* Parser Registers */
100 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
101 #define MVPP2_PRS_PORT_LU_MAX 0xf
102 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
103 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
104 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
105 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
106 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
107 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
108 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
109 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
110 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
111 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
112 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
113 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
114 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
115 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
116 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
118 /* Classifier Registers */
119 #define MVPP2_CLS_MODE_REG 0x1800
120 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
121 #define MVPP2_CLS_PORT_WAY_REG 0x1810
122 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
123 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
124 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
125 #define MVPP2_CLS_LKP_TBL_REG 0x1818
126 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
127 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
128 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
129 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
130 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
131 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
132 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
133 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
134 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
135 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
136 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
137 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
139 /* Descriptor Manager Top Registers */
140 #define MVPP2_RXQ_NUM_REG 0x2040
141 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
142 #define MVPP22_DESC_ADDR_OFFS 8
143 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
144 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
145 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
146 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
147 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
148 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
149 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
150 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
151 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
152 #define MVPP2_RXQ_THRESH_REG 0x204c
153 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
154 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
155 #define MVPP2_RXQ_INDEX_REG 0x2050
156 #define MVPP2_TXQ_NUM_REG 0x2080
157 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
158 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
159 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
160 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
161 #define MVPP2_TXQ_THRESH_REG 0x2094
162 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
163 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
164 #define MVPP2_TXQ_INDEX_REG 0x2098
165 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
166 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
167 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
168 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
169 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
170 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
171 #define MVPP2_TXQ_PENDING_REG 0x20a0
172 #define MVPP2_TXQ_PENDING_MASK 0x3fff
173 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
174 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
175 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
176 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
177 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
178 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
179 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
180 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
181 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
182 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
183 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
184 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
185 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
186 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
187 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
188 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
189 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
191 /* MBUS bridge registers */
192 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
193 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
194 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
195 #define MVPP2_BASE_ADDR_ENABLE 0x4060
197 /* AXI Bridge Registers */
198 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
199 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
200 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
201 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
202 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
203 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
204 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
205 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
206 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
207 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
208 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
209 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
211 /* Values for AXI Bridge registers */
212 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
213 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
215 #define MVPP22_AXI_CODE_CACHE_OFFS 0
216 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
218 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
219 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
220 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
222 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
223 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
225 /* Interrupt Cause and Mask registers */
226 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
227 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
229 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
230 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
231 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
232 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
234 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
237 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
238 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
239 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
240 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
242 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
243 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
244 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
245 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
246 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
247 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
248 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
249 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
250 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
251 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
252 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
253 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
254 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
255 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
256 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
257 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
258 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
259 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
261 /* Buffer Manager registers */
262 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
263 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
264 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
265 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
266 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
267 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
268 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
269 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
270 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
271 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
272 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
273 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
274 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
275 #define MVPP2_BM_START_MASK BIT(0)
276 #define MVPP2_BM_STOP_MASK BIT(1)
277 #define MVPP2_BM_STATE_MASK BIT(4)
278 #define MVPP2_BM_LOW_THRESH_OFFS 8
279 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
280 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
281 MVPP2_BM_LOW_THRESH_OFFS)
282 #define MVPP2_BM_HIGH_THRESH_OFFS 16
283 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
284 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
285 MVPP2_BM_HIGH_THRESH_OFFS)
286 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
287 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
288 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
289 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
290 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
291 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
292 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
293 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
294 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
295 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
296 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
297 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
298 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
299 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
300 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
301 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
302 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
303 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
304 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
305 #define MVPP21_BM_MC_RLS_REG 0x64c4
306 #define MVPP2_BM_MC_ID_MASK 0xfff
307 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
308 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
309 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
310 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
311 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
312 #define MVPP22_BM_MC_RLS_REG 0x64d4
313 #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
314 #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
316 /* TX Scheduler registers */
317 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
318 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
319 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
320 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
321 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
322 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
323 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
324 #define MVPP2_TXP_MTU_MAX 0x7FFFF
325 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
326 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
327 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
328 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
329 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
330 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
331 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
332 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
333 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
334 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
335 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
336 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
337 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
338 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
340 /* TX general registers */
341 #define MVPP2_TX_SNOOP_REG 0x8800
342 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
343 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
346 #define MVPP2_SRC_ADDR_MIDDLE 0x24
347 #define MVPP2_SRC_ADDR_HIGH 0x28
348 #define MVPP2_PHY_AN_CFG0_REG 0x34
349 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
350 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
351 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
353 /* Per-port registers */
354 #define MVPP2_GMAC_CTRL_0_REG 0x0
355 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
356 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
357 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
358 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
359 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
360 #define MVPP2_GMAC_CTRL_1_REG 0x4
361 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
362 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
363 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
364 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
365 #define MVPP2_GMAC_SA_LOW_OFFS 7
366 #define MVPP2_GMAC_CTRL_2_REG 0x8
367 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
368 #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
369 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
370 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
371 #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
372 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
373 #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
374 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
375 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
376 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
377 #define MVPP2_GMAC_EN_PCS_AN BIT(2)
378 #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
379 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
380 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
381 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
382 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
383 #define MVPP2_GMAC_EN_FC_AN BIT(11)
384 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
385 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
386 #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
387 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
388 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
389 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
390 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
391 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
392 #define MVPP2_GMAC_CTRL_4_REG 0x90
393 #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
394 #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
395 #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
396 #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
399 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
400 * relative to port->base.
403 /* Port Mac Control0 */
404 #define MVPP22_XLG_CTRL0_REG 0x100
405 #define MVPP22_XLG_PORT_EN BIT(0)
406 #define MVPP22_XLG_MAC_RESETN BIT(1)
407 #define MVPP22_XLG_RX_FC_EN BIT(7)
408 #define MVPP22_XLG_MIBCNT_DIS BIT(13)
409 /* Port Mac Control1 */
410 #define MVPP22_XLG_CTRL1_REG 0x104
411 #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
412 #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
413 /* Port Interrupt Mask */
414 #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
415 #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
416 /* Port Mac Control3 */
417 #define MVPP22_XLG_CTRL3_REG 0x11c
418 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
419 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
420 #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
421 /* Port Mac Control4 */
422 #define MVPP22_XLG_CTRL4_REG 0x184
423 #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
424 #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
425 #define MVPP22_XLG_MODE_DMA_1G BIT(12)
426 #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
430 /* Global Configuration 0 */
431 #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
432 #define MVPP22_XPCS_PCSRESET BIT(0)
433 #define MVPP22_XPCS_PCSMODE_OFFS 3
434 #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
435 MVPP22_XPCS_PCSMODE_OFFS)
436 #define MVPP22_XPCS_LANEACTIVE_OFFS 5
437 #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
438 MVPP22_XPCS_LANEACTIVE_OFFS)
442 #define PCS40G_COMMON_CONTROL 0x14
443 #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
445 #define PCS_CLOCK_RESET 0x14c
446 #define TX_SD_CLK_RESET_MASK BIT(0)
447 #define RX_SD_CLK_RESET_MASK BIT(1)
448 #define MAC_CLK_RESET_MASK BIT(2)
449 #define CLK_DIVISION_RATIO_OFFS 4
450 #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
451 #define CLK_DIV_PHASE_SET_MASK BIT(11)
453 /* System Soft Reset 1 */
454 #define GOP_SOFT_RESET_1_REG 0x108
455 #define NETC_GOP_SOFT_RESET_OFFS 6
456 #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
457 NETC_GOP_SOFT_RESET_OFFS)
459 /* Ports Control 0 */
460 #define NETCOMP_PORTS_CONTROL_0_REG 0x110
461 #define NETC_BUS_WIDTH_SELECT_OFFS 1
462 #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
463 NETC_BUS_WIDTH_SELECT_OFFS)
464 #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
465 #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
466 NETC_GIG_RX_DATA_SAMPLE_OFFS)
467 #define NETC_CLK_DIV_PHASE_OFFS 31
468 #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
469 /* Ports Control 1 */
470 #define NETCOMP_PORTS_CONTROL_1_REG 0x114
471 #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
472 #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
473 NETC_PORTS_ACTIVE_OFFSET(p))
474 #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
475 #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
476 NETC_PORT_GIG_RF_RESET_OFFS(p))
477 #define NETCOMP_CONTROL_0_REG 0x120
478 #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
479 #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
480 NETC_GBE_PORT0_SGMII_MODE_OFFS)
481 #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
482 #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
483 NETC_GBE_PORT1_SGMII_MODE_OFFS)
484 #define NETC_GBE_PORT1_MII_MODE_OFFS 2
485 #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
486 NETC_GBE_PORT1_MII_MODE_OFFS)
488 #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
489 #define MVPP22_SMI_POLLING_EN BIT(10)
491 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
494 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
496 /* Descriptor ring Macros */
497 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
498 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
500 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
501 #define MVPP22_SMI 0x1200
503 /* Additional PPv2.2 offsets */
504 #define MVPP22_MPCS 0x007000
505 #define MVPP22_XPCS 0x007400
506 #define MVPP22_PORT_BASE 0x007e00
507 #define MVPP22_PORT_OFFSET 0x001000
508 #define MVPP22_RFU1 0x318000
510 /* Maximum number of ports */
511 #define MVPP22_GOP_MAC_NUM 4
513 /* Sets the field located at the specified in data */
514 #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
515 #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
516 #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
519 enum mv_netc_topology {
520 MV_NETC_GE_MAC2_SGMII = BIT(0),
521 MV_NETC_GE_MAC3_SGMII = BIT(1),
522 MV_NETC_GE_MAC3_RGMII = BIT(2),
527 MV_NETC_SECOND_PHASE,
530 enum mv_netc_sgmii_xmi_mode {
535 enum mv_netc_mii_mode {
545 /* Various constants */
548 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
549 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
550 #define MVPP2_RX_COAL_PKTS 32
551 #define MVPP2_RX_COAL_USEC 100
553 /* The two bytes Marvell header. Either contains a special value used
554 * by Marvell switches when a specific hardware mode is enabled (not
555 * supported by this driver) or is filled automatically by zeroes on
556 * the RX side. Those two bytes being at the front of the Ethernet
557 * header, they allow to have the IP header aligned on a 4 bytes
558 * boundary automatically: the hardware skips those two bytes on its
561 #define MVPP2_MH_SIZE 2
562 #define MVPP2_ETH_TYPE_LEN 2
563 #define MVPP2_PPPOE_HDR_SIZE 8
564 #define MVPP2_VLAN_TAG_LEN 4
566 /* Lbtd 802.3 type */
567 #define MVPP2_IP_LBDT_TYPE 0xfffa
569 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
570 #define MVPP2_TX_CSUM_MAX_SIZE 9800
572 /* Timeout constants */
573 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
574 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
576 #define MVPP2_TX_MTU_MAX 0x7ffff
578 /* Maximum number of T-CONTs of PON port */
579 #define MVPP2_MAX_TCONT 16
581 /* Maximum number of supported ports */
582 #define MVPP2_MAX_PORTS 4
584 /* Maximum number of TXQs used by single port */
585 #define MVPP2_MAX_TXQ 8
587 /* Default number of TXQs in use */
588 #define MVPP2_DEFAULT_TXQ 1
590 /* Default number of RXQs in use */
591 #define MVPP2_DEFAULT_RXQ 1
592 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
594 /* Max number of Rx descriptors */
595 #define MVPP2_MAX_RXD 16
597 /* Max number of Tx descriptors */
598 #define MVPP2_MAX_TXD 16
600 /* Amount of Tx descriptors that can be reserved at once by CPU */
601 #define MVPP2_CPU_DESC_CHUNK 16
603 /* Max number of Tx descriptors in each aggregated queue */
604 #define MVPP2_AGGR_TXQ_SIZE 16
606 /* Descriptor aligned size */
607 #define MVPP2_DESC_ALIGNED_SIZE 32
609 /* Descriptor alignment mask */
610 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
612 /* RX FIFO constants */
613 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
614 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
615 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
616 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
617 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
618 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
619 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
620 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
621 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
623 /* TX general registers */
624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
625 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
627 /* TX FIFO constants */
628 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
629 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
631 /* RX buffer constants */
632 #define MVPP2_SKB_SHINFO_SIZE \
635 #define MVPP2_RX_PKT_SIZE(mtu) \
636 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
637 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
639 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
640 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
641 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
642 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
644 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
646 /* IPv6 max L3 address size */
647 #define MVPP2_MAX_L3_ADDR_SIZE 16
650 #define MVPP2_F_LOOPBACK BIT(0)
652 /* Marvell tag types */
653 enum mvpp2_tag_type {
654 MVPP2_TAG_TYPE_NONE = 0,
655 MVPP2_TAG_TYPE_MH = 1,
656 MVPP2_TAG_TYPE_DSA = 2,
657 MVPP2_TAG_TYPE_EDSA = 3,
658 MVPP2_TAG_TYPE_VLAN = 4,
659 MVPP2_TAG_TYPE_LAST = 5
662 /* Parser constants */
663 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
664 #define MVPP2_PRS_TCAM_WORDS 6
665 #define MVPP2_PRS_SRAM_WORDS 4
666 #define MVPP2_PRS_FLOW_ID_SIZE 64
667 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
668 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
669 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
670 #define MVPP2_PRS_IPV4_HEAD 0x40
671 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
672 #define MVPP2_PRS_IPV4_MC 0xe0
673 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
674 #define MVPP2_PRS_IPV4_BC_MASK 0xff
675 #define MVPP2_PRS_IPV4_IHL 0x5
676 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
677 #define MVPP2_PRS_IPV6_MC 0xff
678 #define MVPP2_PRS_IPV6_MC_MASK 0xff
679 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
680 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
681 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
682 #define MVPP2_PRS_DBL_VLANS_MAX 100
685 * - lookup ID - 4 bits
687 * - additional information - 1 byte
688 * - header data - 8 bytes
689 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
691 #define MVPP2_PRS_AI_BITS 8
692 #define MVPP2_PRS_PORT_MASK 0xff
693 #define MVPP2_PRS_LU_MASK 0xf
694 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
695 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
696 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
697 (((offs) * 2) - ((offs) % 2) + 2)
698 #define MVPP2_PRS_TCAM_AI_BYTE 16
699 #define MVPP2_PRS_TCAM_PORT_BYTE 17
700 #define MVPP2_PRS_TCAM_LU_BYTE 20
701 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
702 #define MVPP2_PRS_TCAM_INV_WORD 5
703 /* Tcam entries ID */
704 #define MVPP2_PE_DROP_ALL 0
705 #define MVPP2_PE_FIRST_FREE_TID 1
706 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
707 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
708 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
709 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
710 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
711 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
712 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
713 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
714 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
715 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
716 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
717 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
718 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
719 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
720 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
721 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
722 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
723 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
724 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
725 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
726 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
727 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
728 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
729 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
730 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
733 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
735 #define MVPP2_PRS_SRAM_RI_OFFS 0
736 #define MVPP2_PRS_SRAM_RI_WORD 0
737 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
738 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
739 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
740 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
741 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
742 #define MVPP2_PRS_SRAM_UDF_OFFS 73
743 #define MVPP2_PRS_SRAM_UDF_BITS 8
744 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
745 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
746 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
747 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
748 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
749 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
750 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
751 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
752 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
753 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
754 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
755 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
756 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
757 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
758 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
759 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
760 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
761 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
762 #define MVPP2_PRS_SRAM_AI_OFFS 90
763 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
764 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
765 #define MVPP2_PRS_SRAM_AI_MASK 0xff
766 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
767 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
768 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
769 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
771 /* Sram result info bits assignment */
772 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
773 #define MVPP2_PRS_RI_DSA_MASK 0x2
774 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
775 #define MVPP2_PRS_RI_VLAN_NONE 0x0
776 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
777 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
778 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
779 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
780 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
781 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
782 #define MVPP2_PRS_RI_L2_UCAST 0x0
783 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
784 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
785 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
786 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
787 #define MVPP2_PRS_RI_L3_UN 0x0
788 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
789 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
790 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
791 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
792 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
793 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
794 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
795 #define MVPP2_PRS_RI_L3_UCAST 0x0
796 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
797 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
798 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
799 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
800 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
801 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
802 #define MVPP2_PRS_RI_L4_TCP BIT(22)
803 #define MVPP2_PRS_RI_L4_UDP BIT(23)
804 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
805 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
806 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
807 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
809 /* Sram additional info bits assignment */
810 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
811 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
812 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
813 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
814 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
815 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
816 #define MVPP2_PRS_SINGLE_VLAN_AI 0
817 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
820 #define MVPP2_PRS_TAGGED true
821 #define MVPP2_PRS_UNTAGGED false
822 #define MVPP2_PRS_EDSA true
823 #define MVPP2_PRS_DSA false
825 /* MAC entries, shadow udf */
827 MVPP2_PRS_UDF_MAC_DEF,
828 MVPP2_PRS_UDF_MAC_RANGE,
829 MVPP2_PRS_UDF_L2_DEF,
830 MVPP2_PRS_UDF_L2_DEF_COPY,
831 MVPP2_PRS_UDF_L2_USER,
835 enum mvpp2_prs_lookup {
849 enum mvpp2_prs_l3_cast {
850 MVPP2_PRS_L3_UNI_CAST,
851 MVPP2_PRS_L3_MULTI_CAST,
852 MVPP2_PRS_L3_BROAD_CAST
855 /* Classifier constants */
856 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
857 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
858 #define MVPP2_CLS_LKP_TBL_SIZE 64
861 #define MVPP2_BM_POOLS_NUM 1
862 #define MVPP2_BM_LONG_BUF_NUM 16
863 #define MVPP2_BM_SHORT_BUF_NUM 16
864 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
865 #define MVPP2_BM_POOL_PTR_ALIGN 128
866 #define MVPP2_BM_SWF_LONG_POOL(port) 0
868 /* BM cookie (32 bits) definition */
869 #define MVPP2_BM_COOKIE_POOL_OFFS 8
870 #define MVPP2_BM_COOKIE_CPU_OFFS 24
872 /* BM short pool packet size
873 * These value assure that for SWF the total number
874 * of bytes allocated for each buffer will be 512
876 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
886 /* Shared Packet Processor resources */
888 /* Shared registers' base addresses */
890 void __iomem *lms_base;
891 void __iomem *iface_base;
893 void __iomem *mpcs_base;
894 void __iomem *xpcs_base;
895 void __iomem *rfu1_base;
899 /* List of pointers to port structures */
900 struct mvpp2_port **port_list;
902 /* Aggregated TXQs */
903 struct mvpp2_tx_queue *aggr_txqs;
906 struct mvpp2_bm_pool *bm_pools;
908 /* PRS shadow table */
909 struct mvpp2_prs_shadow *prs_shadow;
910 /* PRS auxiliary table for double vlan entries control */
911 bool *prs_double_vlans;
917 enum { MVPP21, MVPP22 } hw_version;
919 /* Maximum number of RXQs per port */
920 unsigned int max_port_rxqs;
926 struct mvpp2_pcpu_stats {
936 /* Index of the port from the "group of ports" complex point
945 /* Per-port registers' base address */
948 struct mvpp2_rx_queue **rxqs;
949 struct mvpp2_tx_queue **txqs;
953 u32 pending_cause_rx;
955 /* Per-CPU port control */
956 struct mvpp2_port_pcpu __percpu *pcpu;
963 struct mvpp2_pcpu_stats __percpu *stats;
965 struct phy_device *phy_dev;
966 phy_interface_t phy_interface;
968 struct udevice *mdio_dev;
970 #if CONFIG_IS_ENABLED(DM_GPIO)
971 struct gpio_desc phy_reset_gpio;
972 struct gpio_desc phy_tx_disable_gpio;
979 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
981 struct mvpp2_bm_pool *pool_long;
982 struct mvpp2_bm_pool *pool_short;
984 /* Index of first port's physical RXQ */
987 u8 dev_addr[ETH_ALEN];
990 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
991 * layout of the transmit and reception DMA descriptors, and their
992 * layout is therefore defined by the hardware design
995 #define MVPP2_TXD_L3_OFF_SHIFT 0
996 #define MVPP2_TXD_IP_HLEN_SHIFT 8
997 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
998 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
999 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
1000 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
1001 #define MVPP2_TXD_L4_UDP BIT(24)
1002 #define MVPP2_TXD_L3_IP6 BIT(26)
1003 #define MVPP2_TXD_L_DESC BIT(28)
1004 #define MVPP2_TXD_F_DESC BIT(29)
1006 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
1007 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1008 #define MVPP2_RXD_ERR_CRC 0x0
1009 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
1010 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1011 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
1012 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1013 #define MVPP2_RXD_HWF_SYNC BIT(21)
1014 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
1015 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1016 #define MVPP2_RXD_L4_TCP BIT(25)
1017 #define MVPP2_RXD_L4_UDP BIT(26)
1018 #define MVPP2_RXD_L3_IP4 BIT(28)
1019 #define MVPP2_RXD_L3_IP6 BIT(30)
1020 #define MVPP2_RXD_BUF_HDR BIT(31)
1022 /* HW TX descriptor for PPv2.1 */
1023 struct mvpp21_tx_desc {
1024 u32 command; /* Options used by HW for packet transmitting.*/
1025 u8 packet_offset; /* the offset from the buffer beginning */
1026 u8 phys_txq; /* destination queue ID */
1027 u16 data_size; /* data size of transmitted packet in bytes */
1028 u32 buf_dma_addr; /* physical addr of transmitted buffer */
1029 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1030 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1031 u32 reserved2; /* reserved (for future use) */
1034 /* HW RX descriptor for PPv2.1 */
1035 struct mvpp21_rx_desc {
1036 u32 status; /* info about received packet */
1037 u16 reserved1; /* parser_info (for future use, PnC) */
1038 u16 data_size; /* size of received packet in bytes */
1039 u32 buf_dma_addr; /* physical address of the buffer */
1040 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1041 u16 reserved2; /* gem_port_id (for future use, PON) */
1042 u16 reserved3; /* csum_l4 (for future use, PnC) */
1043 u8 reserved4; /* bm_qset (for future use, BM) */
1045 u16 reserved6; /* classify_info (for future use, PnC) */
1046 u32 reserved7; /* flow_id (for future use, PnC) */
1050 /* HW TX descriptor for PPv2.2 */
1051 struct mvpp22_tx_desc {
1057 u64 buf_dma_addr_ptp;
1058 u64 buf_cookie_misc;
1061 /* HW RX descriptor for PPv2.2 */
1062 struct mvpp22_rx_desc {
1068 u64 buf_dma_addr_key_hash;
1069 u64 buf_cookie_misc;
1072 /* Opaque type used by the driver to manipulate the HW TX and RX
1075 struct mvpp2_tx_desc {
1077 struct mvpp21_tx_desc pp21;
1078 struct mvpp22_tx_desc pp22;
1082 struct mvpp2_rx_desc {
1084 struct mvpp21_rx_desc pp21;
1085 struct mvpp22_rx_desc pp22;
1089 /* Per-CPU Tx queue control */
1090 struct mvpp2_txq_pcpu {
1093 /* Number of Tx DMA descriptors in the descriptor ring */
1096 /* Number of currently used Tx DMA descriptor in the
1101 /* Number of Tx DMA descriptors reserved for each CPU */
1104 /* Index of last TX DMA descriptor that was inserted */
1107 /* Index of the TX DMA descriptor to be cleaned up */
1111 struct mvpp2_tx_queue {
1112 /* Physical number of this Tx queue */
1115 /* Logical number of this Tx queue */
1118 /* Number of Tx DMA descriptors in the descriptor ring */
1121 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1124 /* Per-CPU control of physical Tx queues */
1125 struct mvpp2_txq_pcpu __percpu *pcpu;
1129 /* Virtual address of thex Tx DMA descriptors array */
1130 struct mvpp2_tx_desc *descs;
1132 /* DMA address of the Tx DMA descriptors array */
1133 dma_addr_t descs_dma;
1135 /* Index of the last Tx DMA descriptor */
1138 /* Index of the next Tx DMA descriptor to process */
1139 int next_desc_to_proc;
1142 struct mvpp2_rx_queue {
1143 /* RX queue number, in the range 0-31 for physical RXQs */
1146 /* Num of rx descriptors in the rx descriptor ring */
1152 /* Virtual address of the RX DMA descriptors array */
1153 struct mvpp2_rx_desc *descs;
1155 /* DMA address of the RX DMA descriptors array */
1156 dma_addr_t descs_dma;
1158 /* Index of the last RX DMA descriptor */
1161 /* Index of the next RX DMA descriptor to process */
1162 int next_desc_to_proc;
1164 /* ID of port to which physical RXQ is mapped */
1167 /* Port's logic RXQ number to which physical RXQ is mapped */
1171 union mvpp2_prs_tcam_entry {
1172 u32 word[MVPP2_PRS_TCAM_WORDS];
1173 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1176 union mvpp2_prs_sram_entry {
1177 u32 word[MVPP2_PRS_SRAM_WORDS];
1178 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1181 struct mvpp2_prs_entry {
1183 union mvpp2_prs_tcam_entry tcam;
1184 union mvpp2_prs_sram_entry sram;
1187 struct mvpp2_prs_shadow {
1194 /* User defined offset */
1202 struct mvpp2_cls_flow_entry {
1204 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1207 struct mvpp2_cls_lookup_entry {
1213 struct mvpp2_bm_pool {
1214 /* Pool number in the range 0-7 */
1216 enum mvpp2_bm_type type;
1218 /* Buffer Pointers Pool External (BPPE) size */
1220 /* Number of buffers for this pool */
1222 /* Pool buffer size */
1227 /* BPPE virtual base address */
1228 unsigned long *virt_addr;
1229 /* BPPE DMA base address */
1230 dma_addr_t dma_addr;
1232 /* Ports using BM pool */
1236 /* Static declaractions */
1238 /* Number of RXQs used by single port */
1239 static int rxq_number = MVPP2_DEFAULT_RXQ;
1240 /* Number of TXQs used by single port */
1241 static int txq_number = MVPP2_DEFAULT_TXQ;
1245 #define MVPP2_DRIVER_NAME "mvpp2"
1246 #define MVPP2_DRIVER_VERSION "1.0"
1249 * U-Boot internal data, mostly uncached buffers for descriptors and data
1251 struct buffer_location {
1252 struct mvpp2_tx_desc *aggr_tx_descs;
1253 struct mvpp2_tx_desc *tx_descs;
1254 struct mvpp2_rx_desc *rx_descs;
1255 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1256 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1261 * All 4 interfaces use the same global buffer, since only one interface
1262 * can be enabled at once
1264 static struct buffer_location buffer_loc;
1267 * Page table entries are set to 1MB, or multiples of 1MB
1268 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1270 #define BD_SPACE (1 << 20)
1272 /* Utility/helper methods */
1274 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1276 writel(data, priv->base + offset);
1279 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1281 return readl(priv->base + offset);
1284 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1285 struct mvpp2_tx_desc *tx_desc,
1286 dma_addr_t dma_addr)
1288 if (port->priv->hw_version == MVPP21) {
1289 tx_desc->pp21.buf_dma_addr = dma_addr;
1291 u64 val = (u64)dma_addr;
1293 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1294 tx_desc->pp22.buf_dma_addr_ptp |= val;
1298 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1299 struct mvpp2_tx_desc *tx_desc,
1302 if (port->priv->hw_version == MVPP21)
1303 tx_desc->pp21.data_size = size;
1305 tx_desc->pp22.data_size = size;
1308 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1309 struct mvpp2_tx_desc *tx_desc,
1312 if (port->priv->hw_version == MVPP21)
1313 tx_desc->pp21.phys_txq = txq;
1315 tx_desc->pp22.phys_txq = txq;
1318 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1319 struct mvpp2_tx_desc *tx_desc,
1320 unsigned int command)
1322 if (port->priv->hw_version == MVPP21)
1323 tx_desc->pp21.command = command;
1325 tx_desc->pp22.command = command;
1328 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1329 struct mvpp2_tx_desc *tx_desc,
1330 unsigned int offset)
1332 if (port->priv->hw_version == MVPP21)
1333 tx_desc->pp21.packet_offset = offset;
1335 tx_desc->pp22.packet_offset = offset;
1338 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1339 struct mvpp2_rx_desc *rx_desc)
1341 if (port->priv->hw_version == MVPP21)
1342 return rx_desc->pp21.buf_dma_addr;
1344 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1347 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1348 struct mvpp2_rx_desc *rx_desc)
1350 if (port->priv->hw_version == MVPP21)
1351 return rx_desc->pp21.buf_cookie;
1353 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1356 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1357 struct mvpp2_rx_desc *rx_desc)
1359 if (port->priv->hw_version == MVPP21)
1360 return rx_desc->pp21.data_size;
1362 return rx_desc->pp22.data_size;
1365 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1366 struct mvpp2_rx_desc *rx_desc)
1368 if (port->priv->hw_version == MVPP21)
1369 return rx_desc->pp21.status;
1371 return rx_desc->pp22.status;
1374 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1376 txq_pcpu->txq_get_index++;
1377 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1378 txq_pcpu->txq_get_index = 0;
1381 /* Get number of physical egress port */
1382 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1384 return MVPP2_MAX_TCONT + port->id;
1387 /* Get number of physical TXQ */
1388 static inline int mvpp2_txq_phys(int port, int txq)
1390 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1393 /* Parser configuration routines */
1395 /* Update parser tcam and sram hw entries */
1396 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1400 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1403 /* Clear entry invalidation bit */
1404 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1406 /* Write tcam index - indirect access */
1407 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1408 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1409 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1411 /* Write sram index - indirect access */
1412 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1413 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1414 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1419 /* Read tcam entry from hw */
1420 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1424 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1427 /* Write tcam index - indirect access */
1428 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1430 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1431 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1432 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1433 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1435 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1436 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1438 /* Write sram index - indirect access */
1439 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1440 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1441 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1446 /* Invalidate tcam hw entry */
1447 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1449 /* Write index - indirect access */
1450 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1451 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1452 MVPP2_PRS_TCAM_INV_MASK);
1455 /* Enable shadow table entry and set its lookup ID */
1456 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1458 priv->prs_shadow[index].valid = true;
1459 priv->prs_shadow[index].lu = lu;
1462 /* Update ri fields in shadow table entry */
1463 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1464 unsigned int ri, unsigned int ri_mask)
1466 priv->prs_shadow[index].ri_mask = ri_mask;
1467 priv->prs_shadow[index].ri = ri;
1470 /* Update lookup field in tcam sw entry */
1471 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1473 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1475 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1476 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1479 /* Update mask for single port in tcam sw entry */
1480 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1481 unsigned int port, bool add)
1483 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1486 pe->tcam.byte[enable_off] &= ~(1 << port);
1488 pe->tcam.byte[enable_off] |= 1 << port;
1491 /* Update port map in tcam sw entry */
1492 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1495 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1496 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1498 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1499 pe->tcam.byte[enable_off] &= ~port_mask;
1500 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1503 /* Obtain port map from tcam sw entry */
1504 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1506 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1508 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1511 /* Set byte of data and its enable bits in tcam sw entry */
1512 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1513 unsigned int offs, unsigned char byte,
1514 unsigned char enable)
1516 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1517 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1520 /* Get byte of data and its enable bits from tcam sw entry */
1521 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1522 unsigned int offs, unsigned char *byte,
1523 unsigned char *enable)
1525 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1526 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1529 /* Set ethertype in tcam sw entry */
1530 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1531 unsigned short ethertype)
1533 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1534 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1537 /* Set bits in sram sw entry */
1538 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1541 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1544 /* Clear bits in sram sw entry */
1545 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1548 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1551 /* Update ri bits in sram sw entry */
1552 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1553 unsigned int bits, unsigned int mask)
1557 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1558 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1560 if (!(mask & BIT(i)))
1564 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1566 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1568 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1572 /* Update ai bits in sram sw entry */
1573 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1574 unsigned int bits, unsigned int mask)
1577 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1579 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1581 if (!(mask & BIT(i)))
1585 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1587 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1589 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1593 /* Read ai bits from sram sw entry */
1594 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1597 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1598 int ai_en_off = ai_off + 1;
1599 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1601 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1602 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1607 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1610 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1613 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1615 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1616 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1617 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1620 /* In the sram sw entry set sign and value of the next lookup offset
1621 * and the offset value generated to the classifier
1623 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1628 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1631 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1635 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1636 (unsigned char)shift;
1638 /* Reset and set operation */
1639 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1640 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1641 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1643 /* Set base offset as current */
1644 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1647 /* In the sram sw entry set sign and value of the user defined offset
1648 * generated to the classifier
1650 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1651 unsigned int type, int offset,
1656 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1657 offset = 0 - offset;
1659 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1663 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1664 MVPP2_PRS_SRAM_UDF_MASK);
1665 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1666 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1667 MVPP2_PRS_SRAM_UDF_BITS)] &=
1668 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1669 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1670 MVPP2_PRS_SRAM_UDF_BITS)] |=
1671 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1673 /* Set offset type */
1674 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1675 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1676 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1678 /* Set offset operation */
1679 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1680 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1681 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1683 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1684 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1685 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1686 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1688 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1689 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1690 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1692 /* Set base offset as current */
1693 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1696 /* Find parser flow entry */
1697 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1699 struct mvpp2_prs_entry *pe;
1702 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1705 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1707 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1708 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1711 if (!priv->prs_shadow[tid].valid ||
1712 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1716 mvpp2_prs_hw_read(priv, pe);
1717 bits = mvpp2_prs_sram_ai_get(pe);
1719 /* Sram store classification lookup ID in AI bits [5:0] */
1720 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1728 /* Return first free tcam index, seeking from start to end */
1729 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1737 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1738 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1740 for (tid = start; tid <= end; tid++) {
1741 if (!priv->prs_shadow[tid].valid)
1748 /* Enable/disable dropping all mac da's */
1749 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1751 struct mvpp2_prs_entry pe;
1753 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1754 /* Entry exist - update port only */
1755 pe.index = MVPP2_PE_DROP_ALL;
1756 mvpp2_prs_hw_read(priv, &pe);
1758 /* Entry doesn't exist - create new */
1759 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1760 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1761 pe.index = MVPP2_PE_DROP_ALL;
1763 /* Non-promiscuous mode for all ports - DROP unknown packets */
1764 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1765 MVPP2_PRS_RI_DROP_MASK);
1767 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1768 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1770 /* Update shadow table */
1771 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1773 /* Mask all ports */
1774 mvpp2_prs_tcam_port_map_set(&pe, 0);
1777 /* Update port mask */
1778 mvpp2_prs_tcam_port_set(&pe, port, add);
1780 mvpp2_prs_hw_write(priv, &pe);
1783 /* Set port to promiscuous mode */
1784 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1786 struct mvpp2_prs_entry pe;
1788 /* Promiscuous mode - Accept unknown packets */
1790 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1791 /* Entry exist - update port only */
1792 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1793 mvpp2_prs_hw_read(priv, &pe);
1795 /* Entry doesn't exist - create new */
1796 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1797 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1798 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1800 /* Continue - set next lookup */
1801 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1803 /* Set result info bits */
1804 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1805 MVPP2_PRS_RI_L2_CAST_MASK);
1807 /* Shift to ethertype */
1808 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1809 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1811 /* Mask all ports */
1812 mvpp2_prs_tcam_port_map_set(&pe, 0);
1814 /* Update shadow table */
1815 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1818 /* Update port mask */
1819 mvpp2_prs_tcam_port_set(&pe, port, add);
1821 mvpp2_prs_hw_write(priv, &pe);
1824 /* Accept multicast */
1825 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1828 struct mvpp2_prs_entry pe;
1829 unsigned char da_mc;
1831 /* Ethernet multicast address first byte is
1832 * 0x01 for IPv4 and 0x33 for IPv6
1834 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1836 if (priv->prs_shadow[index].valid) {
1837 /* Entry exist - update port only */
1839 mvpp2_prs_hw_read(priv, &pe);
1841 /* Entry doesn't exist - create new */
1842 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1843 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1846 /* Continue - set next lookup */
1847 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1849 /* Set result info bits */
1850 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1851 MVPP2_PRS_RI_L2_CAST_MASK);
1853 /* Update tcam entry data first byte */
1854 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1856 /* Shift to ethertype */
1857 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1858 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1860 /* Mask all ports */
1861 mvpp2_prs_tcam_port_map_set(&pe, 0);
1863 /* Update shadow table */
1864 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1867 /* Update port mask */
1868 mvpp2_prs_tcam_port_set(&pe, port, add);
1870 mvpp2_prs_hw_write(priv, &pe);
1873 /* Parser per-port initialization */
1874 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1875 int lu_max, int offset)
1880 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1881 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1882 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1883 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1885 /* Set maximum number of loops for packet received from port */
1886 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1887 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1888 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1889 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1891 /* Set initial offset for packet header extraction for the first
1894 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1895 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1896 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1897 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1900 /* Default flow entries initialization for all ports */
1901 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1903 struct mvpp2_prs_entry pe;
1906 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1907 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1908 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1909 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1911 /* Mask all ports */
1912 mvpp2_prs_tcam_port_map_set(&pe, 0);
1915 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1916 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1918 /* Update shadow table and hw entry */
1919 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1920 mvpp2_prs_hw_write(priv, &pe);
1924 /* Set default entry for Marvell Header field */
1925 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1927 struct mvpp2_prs_entry pe;
1929 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1931 pe.index = MVPP2_PE_MH_DEFAULT;
1932 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1933 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1934 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1935 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1937 /* Unmask all ports */
1938 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1940 /* Update shadow table and hw entry */
1941 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1942 mvpp2_prs_hw_write(priv, &pe);
1945 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1946 * multicast MAC addresses
1948 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1950 struct mvpp2_prs_entry pe;
1952 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1954 /* Non-promiscuous mode for all ports - DROP unknown packets */
1955 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1956 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1958 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1959 MVPP2_PRS_RI_DROP_MASK);
1960 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1961 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1963 /* Unmask all ports */
1964 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1966 /* Update shadow table and hw entry */
1967 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1968 mvpp2_prs_hw_write(priv, &pe);
1970 /* place holders only - no ports */
1971 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1972 mvpp2_prs_mac_promisc_set(priv, 0, false);
1973 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1974 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1977 /* Match basic ethertypes */
1978 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1980 struct mvpp2_prs_entry pe;
1983 /* Ethertype: PPPoE */
1984 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1985 MVPP2_PE_LAST_FREE_TID);
1989 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1990 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1993 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1995 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1996 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1997 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1998 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1999 MVPP2_PRS_RI_PPPOE_MASK);
2001 /* Update shadow table and hw entry */
2002 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2003 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2004 priv->prs_shadow[pe.index].finish = false;
2005 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2006 MVPP2_PRS_RI_PPPOE_MASK);
2007 mvpp2_prs_hw_write(priv, &pe);
2009 /* Ethertype: ARP */
2010 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2011 MVPP2_PE_LAST_FREE_TID);
2015 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2016 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2019 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2021 /* Generate flow in the next iteration*/
2022 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2023 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2024 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2025 MVPP2_PRS_RI_L3_PROTO_MASK);
2027 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2029 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2031 /* Update shadow table and hw entry */
2032 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2033 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2034 priv->prs_shadow[pe.index].finish = true;
2035 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2036 MVPP2_PRS_RI_L3_PROTO_MASK);
2037 mvpp2_prs_hw_write(priv, &pe);
2039 /* Ethertype: LBTD */
2040 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2041 MVPP2_PE_LAST_FREE_TID);
2045 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2046 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2049 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2051 /* Generate flow in the next iteration*/
2052 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2053 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2054 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2055 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2056 MVPP2_PRS_RI_CPU_CODE_MASK |
2057 MVPP2_PRS_RI_UDF3_MASK);
2059 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2061 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2063 /* Update shadow table and hw entry */
2064 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2065 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2066 priv->prs_shadow[pe.index].finish = true;
2067 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2068 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2069 MVPP2_PRS_RI_CPU_CODE_MASK |
2070 MVPP2_PRS_RI_UDF3_MASK);
2071 mvpp2_prs_hw_write(priv, &pe);
2073 /* Ethertype: IPv4 without options */
2074 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2075 MVPP2_PE_LAST_FREE_TID);
2079 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2080 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2083 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2084 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2085 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2086 MVPP2_PRS_IPV4_HEAD_MASK |
2087 MVPP2_PRS_IPV4_IHL_MASK);
2089 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2090 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2091 MVPP2_PRS_RI_L3_PROTO_MASK);
2092 /* Skip eth_type + 4 bytes of IP header */
2093 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2094 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2096 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2098 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2100 /* Update shadow table and hw entry */
2101 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2102 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2103 priv->prs_shadow[pe.index].finish = false;
2104 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2105 MVPP2_PRS_RI_L3_PROTO_MASK);
2106 mvpp2_prs_hw_write(priv, &pe);
2108 /* Ethertype: IPv4 with options */
2109 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2110 MVPP2_PE_LAST_FREE_TID);
2116 /* Clear tcam data before updating */
2117 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2118 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2120 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2121 MVPP2_PRS_IPV4_HEAD,
2122 MVPP2_PRS_IPV4_HEAD_MASK);
2124 /* Clear ri before updating */
2125 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2126 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2127 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2128 MVPP2_PRS_RI_L3_PROTO_MASK);
2130 /* Update shadow table and hw entry */
2131 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2132 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2133 priv->prs_shadow[pe.index].finish = false;
2134 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2135 MVPP2_PRS_RI_L3_PROTO_MASK);
2136 mvpp2_prs_hw_write(priv, &pe);
2138 /* Ethertype: IPv6 without options */
2139 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2140 MVPP2_PE_LAST_FREE_TID);
2144 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2145 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2148 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2150 /* Skip DIP of IPV6 header */
2151 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2152 MVPP2_MAX_L3_ADDR_SIZE,
2153 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2154 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2155 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2156 MVPP2_PRS_RI_L3_PROTO_MASK);
2158 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2160 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2162 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2163 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2164 priv->prs_shadow[pe.index].finish = false;
2165 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2166 MVPP2_PRS_RI_L3_PROTO_MASK);
2167 mvpp2_prs_hw_write(priv, &pe);
2169 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2170 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2171 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2172 pe.index = MVPP2_PE_ETH_TYPE_UN;
2174 /* Unmask all ports */
2175 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2177 /* Generate flow in the next iteration*/
2178 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2179 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2180 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2181 MVPP2_PRS_RI_L3_PROTO_MASK);
2182 /* Set L3 offset even it's unknown L3 */
2183 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2185 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2187 /* Update shadow table and hw entry */
2188 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2189 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2190 priv->prs_shadow[pe.index].finish = true;
2191 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2192 MVPP2_PRS_RI_L3_PROTO_MASK);
2193 mvpp2_prs_hw_write(priv, &pe);
2198 /* Parser default initialization */
2199 static int mvpp2_prs_default_init(struct udevice *dev,
2204 /* Enable tcam table */
2205 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2207 /* Clear all tcam and sram entries */
2208 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2209 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2210 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2211 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2213 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2214 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2215 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2218 /* Invalidate all tcam entries */
2219 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2220 mvpp2_prs_hw_inv(priv, index);
2222 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2223 sizeof(struct mvpp2_prs_shadow),
2225 if (!priv->prs_shadow)
2228 /* Always start from lookup = 0 */
2229 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2230 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2231 MVPP2_PRS_PORT_LU_MAX, 0);
2233 mvpp2_prs_def_flow_init(priv);
2235 mvpp2_prs_mh_init(priv);
2237 mvpp2_prs_mac_init(priv);
2239 err = mvpp2_prs_etype_init(priv);
2246 /* Compare MAC DA with tcam entry data */
2247 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2248 const u8 *da, unsigned char *mask)
2250 unsigned char tcam_byte, tcam_mask;
2253 for (index = 0; index < ETH_ALEN; index++) {
2254 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2255 if (tcam_mask != mask[index])
2258 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2265 /* Find tcam entry with matched pair <MAC DA, port> */
2266 static struct mvpp2_prs_entry *
2267 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2268 unsigned char *mask, int udf_type)
2270 struct mvpp2_prs_entry *pe;
2273 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2276 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2278 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2279 for (tid = MVPP2_PE_FIRST_FREE_TID;
2280 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2281 unsigned int entry_pmap;
2283 if (!priv->prs_shadow[tid].valid ||
2284 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2285 (priv->prs_shadow[tid].udf != udf_type))
2289 mvpp2_prs_hw_read(priv, pe);
2290 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2292 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2301 /* Update parser's mac da entry */
2302 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2303 const u8 *da, bool add)
2305 struct mvpp2_prs_entry *pe;
2306 unsigned int pmap, len, ri;
2307 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2310 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2311 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2312 MVPP2_PRS_UDF_MAC_DEF);
2319 /* Create new TCAM entry */
2320 /* Find first range mac entry*/
2321 for (tid = MVPP2_PE_FIRST_FREE_TID;
2322 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2323 if (priv->prs_shadow[tid].valid &&
2324 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2325 (priv->prs_shadow[tid].udf ==
2326 MVPP2_PRS_UDF_MAC_RANGE))
2329 /* Go through the all entries from first to last */
2330 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2335 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2338 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2341 /* Mask all ports */
2342 mvpp2_prs_tcam_port_map_set(pe, 0);
2345 /* Update port mask */
2346 mvpp2_prs_tcam_port_set(pe, port, add);
2348 /* Invalidate the entry if no ports are left enabled */
2349 pmap = mvpp2_prs_tcam_port_map_get(pe);
2355 mvpp2_prs_hw_inv(priv, pe->index);
2356 priv->prs_shadow[pe->index].valid = false;
2361 /* Continue - set next lookup */
2362 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2364 /* Set match on DA */
2367 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2369 /* Set result info bits */
2370 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2372 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2373 MVPP2_PRS_RI_MAC_ME_MASK);
2374 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2375 MVPP2_PRS_RI_MAC_ME_MASK);
2377 /* Shift to ethertype */
2378 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2379 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2381 /* Update shadow table and hw entry */
2382 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2383 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2384 mvpp2_prs_hw_write(priv, pe);
2391 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2395 /* Remove old parser entry */
2396 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2401 /* Add new parser entry */
2402 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2406 /* Set addr in the device */
2407 memcpy(port->dev_addr, da, ETH_ALEN);
2412 /* Set prs flow for the port */
2413 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2415 struct mvpp2_prs_entry *pe;
2418 pe = mvpp2_prs_flow_find(port->priv, port->id);
2420 /* Such entry not exist */
2422 /* Go through the all entires from last to first */
2423 tid = mvpp2_prs_tcam_first_free(port->priv,
2424 MVPP2_PE_LAST_FREE_TID,
2425 MVPP2_PE_FIRST_FREE_TID);
2429 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2433 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2437 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2438 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2440 /* Update shadow table */
2441 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2444 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2445 mvpp2_prs_hw_write(port->priv, pe);
2451 /* Classifier configuration routines */
2453 /* Update classification flow table registers */
2454 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2455 struct mvpp2_cls_flow_entry *fe)
2457 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2458 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2459 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2460 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2463 /* Update classification lookup table register */
2464 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2465 struct mvpp2_cls_lookup_entry *le)
2469 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2470 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2471 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2474 /* Classifier default initialization */
2475 static void mvpp2_cls_init(struct mvpp2 *priv)
2477 struct mvpp2_cls_lookup_entry le;
2478 struct mvpp2_cls_flow_entry fe;
2481 /* Enable classifier */
2482 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2484 /* Clear classifier flow table */
2485 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2486 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2488 mvpp2_cls_flow_write(priv, &fe);
2491 /* Clear classifier lookup table */
2493 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2496 mvpp2_cls_lookup_write(priv, &le);
2499 mvpp2_cls_lookup_write(priv, &le);
2503 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2505 struct mvpp2_cls_lookup_entry le;
2508 /* Set way for the port */
2509 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2510 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2511 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2513 /* Pick the entry to be accessed in lookup ID decoding table
2514 * according to the way and lkpid.
2516 le.lkpid = port->id;
2520 /* Set initial CPU queue for receiving packets */
2521 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2522 le.data |= port->first_rxq;
2524 /* Disable classification engines */
2525 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2527 /* Update lookup ID table entry */
2528 mvpp2_cls_lookup_write(port->priv, &le);
2531 /* Set CPU queue number for oversize packets */
2532 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2536 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2537 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2539 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2540 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2542 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2543 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2544 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2547 /* Buffer Manager configuration routines */
2550 static int mvpp2_bm_pool_create(struct udevice *dev,
2552 struct mvpp2_bm_pool *bm_pool, int size)
2556 /* Number of buffer pointers must be a multiple of 16, as per
2557 * hardware constraints
2559 if (!IS_ALIGNED(size, 16))
2562 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2563 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2564 if (!bm_pool->virt_addr)
2567 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2568 MVPP2_BM_POOL_PTR_ALIGN)) {
2569 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2570 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2574 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2575 lower_32_bits(bm_pool->dma_addr));
2576 if (priv->hw_version == MVPP22)
2577 mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
2578 (upper_32_bits(bm_pool->dma_addr) &
2579 MVPP22_BM_POOL_BASE_HIGH_MASK));
2580 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2582 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2583 val |= MVPP2_BM_START_MASK;
2584 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2586 bm_pool->type = MVPP2_BM_FREE;
2587 bm_pool->size = size;
2588 bm_pool->pkt_size = 0;
2589 bm_pool->buf_num = 0;
2594 /* Set pool buffer size */
2595 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2596 struct mvpp2_bm_pool *bm_pool,
2601 bm_pool->buf_size = buf_size;
2603 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2604 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2607 /* Free all buffers from the pool */
2608 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2609 struct mvpp2_bm_pool *bm_pool)
2613 for (i = 0; i < bm_pool->buf_num; i++) {
2614 /* Allocate buffer back from the buffer manager */
2615 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2618 bm_pool->buf_num = 0;
2622 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2624 struct mvpp2_bm_pool *bm_pool)
2628 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2629 if (bm_pool->buf_num) {
2630 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2634 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2635 val |= MVPP2_BM_STOP_MASK;
2636 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2641 static int mvpp2_bm_pools_init(struct udevice *dev,
2645 struct mvpp2_bm_pool *bm_pool;
2647 /* Create all pools with maximum size */
2648 size = MVPP2_BM_POOL_SIZE_MAX;
2649 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2650 bm_pool = &priv->bm_pools[i];
2652 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2654 goto err_unroll_pools;
2655 mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
2660 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2661 for (i = i - 1; i >= 0; i--)
2662 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2666 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2670 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2671 /* Mask BM all interrupts */
2672 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2673 /* Clear BM cause register */
2674 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2677 /* Allocate and initialize BM pools */
2678 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2679 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2680 if (!priv->bm_pools)
2683 err = mvpp2_bm_pools_init(dev, priv);
2689 /* Attach long pool to rxq */
2690 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2691 int lrxq, int long_pool)
2696 /* Get queue physical ID */
2697 prxq = port->rxqs[lrxq]->id;
2699 if (port->priv->hw_version == MVPP21)
2700 mask = MVPP21_RXQ_POOL_LONG_MASK;
2702 mask = MVPP22_RXQ_POOL_LONG_MASK;
2704 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2706 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2707 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2710 /* Set pool number in a BM cookie */
2711 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2715 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2716 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2721 /* Get pool number from a BM cookie */
2722 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2724 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2727 /* Release buffer to BM */
2728 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2729 dma_addr_t buf_dma_addr,
2730 unsigned long buf_phys_addr)
2732 if (port->priv->hw_version == MVPP22) {
2735 if (sizeof(dma_addr_t) == 8)
2736 val |= upper_32_bits(buf_dma_addr) &
2737 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2739 if (sizeof(phys_addr_t) == 8)
2740 val |= (upper_32_bits(buf_phys_addr)
2741 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2742 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2744 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2747 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2748 * returned in the "cookie" field of the RX
2749 * descriptor. Instead of storing the virtual address, we
2750 * store the physical address
2752 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2753 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2756 /* Refill BM pool */
2757 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2758 dma_addr_t dma_addr,
2759 phys_addr_t phys_addr)
2761 int pool = mvpp2_bm_cookie_pool_get(bm);
2763 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2766 /* Allocate buffers for the pool */
2767 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2768 struct mvpp2_bm_pool *bm_pool, int buf_num)
2773 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2774 netdev_err(port->dev,
2775 "cannot allocate %d buffers for pool %d\n",
2776 buf_num, bm_pool->id);
2780 for (i = 0; i < buf_num; i++) {
2781 mvpp2_bm_pool_put(port, bm_pool->id,
2782 (dma_addr_t)buffer_loc.rx_buffer[i],
2783 (unsigned long)buffer_loc.rx_buffer[i]);
2787 /* Update BM driver with number of buffers added to pool */
2788 bm_pool->buf_num += i;
2793 /* Notify the driver that BM pool is being used as specific type and return the
2794 * pool pointer on success
2796 static struct mvpp2_bm_pool *
2797 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2800 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2803 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2804 netdev_err(port->dev, "mixing pool types is forbidden\n");
2808 if (new_pool->type == MVPP2_BM_FREE)
2809 new_pool->type = type;
2811 /* Allocate buffers in case BM pool is used as long pool, but packet
2812 * size doesn't match MTU or BM pool hasn't being used yet
2814 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2815 (new_pool->pkt_size == 0)) {
2818 /* Set default buffer number or free all the buffers in case
2819 * the pool is not empty
2821 pkts_num = new_pool->buf_num;
2823 pkts_num = type == MVPP2_BM_SWF_LONG ?
2824 MVPP2_BM_LONG_BUF_NUM :
2825 MVPP2_BM_SHORT_BUF_NUM;
2827 mvpp2_bm_bufs_free(NULL,
2828 port->priv, new_pool);
2830 new_pool->pkt_size = pkt_size;
2832 /* Allocate buffers for this pool */
2833 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2834 if (num != pkts_num) {
2835 dev_err(dev, "pool %d: %d of %d allocated\n",
2836 new_pool->id, num, pkts_num);
2844 /* Initialize pools for swf */
2845 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2849 if (!port->pool_long) {
2851 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2854 if (!port->pool_long)
2857 port->pool_long->port_map |= (1 << port->id);
2859 for (rxq = 0; rxq < rxq_number; rxq++)
2860 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2866 /* Port configuration routines */
2868 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2872 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2874 switch (port->phy_interface) {
2875 case PHY_INTERFACE_MODE_SGMII:
2876 val |= MVPP2_GMAC_INBAND_AN_MASK;
2878 case PHY_INTERFACE_MODE_RGMII:
2879 case PHY_INTERFACE_MODE_RGMII_ID:
2880 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2882 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2885 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2888 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2892 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2893 val |= MVPP2_GMAC_FC_ADV_EN;
2894 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2897 static void mvpp2_port_enable(struct mvpp2_port *port)
2901 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2902 val |= MVPP2_GMAC_PORT_EN_MASK;
2903 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2904 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2907 static void mvpp2_port_disable(struct mvpp2_port *port)
2911 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2912 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2913 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2916 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2917 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2921 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2922 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2923 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2926 /* Configure loopback port */
2927 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2931 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2933 if (port->speed == 1000)
2934 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2936 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2938 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2939 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2941 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2943 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2946 static void mvpp2_port_reset(struct mvpp2_port *port)
2950 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2951 ~MVPP2_GMAC_PORT_RESET_MASK;
2952 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2954 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2955 MVPP2_GMAC_PORT_RESET_MASK)
2959 /* Change maximum receive size of the port */
2960 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2964 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2965 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2966 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2967 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2968 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2971 /* PPv2.2 GoP/GMAC config */
2973 /* Set the MAC to reset or exit from reset */
2974 static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2978 /* read - modify - write */
2979 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2981 val |= MVPP2_GMAC_PORT_RESET_MASK;
2983 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
2984 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2992 * Configure port to working with Gig PCS or don't.
2994 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
2998 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3000 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
3002 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3003 /* enable / disable PCS on this port */
3004 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3009 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3013 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3015 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3017 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3018 /* enable / disable PCS on this port */
3019 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3024 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3029 * Configure minimal level of the Tx FIFO before the lower part
3030 * starts to read a packet
3032 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3033 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3034 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3035 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3036 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3038 /* Disable bypass of sync module */
3039 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3040 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3041 /* configure DP clock select according to mode */
3042 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3043 /* configure QSGMII bypass according to mode */
3044 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3045 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3047 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3049 * Configure GIG MAC to 1000Base-X mode connected to a fiber
3052 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3053 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3055 /* configure AN 0x9268 */
3056 val = MVPP2_GMAC_EN_PCS_AN |
3057 MVPP2_GMAC_AN_BYPASS_EN |
3058 MVPP2_GMAC_CONFIG_MII_SPEED |
3059 MVPP2_GMAC_CONFIG_GMII_SPEED |
3060 MVPP2_GMAC_FC_ADV_EN |
3061 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3062 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3063 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3066 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3071 * Configure minimal level of the Tx FIFO before the lower part
3072 * starts to read a packet
3074 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3075 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3076 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3077 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3078 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3080 /* Disable bypass of sync module */
3081 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3082 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3083 /* configure DP clock select according to mode */
3084 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3085 /* configure QSGMII bypass according to mode */
3086 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3087 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3089 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3090 /* configure GIG MAC to SGMII mode */
3091 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3092 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3095 val = MVPP2_GMAC_EN_PCS_AN |
3096 MVPP2_GMAC_AN_BYPASS_EN |
3097 MVPP2_GMAC_AN_SPEED_EN |
3098 MVPP2_GMAC_EN_FC_AN |
3099 MVPP2_GMAC_AN_DUPLEX_EN |
3100 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3101 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3104 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3109 * Configure minimal level of the Tx FIFO before the lower part
3110 * starts to read a packet
3112 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3113 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3114 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3115 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3116 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3118 /* Disable bypass of sync module */
3119 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3120 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3121 /* configure DP clock select according to mode */
3122 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3123 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3124 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3125 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3127 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3128 /* configure GIG MAC to SGMII mode */
3129 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3130 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3132 /* configure AN 0xb8e8 */
3133 val = MVPP2_GMAC_AN_BYPASS_EN |
3134 MVPP2_GMAC_AN_SPEED_EN |
3135 MVPP2_GMAC_EN_FC_AN |
3136 MVPP2_GMAC_AN_DUPLEX_EN |
3137 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3138 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3141 /* Set the internal mux's to the required MAC in the GOP */
3142 static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3146 /* Set TX FIFO thresholds */
3147 switch (port->phy_interface) {
3148 case PHY_INTERFACE_MODE_SGMII:
3149 if (port->phy_speed == 2500)
3150 gop_gmac_sgmii2_5_cfg(port);
3152 gop_gmac_sgmii_cfg(port);
3155 case PHY_INTERFACE_MODE_RGMII:
3156 case PHY_INTERFACE_MODE_RGMII_ID:
3157 gop_gmac_rgmii_cfg(port);
3164 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3165 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3166 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3167 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3168 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3170 /* PeriodicXonEn disable */
3171 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3172 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3173 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3178 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3182 /* relevant only for MAC0 (XLG0 and GMAC0) */
3183 if (port->gop_id > 0)
3186 /* configure 1Gig MAC mode */
3187 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3188 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3189 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3190 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3193 static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3197 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3199 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3201 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3202 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3207 /* Set the internal mux's to the required PCS in the PI */
3208 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
3213 switch (num_of_lanes) {
3227 /* configure XG MAC mode */
3228 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3229 val &= ~MVPP22_XPCS_PCSMODE_MASK;
3230 val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
3231 val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
3232 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3237 static int gop_mpcs_mode(struct mvpp2_port *port)
3241 /* configure PCS40G COMMON CONTROL */
3242 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3243 val &= ~FORWARD_ERROR_CORRECTION_MASK;
3244 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3246 /* configure PCS CLOCK RESET */
3247 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
3248 val &= ~CLK_DIVISION_RATIO_MASK;
3249 val |= 1 << CLK_DIVISION_RATIO_OFFS;
3250 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3252 val &= ~CLK_DIV_PHASE_SET_MASK;
3253 val |= MAC_CLK_RESET_MASK;
3254 val |= RX_SD_CLK_RESET_MASK;
3255 val |= TX_SD_CLK_RESET_MASK;
3256 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3261 /* Set the internal mux's to the required MAC in the GOP */
3262 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3266 /* configure 10G MAC mode */
3267 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3268 val |= MVPP22_XLG_RX_FC_EN;
3269 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3271 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3272 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3273 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3274 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3276 /* read - modify - write */
3277 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3278 val &= ~MVPP22_XLG_MODE_DMA_1G;
3279 val |= MVPP22_XLG_FORWARD_PFC_EN;
3280 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3281 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3282 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3284 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3285 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3286 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3287 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3288 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3290 /* unmask link change interrupt */
3291 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3292 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3293 val |= 1; /* unmask summary bit */
3294 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3299 /* Set PCS to reset or exit from reset */
3300 static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
3304 /* read - modify - write */
3305 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3307 val &= ~MVPP22_XPCS_PCSRESET;
3309 val |= MVPP22_XPCS_PCSRESET;
3310 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3315 /* Set the MAC to reset or exit from reset */
3316 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3320 /* read - modify - write */
3321 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3323 val &= ~MVPP22_XLG_MAC_RESETN;
3325 val |= MVPP22_XLG_MAC_RESETN;
3326 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3334 * Init physical port. Configures the port mode and all it's elements
3336 * Does not verify that the selected mode/port number is valid at the
3339 static int gop_port_init(struct mvpp2_port *port)
3341 int mac_num = port->gop_id;
3342 int num_of_act_lanes;
3344 if (mac_num >= MVPP22_GOP_MAC_NUM) {
3345 netdev_err(NULL, "%s: illegal port number %d", __func__,
3350 switch (port->phy_interface) {
3351 case PHY_INTERFACE_MODE_RGMII:
3352 case PHY_INTERFACE_MODE_RGMII_ID:
3353 gop_gmac_reset(port, 1);
3356 gop_gpcs_mode_cfg(port, 0);
3357 gop_bypass_clk_cfg(port, 1);
3360 gop_gmac_mode_cfg(port);
3362 gop_gpcs_reset(port, 0);
3365 gop_gmac_reset(port, 0);
3368 case PHY_INTERFACE_MODE_SGMII:
3370 gop_gpcs_mode_cfg(port, 1);
3373 gop_gmac_mode_cfg(port);
3374 /* select proper Mac mode */
3375 gop_xlg_2_gig_mac_cfg(port);
3378 gop_gpcs_reset(port, 0);
3380 gop_gmac_reset(port, 0);
3383 case PHY_INTERFACE_MODE_SFI:
3384 num_of_act_lanes = 2;
3387 gop_xpcs_mode(port, num_of_act_lanes);
3388 gop_mpcs_mode(port);
3390 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3393 gop_xpcs_reset(port, 0);
3396 gop_xlg_mac_reset(port, 0);
3400 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
3401 __func__, port->phy_interface);
3408 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3412 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3414 /* Enable port and MIB counters update */
3415 val |= MVPP22_XLG_PORT_EN;
3416 val &= ~MVPP22_XLG_MIBCNT_DIS;
3419 val &= ~MVPP22_XLG_PORT_EN;
3421 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3424 static void gop_port_enable(struct mvpp2_port *port, int enable)
3426 switch (port->phy_interface) {
3427 case PHY_INTERFACE_MODE_RGMII:
3428 case PHY_INTERFACE_MODE_RGMII_ID:
3429 case PHY_INTERFACE_MODE_SGMII:
3431 mvpp2_port_enable(port);
3433 mvpp2_port_disable(port);
3436 case PHY_INTERFACE_MODE_SFI:
3437 gop_xlg_mac_port_enable(port, enable);
3441 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
3442 port->phy_interface);
3447 /* RFU1 functions */
3448 static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3450 return readl(priv->rfu1_base + offset);
3453 static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3455 writel(data, priv->rfu1_base + offset);
3458 static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3463 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3464 val |= MV_NETC_GE_MAC2_SGMII;
3468 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3469 val |= MV_NETC_GE_MAC3_SGMII;
3470 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3471 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3472 val |= MV_NETC_GE_MAC3_RGMII;
3478 static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3482 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3483 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3485 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3486 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3490 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3493 static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3497 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3498 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3500 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3501 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3505 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3508 static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3512 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3513 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3515 val <<= NETC_GOP_SOFT_RESET_OFFS;
3516 val &= NETC_GOP_SOFT_RESET_MASK;
3520 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3523 static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3527 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3528 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3530 val <<= NETC_CLK_DIV_PHASE_OFFS;
3531 val &= NETC_CLK_DIV_PHASE_MASK;
3535 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3538 static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3542 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3543 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3545 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3546 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3550 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3553 static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3556 u32 reg, mask, offset;
3559 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3560 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3562 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3563 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3565 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3573 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3576 static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3580 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3581 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3583 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3584 val &= NETC_BUS_WIDTH_SELECT_MASK;
3588 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3591 static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3595 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3596 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3598 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3599 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3603 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3606 static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3607 enum mv_netc_phase phase)
3610 case MV_NETC_FIRST_PHASE:
3611 /* Set Bus Width to HB mode = 1 */
3612 gop_netc_bus_width_select(priv, 1);
3613 /* Select RGMII mode */
3614 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3617 case MV_NETC_SECOND_PHASE:
3618 /* De-assert the relevant port HB reset */
3619 gop_netc_port_rf_reset(priv, gop_id, 1);
3624 static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3625 enum mv_netc_phase phase)
3628 case MV_NETC_FIRST_PHASE:
3629 /* Set Bus Width to HB mode = 1 */
3630 gop_netc_bus_width_select(priv, 1);
3631 /* Select SGMII mode */
3633 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3637 /* Configure the sample stages */
3638 gop_netc_sample_stages_timing(priv, 0);
3639 /* Configure the ComPhy Selector */
3640 /* gop_netc_com_phy_selector_config(netComplex); */
3643 case MV_NETC_SECOND_PHASE:
3644 /* De-assert the relevant port HB reset */
3645 gop_netc_port_rf_reset(priv, gop_id, 1);
3650 static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3652 u32 c = priv->netc_config;
3654 if (c & MV_NETC_GE_MAC2_SGMII)
3655 gop_netc_mac_to_sgmii(priv, 2, phase);
3657 gop_netc_mac_to_xgmii(priv, 2, phase);
3659 if (c & MV_NETC_GE_MAC3_SGMII) {
3660 gop_netc_mac_to_sgmii(priv, 3, phase);
3662 gop_netc_mac_to_xgmii(priv, 3, phase);
3663 if (c & MV_NETC_GE_MAC3_RGMII)
3664 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3666 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3669 /* Activate gop ports 0, 2, 3 */
3670 gop_netc_active_port(priv, 0, 1);
3671 gop_netc_active_port(priv, 2, 1);
3672 gop_netc_active_port(priv, 3, 1);
3674 if (phase == MV_NETC_SECOND_PHASE) {
3675 /* Enable the GOP internal clock logic */
3676 gop_netc_gop_clock_logic_set(priv, 1);
3677 /* De-assert GOP unit reset */
3678 gop_netc_gop_reset(priv, 1);
3684 /* Set defaults to the MVPP2 port */
3685 static void mvpp2_defaults_set(struct mvpp2_port *port)
3687 int tx_port_num, val, queue, ptxq, lrxq;
3689 if (port->priv->hw_version == MVPP21) {
3690 /* Configure port to loopback if needed */
3691 if (port->flags & MVPP2_F_LOOPBACK)
3692 mvpp2_port_loopback_set(port);
3694 /* Update TX FIFO MIN Threshold */
3695 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3696 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3697 /* Min. TX threshold must be less than minimal packet length */
3698 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3699 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3702 /* Disable Legacy WRR, Disable EJP, Release from reset */
3703 tx_port_num = mvpp2_egress_port(port);
3704 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3706 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3708 /* Close bandwidth for all queues */
3709 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3710 ptxq = mvpp2_txq_phys(port->id, queue);
3711 mvpp2_write(port->priv,
3712 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3715 /* Set refill period to 1 usec, refill tokens
3716 * and bucket size to maximum
3718 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3719 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3720 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3721 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3722 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3723 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3724 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3725 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3727 /* Set MaximumLowLatencyPacketSize value to 256 */
3728 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3729 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3730 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3732 /* Enable Rx cache snoop */
3733 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3734 queue = port->rxqs[lrxq]->id;
3735 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3736 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3737 MVPP2_SNOOP_BUF_HDR_MASK;
3738 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3742 /* Enable/disable receiving packets */
3743 static void mvpp2_ingress_enable(struct mvpp2_port *port)
3748 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3749 queue = port->rxqs[lrxq]->id;
3750 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3751 val &= ~MVPP2_RXQ_DISABLE_MASK;
3752 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3756 static void mvpp2_ingress_disable(struct mvpp2_port *port)
3761 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3762 queue = port->rxqs[lrxq]->id;
3763 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3764 val |= MVPP2_RXQ_DISABLE_MASK;
3765 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3769 /* Enable transmit via physical egress queue
3770 * - HW starts take descriptors from DRAM
3772 static void mvpp2_egress_enable(struct mvpp2_port *port)
3776 int tx_port_num = mvpp2_egress_port(port);
3778 /* Enable all initialized TXs. */
3780 for (queue = 0; queue < txq_number; queue++) {
3781 struct mvpp2_tx_queue *txq = port->txqs[queue];
3783 if (txq->descs != NULL)
3784 qmap |= (1 << queue);
3787 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3788 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3791 /* Disable transmit via physical egress queue
3792 * - HW doesn't take descriptors from DRAM
3794 static void mvpp2_egress_disable(struct mvpp2_port *port)
3798 int tx_port_num = mvpp2_egress_port(port);
3800 /* Issue stop command for active channels only */
3801 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3802 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3803 MVPP2_TXP_SCHED_ENQ_MASK;
3805 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3806 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3808 /* Wait for all Tx activity to terminate. */
3811 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
3812 netdev_warn(port->dev,
3813 "Tx stop timed out, status=0x%08x\n",
3820 /* Check port TX Command register that all
3821 * Tx queues are stopped
3823 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3824 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3827 /* Rx descriptors helper methods */
3829 /* Get number of Rx descriptors occupied by received packets */
3831 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3833 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3835 return val & MVPP2_RXQ_OCCUPIED_MASK;
3838 /* Update Rx queue status with the number of occupied and available
3839 * Rx descriptor slots.
3842 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3843 int used_count, int free_count)
3845 /* Decrement the number of used descriptors and increment count
3846 * increment the number of free descriptors.
3848 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3850 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3853 /* Get pointer to next RX descriptor to be processed by SW */
3854 static inline struct mvpp2_rx_desc *
3855 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3857 int rx_desc = rxq->next_desc_to_proc;
3859 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3860 prefetch(rxq->descs + rxq->next_desc_to_proc);
3861 return rxq->descs + rx_desc;
3864 /* Set rx queue offset */
3865 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3866 int prxq, int offset)
3870 /* Convert offset from bytes to units of 32 bytes */
3871 offset = offset >> 5;
3873 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3874 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3877 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3878 MVPP2_RXQ_PACKET_OFFSET_MASK);
3880 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3883 /* Obtain BM cookie information from descriptor */
3884 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3885 struct mvpp2_rx_desc *rx_desc)
3887 int cpu = smp_processor_id();
3890 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3891 MVPP2_RXD_BM_POOL_ID_MASK) >>
3892 MVPP2_RXD_BM_POOL_ID_OFFS;
3894 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3895 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3898 /* Tx descriptors helper methods */
3900 /* Get number of Tx descriptors waiting to be transmitted by HW */
3901 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3902 struct mvpp2_tx_queue *txq)
3906 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3907 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3909 return val & MVPP2_TXQ_PENDING_MASK;
3912 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3913 static struct mvpp2_tx_desc *
3914 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3916 int tx_desc = txq->next_desc_to_proc;
3918 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3919 return txq->descs + tx_desc;
3922 /* Update HW with number of aggregated Tx descriptors to be sent */
3923 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3925 /* aggregated access - relevant TXQ number is written in TX desc */
3926 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3929 /* Get number of sent descriptors and decrement counter.
3930 * The number of sent descriptors is returned.
3933 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3934 struct mvpp2_tx_queue *txq)
3938 /* Reading status reg resets transmitted descriptor counter */
3939 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3941 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3942 MVPP2_TRANSMITTED_COUNT_OFFSET;
3945 static void mvpp2_txq_sent_counter_clear(void *arg)
3947 struct mvpp2_port *port = arg;
3950 for (queue = 0; queue < txq_number; queue++) {
3951 int id = port->txqs[queue]->id;
3953 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3957 /* Set max sizes for Tx queues */
3958 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3961 int txq, tx_port_num;
3963 mtu = port->pkt_size * 8;
3964 if (mtu > MVPP2_TXP_MTU_MAX)
3965 mtu = MVPP2_TXP_MTU_MAX;
3967 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3970 /* Indirect access to registers */
3971 tx_port_num = mvpp2_egress_port(port);
3972 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3975 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3976 val &= ~MVPP2_TXP_MTU_MAX;
3978 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3980 /* TXP token size and all TXQs token size must be larger that MTU */
3981 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3982 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3985 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3987 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3990 for (txq = 0; txq < txq_number; txq++) {
3991 val = mvpp2_read(port->priv,
3992 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3993 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3997 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3999 mvpp2_write(port->priv,
4000 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4006 /* Free Tx queue skbuffs */
4007 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4008 struct mvpp2_tx_queue *txq,
4009 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4013 for (i = 0; i < num; i++)
4014 mvpp2_txq_inc_get(txq_pcpu);
4017 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4020 int queue = fls(cause) - 1;
4022 return port->rxqs[queue];
4025 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4028 int queue = fls(cause) - 1;
4030 return port->txqs[queue];
4033 /* Rx/Tx queue initialization/cleanup methods */
4035 /* Allocate and initialize descriptors for aggr TXQ */
4036 static int mvpp2_aggr_txq_init(struct udevice *dev,
4037 struct mvpp2_tx_queue *aggr_txq,
4038 int desc_num, int cpu,
4043 /* Allocate memory for TX descriptors */
4044 aggr_txq->descs = buffer_loc.aggr_tx_descs;
4045 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
4046 if (!aggr_txq->descs)
4049 /* Make sure descriptor address is cache line size aligned */
4050 BUG_ON(aggr_txq->descs !=
4051 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4053 aggr_txq->last_desc = aggr_txq->size - 1;
4055 /* Aggr TXQ no reset WA */
4056 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4057 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4059 /* Set Tx descriptors queue starting address indirect
4062 if (priv->hw_version == MVPP21)
4063 txq_dma = aggr_txq->descs_dma;
4065 txq_dma = aggr_txq->descs_dma >>
4066 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4068 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
4069 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4074 /* Create a specified Rx queue */
4075 static int mvpp2_rxq_init(struct mvpp2_port *port,
4076 struct mvpp2_rx_queue *rxq)
4081 rxq->size = port->rx_ring_size;
4083 /* Allocate memory for RX descriptors */
4084 rxq->descs = buffer_loc.rx_descs;
4085 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
4089 BUG_ON(rxq->descs !=
4090 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4092 rxq->last_desc = rxq->size - 1;
4094 /* Zero occupied and non-occupied counters - direct access */
4095 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4097 /* Set Rx descriptors queue starting address - indirect access */
4098 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4099 if (port->priv->hw_version == MVPP21)
4100 rxq_dma = rxq->descs_dma;
4102 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4103 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
4104 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4105 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4108 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4110 /* Add number of descriptors ready for receiving packets */
4111 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4116 /* Push packets received by the RXQ to BM pool */
4117 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4118 struct mvpp2_rx_queue *rxq)
4122 rx_received = mvpp2_rxq_received(port, rxq->id);
4126 for (i = 0; i < rx_received; i++) {
4127 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4128 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
4130 mvpp2_pool_refill(port, bm,
4131 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4132 mvpp2_rxdesc_cookie_get(port, rx_desc));
4134 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4137 /* Cleanup Rx queue */
4138 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4139 struct mvpp2_rx_queue *rxq)
4141 mvpp2_rxq_drop_pkts(port, rxq);
4145 rxq->next_desc_to_proc = 0;
4148 /* Clear Rx descriptors queue starting address and size;
4149 * free descriptor number
4151 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4152 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4153 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4154 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4157 /* Create and initialize a Tx queue */
4158 static int mvpp2_txq_init(struct mvpp2_port *port,
4159 struct mvpp2_tx_queue *txq)
4162 int cpu, desc, desc_per_txq, tx_port_num;
4163 struct mvpp2_txq_pcpu *txq_pcpu;
4165 txq->size = port->tx_ring_size;
4167 /* Allocate memory for Tx descriptors */
4168 txq->descs = buffer_loc.tx_descs;
4169 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
4173 /* Make sure descriptor address is cache line size aligned */
4174 BUG_ON(txq->descs !=
4175 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4177 txq->last_desc = txq->size - 1;
4179 /* Set Tx descriptors queue starting address - indirect access */
4180 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4181 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
4182 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4183 MVPP2_TXQ_DESC_SIZE_MASK);
4184 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4185 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4186 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4187 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4188 val &= ~MVPP2_TXQ_PENDING_MASK;
4189 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4191 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4192 * for each existing TXQ.
4193 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4194 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4197 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4198 (txq->log_id * desc_per_txq);
4200 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4201 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4202 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
4204 /* WRR / EJP configuration - indirect access */
4205 tx_port_num = mvpp2_egress_port(port);
4206 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4208 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4209 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4210 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4211 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4212 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4214 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4215 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4218 for_each_present_cpu(cpu) {
4219 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4220 txq_pcpu->size = txq->size;
4226 /* Free allocated TXQ resources */
4227 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4228 struct mvpp2_tx_queue *txq)
4232 txq->next_desc_to_proc = 0;
4235 /* Set minimum bandwidth for disabled TXQs */
4236 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4238 /* Set Tx descriptors queue starting address and size */
4239 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4240 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4241 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4244 /* Cleanup Tx ports */
4245 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4247 struct mvpp2_txq_pcpu *txq_pcpu;
4248 int delay, pending, cpu;
4251 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4252 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4253 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4254 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4256 /* The napi queue has been stopped so wait for all packets
4257 * to be transmitted.
4261 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4262 netdev_warn(port->dev,
4263 "port %d: cleaning queue %d timed out\n",
4264 port->id, txq->log_id);
4270 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4273 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4274 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4276 for_each_present_cpu(cpu) {
4277 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4279 /* Release all packets */
4280 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4283 txq_pcpu->count = 0;
4284 txq_pcpu->txq_put_index = 0;
4285 txq_pcpu->txq_get_index = 0;
4289 /* Cleanup all Tx queues */
4290 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4292 struct mvpp2_tx_queue *txq;
4296 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4298 /* Reset Tx ports and delete Tx queues */
4299 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4300 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4302 for (queue = 0; queue < txq_number; queue++) {
4303 txq = port->txqs[queue];
4304 mvpp2_txq_clean(port, txq);
4305 mvpp2_txq_deinit(port, txq);
4308 mvpp2_txq_sent_counter_clear(port);
4310 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4311 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4314 /* Cleanup all Rx queues */
4315 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4319 for (queue = 0; queue < rxq_number; queue++)
4320 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4323 /* Init all Rx queues for port */
4324 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4328 for (queue = 0; queue < rxq_number; queue++) {
4329 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4336 mvpp2_cleanup_rxqs(port);
4340 /* Init all tx queues for port */
4341 static int mvpp2_setup_txqs(struct mvpp2_port *port)
4343 struct mvpp2_tx_queue *txq;
4346 for (queue = 0; queue < txq_number; queue++) {
4347 txq = port->txqs[queue];
4348 err = mvpp2_txq_init(port, txq);
4353 mvpp2_txq_sent_counter_clear(port);
4357 mvpp2_cleanup_txqs(port);
4362 static void mvpp2_link_event(struct mvpp2_port *port)
4364 struct phy_device *phydev = port->phy_dev;
4365 int status_change = 0;
4369 if ((port->speed != phydev->speed) ||
4370 (port->duplex != phydev->duplex)) {
4373 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4374 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4375 MVPP2_GMAC_CONFIG_GMII_SPEED |
4376 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4377 MVPP2_GMAC_AN_SPEED_EN |
4378 MVPP2_GMAC_AN_DUPLEX_EN);
4381 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4383 if (phydev->speed == SPEED_1000)
4384 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4385 else if (phydev->speed == SPEED_100)
4386 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4388 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4390 port->duplex = phydev->duplex;
4391 port->speed = phydev->speed;
4395 if (phydev->link != port->link) {
4396 if (!phydev->link) {
4401 port->link = phydev->link;
4405 if (status_change) {
4407 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4408 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4409 MVPP2_GMAC_FORCE_LINK_DOWN);
4410 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4411 mvpp2_egress_enable(port);
4412 mvpp2_ingress_enable(port);
4414 mvpp2_ingress_disable(port);
4415 mvpp2_egress_disable(port);
4420 /* Main RX/TX processing routines */
4422 /* Display more error info */
4423 static void mvpp2_rx_error(struct mvpp2_port *port,
4424 struct mvpp2_rx_desc *rx_desc)
4426 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4427 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
4429 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4430 case MVPP2_RXD_ERR_CRC:
4431 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
4434 case MVPP2_RXD_ERR_OVERRUN:
4435 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
4438 case MVPP2_RXD_ERR_RESOURCE:
4439 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
4445 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4446 static int mvpp2_rx_refill(struct mvpp2_port *port,
4447 struct mvpp2_bm_pool *bm_pool,
4448 u32 bm, dma_addr_t dma_addr)
4450 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
4454 /* Set hw internals when starting port */
4455 static void mvpp2_start_dev(struct mvpp2_port *port)
4457 switch (port->phy_interface) {
4458 case PHY_INTERFACE_MODE_RGMII:
4459 case PHY_INTERFACE_MODE_RGMII_ID:
4460 case PHY_INTERFACE_MODE_SGMII:
4461 mvpp2_gmac_max_rx_size_set(port);
4466 mvpp2_txp_max_tx_size_set(port);
4468 if (port->priv->hw_version == MVPP21)
4469 mvpp2_port_enable(port);
4471 gop_port_enable(port, 1);
4474 /* Set hw internals when stopping port */
4475 static void mvpp2_stop_dev(struct mvpp2_port *port)
4477 /* Stop new packets from arriving to RXQs */
4478 mvpp2_ingress_disable(port);
4480 mvpp2_egress_disable(port);
4482 if (port->priv->hw_version == MVPP21)
4483 mvpp2_port_disable(port);
4485 gop_port_enable(port, 0);
4488 static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
4490 struct phy_device *phy_dev;
4492 if (!port->init || port->link == 0) {
4493 phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
4494 dev, port->phy_interface);
4497 * If the phy doesn't match with any existing u-boot drivers the
4498 * phy framework will connect it to generic one which
4499 * uid == 0xffffffff. In this case act as if the phy wouldn't be
4500 * declared in dts. Otherwise in case of 3310 (for which the
4501 * driver doesn't exist) the link will not be correctly
4502 * detected. Removing phy entry from dts in case of 3310 is not
4503 * an option because it is required for the phy_fw_down
4507 phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
4508 netdev_warn(port->dev,
4509 "Marking phy as invalid, link will not be checked\n");
4510 /* set phy_addr to invalid value */
4511 port->phyaddr = PHY_MAX_ADDR;
4512 mvpp2_egress_enable(port);
4513 mvpp2_ingress_enable(port);
4518 port->phy_dev = phy_dev;
4520 netdev_err(port->dev, "cannot connect to phy\n");
4523 phy_dev->supported &= PHY_GBIT_FEATURES;
4524 phy_dev->advertising = phy_dev->supported;
4526 port->phy_dev = phy_dev;
4531 phy_config(phy_dev);
4532 phy_startup(phy_dev);
4534 printf("%s: No link\n", phy_dev->dev->name);
4538 mvpp2_egress_enable(port);
4539 mvpp2_ingress_enable(port);
4543 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4545 unsigned char mac_bcast[ETH_ALEN] = {
4546 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4549 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4551 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4554 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4555 port->dev_addr, true);
4557 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
4560 err = mvpp2_prs_def_flow(port);
4562 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4566 /* Allocate the Rx/Tx queues */
4567 err = mvpp2_setup_rxqs(port);
4569 netdev_err(port->dev, "cannot allocate Rx queues\n");
4573 err = mvpp2_setup_txqs(port);
4575 netdev_err(port->dev, "cannot allocate Tx queues\n");
4579 if (port->phyaddr < PHY_MAX_ADDR) {
4580 mvpp2_phy_connect(dev, port);
4581 mvpp2_link_event(port);
4583 mvpp2_egress_enable(port);
4584 mvpp2_ingress_enable(port);
4587 mvpp2_start_dev(port);
4592 /* No Device ops here in U-Boot */
4594 /* Driver initialization */
4596 static void mvpp2_port_power_up(struct mvpp2_port *port)
4598 struct mvpp2 *priv = port->priv;
4600 /* On PPv2.2 the GoP / interface configuration has already been done */
4601 if (priv->hw_version == MVPP21)
4602 mvpp2_port_mii_set(port);
4603 mvpp2_port_periodic_xon_disable(port);
4604 if (priv->hw_version == MVPP21)
4605 mvpp2_port_fc_adv_enable(port);
4606 mvpp2_port_reset(port);
4609 /* Initialize port HW */
4610 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4612 struct mvpp2 *priv = port->priv;
4613 struct mvpp2_txq_pcpu *txq_pcpu;
4614 int queue, cpu, err;
4616 if (port->first_rxq + rxq_number >
4617 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4621 mvpp2_egress_disable(port);
4622 if (priv->hw_version == MVPP21)
4623 mvpp2_port_disable(port);
4625 gop_port_enable(port, 0);
4627 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4632 /* Associate physical Tx queues to this port and initialize.
4633 * The mapping is predefined.
4635 for (queue = 0; queue < txq_number; queue++) {
4636 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4637 struct mvpp2_tx_queue *txq;
4639 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4643 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4648 txq->id = queue_phy_id;
4649 txq->log_id = queue;
4650 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4651 for_each_present_cpu(cpu) {
4652 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4653 txq_pcpu->cpu = cpu;
4656 port->txqs[queue] = txq;
4659 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4664 /* Allocate and initialize Rx queue for this port */
4665 for (queue = 0; queue < rxq_number; queue++) {
4666 struct mvpp2_rx_queue *rxq;
4668 /* Map physical Rx queue to port's logical Rx queue */
4669 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4672 /* Map this Rx queue to a physical queue */
4673 rxq->id = port->first_rxq + queue;
4674 rxq->port = port->id;
4675 rxq->logic_rxq = queue;
4677 port->rxqs[queue] = rxq;
4681 /* Create Rx descriptor rings */
4682 for (queue = 0; queue < rxq_number; queue++) {
4683 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4685 rxq->size = port->rx_ring_size;
4686 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4687 rxq->time_coal = MVPP2_RX_COAL_USEC;
4690 mvpp2_ingress_disable(port);
4692 /* Port default configuration */
4693 mvpp2_defaults_set(port);
4695 /* Port's classifier configuration */
4696 mvpp2_cls_oversize_rxq_set(port);
4697 mvpp2_cls_port_config(port);
4699 /* Provide an initial Rx packet size */
4700 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4702 /* Initialize pools for swf */
4703 err = mvpp2_swf_bm_pool_init(port);
4710 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
4712 int port_node = dev_of_offset(dev);
4713 const char *phy_mode_str;
4720 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
4724 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
4726 dev_err(&pdev->dev, "could not find phy address\n");
4729 parent = fdt_parent_offset(gd->fdt_blob, phy_node);
4730 ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
4735 /* phy_addr is set to invalid value */
4736 phyaddr = PHY_MAX_ADDR;
4739 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
4741 phy_mode = phy_get_interface_by_name(phy_mode_str);
4742 if (phy_mode == -1) {
4743 dev_err(&pdev->dev, "incorrect phy mode\n");
4747 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4749 dev_err(&pdev->dev, "missing port-id value\n");
4753 #if CONFIG_IS_ENABLED(DM_GPIO)
4754 gpio_request_by_name(dev, "phy-reset-gpios", 0,
4755 &port->phy_reset_gpio, GPIOD_IS_OUT);
4756 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
4757 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
4762 * Not sure if this DT property "phy-speed" will get accepted, so
4763 * this might change later
4765 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
4766 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
4770 if (port->priv->hw_version == MVPP21)
4771 port->first_rxq = port->id * rxq_number;
4773 port->first_rxq = port->id * port->priv->max_port_rxqs;
4774 port->phy_interface = phy_mode;
4775 port->phyaddr = phyaddr;
4780 #if CONFIG_IS_ENABLED(DM_GPIO)
4781 /* Port GPIO initialization */
4782 static void mvpp2_gpio_init(struct mvpp2_port *port)
4784 if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
4785 dm_gpio_set_value(&port->phy_reset_gpio, 1);
4787 dm_gpio_set_value(&port->phy_reset_gpio, 0);
4790 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
4791 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
4795 /* Ports initialization */
4796 static int mvpp2_port_probe(struct udevice *dev,
4797 struct mvpp2_port *port,
4803 port->tx_ring_size = MVPP2_MAX_TXD;
4804 port->rx_ring_size = MVPP2_MAX_RXD;
4806 err = mvpp2_port_init(dev, port);
4808 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
4811 mvpp2_port_power_up(port);
4813 #if CONFIG_IS_ENABLED(DM_GPIO)
4814 mvpp2_gpio_init(port);
4817 priv->port_list[port->id] = port;
4822 /* Initialize decoding windows */
4823 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4829 for (i = 0; i < 6; i++) {
4830 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4831 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4834 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4839 for (i = 0; i < dram->num_cs; i++) {
4840 const struct mbus_dram_window *cs = dram->cs + i;
4842 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4843 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4844 dram->mbus_dram_target_id);
4846 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4847 (cs->size - 1) & 0xffff0000);
4849 win_enable |= (1 << i);
4852 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4855 /* Initialize Rx FIFO's */
4856 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4860 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4861 if (priv->hw_version == MVPP22) {
4864 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4865 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4867 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4868 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4869 } else if (port == 1) {
4871 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4872 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4874 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4875 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4878 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4879 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4881 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4882 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4885 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4886 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4887 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4888 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4892 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4893 MVPP2_RX_FIFO_PORT_MIN_PKT);
4894 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4897 /* Initialize Tx FIFO's */
4898 static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4902 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4903 /* Port 0 supports 10KB TX FIFO */
4905 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4906 MVPP22_TX_FIFO_SIZE_MASK;
4908 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4909 MVPP22_TX_FIFO_SIZE_MASK;
4911 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4915 static void mvpp2_axi_init(struct mvpp2 *priv)
4917 u32 val, rdval, wrval;
4919 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4921 /* AXI Bridge Configuration */
4923 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4924 << MVPP22_AXI_ATTR_CACHE_OFFS;
4925 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4926 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4928 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4929 << MVPP22_AXI_ATTR_CACHE_OFFS;
4930 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4931 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4934 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4935 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4938 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4939 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4940 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4941 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4944 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4945 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4947 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4948 << MVPP22_AXI_CODE_CACHE_OFFS;
4949 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4950 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4951 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4952 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4954 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4955 << MVPP22_AXI_CODE_CACHE_OFFS;
4956 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4957 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4959 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4961 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4962 << MVPP22_AXI_CODE_CACHE_OFFS;
4963 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4964 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4966 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
4969 /* Initialize network controller common part HW */
4970 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
4972 const struct mbus_dram_target_info *dram_target_info;
4976 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4977 if ((rxq_number > priv->max_port_rxqs) ||
4978 (txq_number > MVPP2_MAX_TXQ)) {
4979 dev_err(&pdev->dev, "invalid queue size parameter\n");
4983 if (priv->hw_version == MVPP22)
4984 mvpp2_axi_init(priv);
4986 /* MBUS windows configuration */
4987 dram_target_info = mvebu_mbus_dram_info();
4988 if (dram_target_info)
4989 mvpp2_conf_mbus_windows(dram_target_info, priv);
4992 if (priv->hw_version == MVPP21) {
4993 /* Disable HW PHY polling */
4994 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4995 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4996 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4998 /* Enable HW PHY polling */
4999 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5000 val |= MVPP22_SMI_POLLING_EN;
5001 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5004 /* Allocate and initialize aggregated TXQs */
5005 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
5006 sizeof(struct mvpp2_tx_queue),
5008 if (!priv->aggr_txqs)
5011 for_each_present_cpu(i) {
5012 priv->aggr_txqs[i].id = i;
5013 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5014 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5015 MVPP2_AGGR_TXQ_SIZE, i, priv);
5021 mvpp2_rx_fifo_init(priv);
5024 if (priv->hw_version == MVPP22)
5025 mvpp2_tx_fifo_init(priv);
5027 if (priv->hw_version == MVPP21)
5028 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5029 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5031 /* Allow cache snoop when transmiting packets */
5032 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5034 /* Buffer Manager initialization */
5035 err = mvpp2_bm_init(dev, priv);
5039 /* Parser default initialization */
5040 err = mvpp2_prs_default_init(dev, priv);
5044 /* Classifier default initialization */
5045 mvpp2_cls_init(priv);
5050 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5052 struct mvpp2_port *port = dev_get_priv(dev);
5053 struct mvpp2_rx_desc *rx_desc;
5054 struct mvpp2_bm_pool *bm_pool;
5055 dma_addr_t dma_addr;
5057 int pool, rx_bytes, err;
5059 struct mvpp2_rx_queue *rxq;
5062 if (port->phyaddr < PHY_MAX_ADDR)
5063 if (!port->phy_dev->link)
5066 /* Process RX packets */
5067 rxq = port->rxqs[0];
5069 /* Get number of received packets and clamp the to-do */
5070 rx_received = mvpp2_rxq_received(port, rxq->id);
5072 /* Return if no packets are received */
5076 rx_desc = mvpp2_rxq_next_desc_get(rxq);
5077 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5078 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5079 rx_bytes -= MVPP2_MH_SIZE;
5080 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
5082 bm = mvpp2_bm_cookie_build(port, rx_desc);
5083 pool = mvpp2_bm_cookie_pool_get(bm);
5084 bm_pool = &port->priv->bm_pools[pool];
5086 /* In case of an error, release the requested buffer pointer
5087 * to the Buffer Manager. This request process is controlled
5088 * by the hardware, and the information about the buffer is
5089 * comprised by the RX descriptor.
5091 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5092 mvpp2_rx_error(port, rx_desc);
5093 /* Return the buffer to the pool */
5094 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
5098 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
5100 netdev_err(port->dev, "failed to refill BM pools\n");
5104 /* Update Rx queue management counters */
5106 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5108 /* give packet to stack - skip on first n bytes */
5109 data = (u8 *)dma_addr + 2 + 32;
5115 * No cache invalidation needed here, since the rx_buffer's are
5116 * located in a uncached memory region
5123 static int mvpp2_send(struct udevice *dev, void *packet, int length)
5125 struct mvpp2_port *port = dev_get_priv(dev);
5126 struct mvpp2_tx_queue *txq, *aggr_txq;
5127 struct mvpp2_tx_desc *tx_desc;
5131 if (port->phyaddr < PHY_MAX_ADDR)
5132 if (!port->phy_dev->link)
5135 txq = port->txqs[0];
5136 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5138 /* Get a descriptor for the first part of the packet */
5139 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5140 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5141 mvpp2_txdesc_size_set(port, tx_desc, length);
5142 mvpp2_txdesc_offset_set(port, tx_desc,
5143 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5144 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5145 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
5146 /* First and Last descriptor */
5147 mvpp2_txdesc_cmd_set(port, tx_desc,
5148 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5149 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
5152 flush_dcache_range((unsigned long)packet,
5153 (unsigned long)packet + ALIGN(length, PKTALIGN));
5155 /* Enable transmit */
5157 mvpp2_aggr_txq_pend_desc_add(port, 1);
5159 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5163 if (timeout++ > 10000) {
5164 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5167 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5172 if (timeout++ > 10000) {
5173 printf("timeout: packet not sent\n");
5176 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5182 static int mvpp2_start(struct udevice *dev)
5184 struct eth_pdata *pdata = dev_get_platdata(dev);
5185 struct mvpp2_port *port = dev_get_priv(dev);
5187 /* Load current MAC address */
5188 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5190 /* Reconfigure parser accept the original MAC address */
5191 mvpp2_prs_update_mac_da(port, port->dev_addr);
5193 switch (port->phy_interface) {
5194 case PHY_INTERFACE_MODE_RGMII:
5195 case PHY_INTERFACE_MODE_RGMII_ID:
5196 case PHY_INTERFACE_MODE_SGMII:
5197 mvpp2_port_power_up(port);
5202 mvpp2_open(dev, port);
5207 static void mvpp2_stop(struct udevice *dev)
5209 struct mvpp2_port *port = dev_get_priv(dev);
5211 mvpp2_stop_dev(port);
5212 mvpp2_cleanup_rxqs(port);
5213 mvpp2_cleanup_txqs(port);
5216 static int mvpp2_write_hwaddr(struct udevice *dev)
5218 struct mvpp2_port *port = dev_get_priv(dev);
5220 return mvpp2_prs_update_mac_da(port, port->dev_addr);
5223 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
5225 writel(port->phyaddr, port->priv->iface_base +
5226 MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
5231 static int mvpp2_base_probe(struct udevice *dev)
5233 struct mvpp2 *priv = dev_get_priv(dev);
5238 /* Save hw-version */
5239 priv->hw_version = dev_get_driver_data(dev);
5242 * U-Boot special buffer handling:
5244 * Allocate buffer area for descs and rx_buffers. This is only
5245 * done once for all interfaces. As only one interface can
5246 * be active. Make this area DMA-safe by disabling the D-cache
5249 /* Align buffer area for descs and rx_buffers to 1MiB */
5250 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
5251 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5252 BD_SPACE, DCACHE_OFF);
5254 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5255 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
5257 buffer_loc.tx_descs =
5258 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
5259 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
5261 buffer_loc.rx_descs =
5262 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
5263 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
5265 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5266 buffer_loc.bm_pool[i] =
5267 (unsigned long *)((unsigned long)bd_space + size);
5268 if (priv->hw_version == MVPP21)
5269 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5271 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
5274 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
5275 buffer_loc.rx_buffer[i] =
5276 (unsigned long *)((unsigned long)bd_space + size);
5277 size += RX_BUFFER_SIZE;
5280 /* Clear the complete area so that all descriptors are cleared */
5281 memset(bd_space, 0, size);
5283 /* Save base addresses for later use */
5284 priv->base = (void *)devfdt_get_addr_index(dev, 0);
5285 if (IS_ERR(priv->base))
5286 return PTR_ERR(priv->base);
5288 if (priv->hw_version == MVPP21) {
5289 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
5290 if (IS_ERR(priv->lms_base))
5291 return PTR_ERR(priv->lms_base);
5293 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
5294 if (IS_ERR(priv->iface_base))
5295 return PTR_ERR(priv->iface_base);
5297 /* Store common base addresses for all ports */
5298 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5299 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5300 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
5303 if (priv->hw_version == MVPP21)
5304 priv->max_port_rxqs = 8;
5306 priv->max_port_rxqs = 32;
5311 static int mvpp2_probe(struct udevice *dev)
5313 struct mvpp2_port *port = dev_get_priv(dev);
5314 struct mvpp2 *priv = dev_get_priv(dev->parent);
5317 /* Only call the probe function for the parent once */
5318 if (!priv->probe_done)
5319 err = mvpp2_base_probe(dev->parent);
5323 err = phy_info_parse(dev, port);
5328 * We need the port specific io base addresses at this stage, since
5329 * gop_port_init() accesses these registers
5331 if (priv->hw_version == MVPP21) {
5332 int priv_common_regs_num = 2;
5334 port->base = (void __iomem *)devfdt_get_addr_index(
5335 dev->parent, priv_common_regs_num + port->id);
5336 if (IS_ERR(port->base))
5337 return PTR_ERR(port->base);
5339 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5341 if (port->id == -1) {
5342 dev_err(&pdev->dev, "missing gop-port-id value\n");
5346 port->base = priv->iface_base + MVPP22_PORT_BASE +
5347 port->gop_id * MVPP22_PORT_OFFSET;
5349 /* Set phy address of the port */
5350 if (port->phyaddr < PHY_MAX_ADDR)
5351 mvpp22_smi_phy_addr_cfg(port);
5354 gop_port_init(port);
5357 if (!priv->probe_done) {
5358 /* Initialize network controller */
5359 err = mvpp2_init(dev, priv);
5361 dev_err(&pdev->dev, "failed to initialize controller\n");
5364 priv->num_ports = 0;
5365 priv->probe_done = 1;
5368 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5372 if (priv->hw_version == MVPP22) {
5373 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5374 port->phy_interface);
5376 /* Netcomplex configurations for all ports */
5377 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5378 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5385 * Empty BM pool and stop its activity before the OS is started
5387 static int mvpp2_remove(struct udevice *dev)
5389 struct mvpp2_port *port = dev_get_priv(dev);
5390 struct mvpp2 *priv = port->priv;
5395 if (priv->num_ports)
5398 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5399 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5404 static const struct eth_ops mvpp2_ops = {
5405 .start = mvpp2_start,
5409 .write_hwaddr = mvpp2_write_hwaddr
5412 static struct driver mvpp2_driver = {
5415 .probe = mvpp2_probe,
5416 .remove = mvpp2_remove,
5418 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
5419 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5420 .flags = DM_FLAG_ACTIVE_DMA,
5424 * Use a MISC device to bind the n instances (child nodes) of the
5425 * network base controller in UCLASS_ETH.
5427 static int mvpp2_base_bind(struct udevice *parent)
5429 const void *blob = gd->fdt_blob;
5430 int node = dev_of_offset(parent);
5431 struct uclass_driver *drv;
5432 struct udevice *dev;
5433 struct eth_pdata *plat;
5439 /* Lookup eth driver */
5440 drv = lists_uclass_lookup(UCLASS_ETH);
5442 puts("Cannot find eth driver\n");
5446 base_id_add = base_id;
5448 fdt_for_each_subnode(subnode, blob, node) {
5449 /* Increment base_id for all subnodes, also the disabled ones */
5452 /* Skip disabled ports */
5453 if (!fdtdec_get_is_enabled(blob, subnode))
5456 plat = calloc(1, sizeof(*plat));
5460 id = fdtdec_get_int(blob, subnode, "port-id", -1);
5463 name = calloc(1, 16);
5468 sprintf(name, "mvpp2-%d", id);
5470 /* Create child device UCLASS_ETH and bind it */
5471 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
5472 dev_set_of_offset(dev, subnode);
5478 static const struct udevice_id mvpp2_ids[] = {
5480 .compatible = "marvell,armada-375-pp2",
5484 .compatible = "marvell,armada-7k-pp22",
5490 U_BOOT_DRIVER(mvpp2_base) = {
5491 .name = "mvpp2_base",
5493 .of_match = mvpp2_ids,
5494 .bind = mvpp2_base_bind,
5495 .priv_auto_alloc_size = sizeof(struct mvpp2),