1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
12 * The u-boot networking stack is a little weird. It seems like the
13 * networking core allocates receive buffers up front without any
14 * regard to the hardware that's supposed to actually receive those
17 * The MACB receives packets into 128-byte receive buffers, so the
18 * buffers allocated by the core isn't very practical to use. We'll
19 * allocate our own, but we need one such buffer in case a packet
20 * wraps around the DMA ring so that we have to copy it.
22 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
23 * configuration header. This way, the core allocates one RX buffer
24 * and one TX buffer, each of which can hold a ethernet packet of
27 * For some reason, the networking core unconditionally specifies a
28 * 32-byte packet "alignment" (which really should be called
29 * "padding"). MACB shouldn't need that, but we'll refrain from any
30 * core modifications here...
40 #include <linux/mii.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/arch/clk.h>
44 #include <linux/errno.h>
48 DECLARE_GLOBAL_DATA_PTR;
51 * These buffer sizes must be power of 2 and divisible
52 * by RX_BUFFER_MULTIPLE
54 #define MACB_RX_BUFFER_SIZE 128
55 #define GEM_RX_BUFFER_SIZE 2048
56 #define RX_BUFFER_MULTIPLE 64
58 #define MACB_RX_RING_SIZE 32
59 #define MACB_TX_RING_SIZE 16
61 #define MACB_TX_TIMEOUT 1000
62 #define MACB_AUTONEG_TIMEOUT 5000000
64 #ifdef CONFIG_MACB_ZYNQ
65 /* INCR4 AHB bursts */
66 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
67 /* Use full configured addressable space (8 Kb) */
68 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
69 /* Use full configured addressable space (4 Kb) */
70 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
71 /* Set RXBUF with use of 128 byte */
72 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
73 #define MACB_ZYNQ_GEM_DMACR_INIT \
74 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
75 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
76 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
77 MACB_ZYNQ_GEM_DMACR_RXBUF)
80 struct macb_dma_desc {
85 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
86 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
87 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
88 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
90 #define RXBUF_FRMLEN_MASK 0x00000fff
91 #define TXBUF_FRMLEN_MASK 0x000007ff
98 const struct macb_config *config;
100 unsigned int rx_tail;
101 unsigned int tx_head;
102 unsigned int tx_tail;
103 unsigned int next_rx_tail;
108 struct macb_dma_desc *rx_ring;
109 struct macb_dma_desc *tx_ring;
110 size_t rx_buffer_size;
112 unsigned long rx_buffer_dma;
113 unsigned long rx_ring_dma;
114 unsigned long tx_ring_dma;
116 struct macb_dma_desc *dummy_desc;
117 unsigned long dummy_desc_dma;
119 const struct device *dev;
120 #ifndef CONFIG_DM_ETH
121 struct eth_device netdev;
123 unsigned short phy_addr;
126 struct phy_device *phydev;
131 unsigned long pclk_rate;
133 phy_interface_t phy_interface;
138 unsigned int dma_burst_length;
140 int (*clk_init)(struct udevice *dev, ulong rate);
143 #ifndef CONFIG_DM_ETH
144 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
147 static int macb_is_gem(struct macb_device *macb)
149 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
152 #ifndef cpu_is_sama5d2
153 #define cpu_is_sama5d2() 0
156 #ifndef cpu_is_sama5d4
157 #define cpu_is_sama5d4() 0
160 static int gem_is_gigabit_capable(struct macb_device *macb)
163 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
164 * configured to support only 10/100.
166 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
169 static void macb_mdio_write(struct macb_device *macb, u8 phy_adr, u8 reg,
172 unsigned long netctl;
173 unsigned long netstat;
176 netctl = macb_readl(macb, NCR);
177 netctl |= MACB_BIT(MPE);
178 macb_writel(macb, NCR, netctl);
180 frame = (MACB_BF(SOF, 1)
182 | MACB_BF(PHYA, phy_adr)
185 | MACB_BF(DATA, value));
186 macb_writel(macb, MAN, frame);
189 netstat = macb_readl(macb, NSR);
190 } while (!(netstat & MACB_BIT(IDLE)));
192 netctl = macb_readl(macb, NCR);
193 netctl &= ~MACB_BIT(MPE);
194 macb_writel(macb, NCR, netctl);
197 static u16 macb_mdio_read(struct macb_device *macb, u8 phy_adr, u8 reg)
199 unsigned long netctl;
200 unsigned long netstat;
203 netctl = macb_readl(macb, NCR);
204 netctl |= MACB_BIT(MPE);
205 macb_writel(macb, NCR, netctl);
207 frame = (MACB_BF(SOF, 1)
209 | MACB_BF(PHYA, phy_adr)
212 macb_writel(macb, MAN, frame);
215 netstat = macb_readl(macb, NSR);
216 } while (!(netstat & MACB_BIT(IDLE)));
218 frame = macb_readl(macb, MAN);
220 netctl = macb_readl(macb, NCR);
221 netctl &= ~MACB_BIT(MPE);
222 macb_writel(macb, NCR, netctl);
224 return MACB_BFEXT(DATA, frame);
227 void __weak arch_get_mdio_control(const char *name)
232 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
234 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
238 struct udevice *dev = eth_get_dev_by_name(bus->name);
239 struct macb_device *macb = dev_get_priv(dev);
241 struct eth_device *dev = eth_get_dev_by_name(bus->name);
242 struct macb_device *macb = to_macb(dev);
245 arch_get_mdio_control(bus->name);
246 value = macb_mdio_read(macb, phy_adr, reg);
251 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
255 struct udevice *dev = eth_get_dev_by_name(bus->name);
256 struct macb_device *macb = dev_get_priv(dev);
258 struct eth_device *dev = eth_get_dev_by_name(bus->name);
259 struct macb_device *macb = to_macb(dev);
262 arch_get_mdio_control(bus->name);
263 macb_mdio_write(macb, phy_adr, reg, value);
271 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
274 invalidate_dcache_range(macb->rx_ring_dma,
275 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
278 invalidate_dcache_range(macb->tx_ring_dma,
279 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
283 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
286 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
287 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
289 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
290 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
293 static inline void macb_flush_rx_buffer(struct macb_device *macb)
295 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
296 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
300 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
302 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
303 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
307 #if defined(CONFIG_CMD_NET)
309 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
312 unsigned long paddr, ctrl;
313 unsigned int tx_head = macb->tx_head;
316 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
318 ctrl = length & TXBUF_FRMLEN_MASK;
319 ctrl |= MACB_BIT(TX_LAST);
320 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
321 ctrl |= MACB_BIT(TX_WRAP);
327 macb->tx_ring[tx_head].ctrl = ctrl;
328 macb->tx_ring[tx_head].addr = paddr;
330 macb_flush_ring_desc(macb, TX);
331 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
334 * I guess this is necessary because the networking core may
335 * re-use the transmit buffer as soon as we return...
337 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
339 macb_invalidate_ring_desc(macb, TX);
340 ctrl = macb->tx_ring[tx_head].ctrl;
341 if (ctrl & MACB_BIT(TX_USED))
346 dma_unmap_single(paddr, length, DMA_TO_DEVICE);
348 if (i <= MACB_TX_TIMEOUT) {
349 if (ctrl & MACB_BIT(TX_UNDERRUN))
350 printf("%s: TX underrun\n", name);
351 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
352 printf("%s: TX buffers exhausted in mid frame\n", name);
354 printf("%s: TX timeout\n", name);
357 /* No one cares anyway */
361 static void reclaim_rx_buffers(struct macb_device *macb,
362 unsigned int new_tail)
368 macb_invalidate_ring_desc(macb, RX);
369 while (i > new_tail) {
370 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
372 if (i > MACB_RX_RING_SIZE)
376 while (i < new_tail) {
377 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
382 macb_flush_ring_desc(macb, RX);
383 macb->rx_tail = new_tail;
386 static int _macb_recv(struct macb_device *macb, uchar **packetp)
388 unsigned int next_rx_tail = macb->next_rx_tail;
393 macb->wrapped = false;
395 macb_invalidate_ring_desc(macb, RX);
397 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
400 status = macb->rx_ring[next_rx_tail].ctrl;
401 if (status & MACB_BIT(RX_SOF)) {
402 if (next_rx_tail != macb->rx_tail)
403 reclaim_rx_buffers(macb, next_rx_tail);
404 macb->wrapped = false;
407 if (status & MACB_BIT(RX_EOF)) {
408 buffer = macb->rx_buffer +
409 macb->rx_buffer_size * macb->rx_tail;
410 length = status & RXBUF_FRMLEN_MASK;
412 macb_invalidate_rx_buffer(macb);
414 unsigned int headlen, taillen;
416 headlen = macb->rx_buffer_size *
417 (MACB_RX_RING_SIZE - macb->rx_tail);
418 taillen = length - headlen;
419 memcpy((void *)net_rx_packets[0],
421 memcpy((void *)net_rx_packets[0] + headlen,
422 macb->rx_buffer, taillen);
423 *packetp = (void *)net_rx_packets[0];
428 if (++next_rx_tail >= MACB_RX_RING_SIZE)
430 macb->next_rx_tail = next_rx_tail;
433 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
434 macb->wrapped = true;
442 static void macb_phy_reset(struct macb_device *macb, const char *name)
447 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
448 macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv);
449 printf("%s: Starting autonegotiation...\n", name);
450 macb_mdio_write(macb, macb->phy_addr, MII_BMCR, (BMCR_ANENABLE
453 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
454 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
455 if (status & BMSR_ANEGCOMPLETE)
460 if (status & BMSR_ANEGCOMPLETE)
461 printf("%s: Autonegotiation complete\n", name);
463 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
467 static int macb_phy_find(struct macb_device *macb, const char *name)
472 /* Search for PHY... */
473 for (i = 0; i < 32; i++) {
475 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
476 if (phy_id != 0xffff) {
477 printf("%s: PHY present at %d\n", name, i);
482 /* PHY isn't up to snuff */
483 printf("%s: PHY not found\n", name);
489 * macb_linkspd_cb - Linkspeed change callback function
490 * @dev/@regs: MACB udevice (DM version) or
491 * Base Register of MACB devices (non-DM version)
493 * Returns 0 when operation success and negative errno number
494 * when operation failed.
497 static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
502 addr = dev_read_addr_index(dev, 1);
503 if (addr == FDT_ADDR_T_NONE)
506 gemgxl_regs = (void __iomem *)addr;
511 * SiFive GEMGXL TX clock operation mode:
513 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
514 * and output clock on GMII output signal GTX_CLK
515 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
517 writel(rate != 125000000, gemgxl_regs);
521 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
524 struct macb_device *macb = dev_get_priv(dev);
531 rate = 2500000; /* 2.5 MHz */
534 rate = 25000000; /* 25 MHz */
537 rate = 125000000; /* 125 MHz */
540 /* does not change anything */
544 if (macb->config->clk_init)
545 return macb->config->clk_init(dev, rate);
548 * "tx_clk" is an optional clock source for MACB.
549 * Ignore if it does not exist in DT.
551 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
556 ret = clk_set_rate(&tx_clk, rate);
565 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
572 static int macb_phy_init(struct udevice *dev, const char *name)
574 static int macb_phy_init(struct macb_device *macb, const char *name)
578 struct macb_device *macb = dev_get_priv(dev);
581 u16 phy_id, status, adv, lpa;
582 int media, speed, duplex;
586 arch_get_mdio_control(name);
587 /* Auto-detect phy_addr */
588 ret = macb_phy_find(macb, name);
592 /* Check if the PHY is up to snuff... */
593 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
594 if (phy_id == 0xffff) {
595 printf("%s: No PHY present\n", name);
601 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
602 macb->phy_interface);
604 /* need to consider other phy interface mode */
605 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
606 PHY_INTERFACE_MODE_RGMII);
609 printf("phy_connect failed\n");
613 phy_config(macb->phydev);
616 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
617 if (!(status & BMSR_LSTATUS)) {
618 /* Try to re-negotiate if we don't have link already. */
619 macb_phy_reset(macb, name);
621 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
622 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
623 if (status & BMSR_LSTATUS) {
625 * Delay a bit after the link is established,
626 * so that the next xfer does not fail
635 if (!(status & BMSR_LSTATUS)) {
636 printf("%s: link down (status: 0x%04x)\n",
641 /* First check for GMAC and that it is GiB capable */
642 if (gem_is_gigabit_capable(macb)) {
643 lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000);
645 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
647 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
650 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
652 duplex ? "full" : "half",
655 ncfgr = macb_readl(macb, NCFGR);
656 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
657 ncfgr |= GEM_BIT(GBE);
660 ncfgr |= MACB_BIT(FD);
662 macb_writel(macb, NCFGR, ncfgr);
665 ret = macb_linkspd_cb(dev, _1000BASET);
667 ret = macb_linkspd_cb(macb->regs, _1000BASET);
676 /* fall back for EMAC checking */
677 adv = macb_mdio_read(macb, macb->phy_addr, MII_ADVERTISE);
678 lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA);
679 media = mii_nway_result(lpa & adv);
680 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
682 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
683 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
685 speed ? "100" : "10",
686 duplex ? "full" : "half",
689 ncfgr = macb_readl(macb, NCFGR);
690 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
692 ncfgr |= MACB_BIT(SPD);
694 ret = macb_linkspd_cb(dev, _100BASET);
696 ret = macb_linkspd_cb(macb->regs, _100BASET);
700 ret = macb_linkspd_cb(dev, _10BASET);
702 ret = macb_linkspd_cb(macb->regs, _10BASET);
710 ncfgr |= MACB_BIT(FD);
711 macb_writel(macb, NCFGR, ncfgr);
716 static int gmac_init_multi_queues(struct macb_device *macb)
718 int i, num_queues = 1;
721 /* bit 0 is never set but queue 0 always exists */
722 queue_mask = gem_readl(macb, DCFG6) & 0xff;
725 for (i = 1; i < MACB_MAX_QUEUES; i++)
726 if (queue_mask & (1 << i))
729 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
730 macb->dummy_desc->addr = 0;
731 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
732 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
734 for (i = 1; i < num_queues; i++)
735 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
740 static void gmac_configure_dma(struct macb_device *macb)
745 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
746 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
747 dmacfg |= GEM_BF(RXBS, buffer_size);
749 if (macb->config->dma_burst_length)
750 dmacfg = GEM_BFINS(FBLDO,
751 macb->config->dma_burst_length, dmacfg);
753 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
754 dmacfg &= ~GEM_BIT(ENDIA_PKT);
756 if (macb->is_big_endian)
757 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
759 dmacfg &= ~GEM_BIT(ENDIA_DESC);
761 dmacfg &= ~GEM_BIT(ADDR64);
762 gem_writel(macb, DMACFG, dmacfg);
766 static int _macb_init(struct udevice *dev, const char *name)
768 static int _macb_init(struct macb_device *macb, const char *name)
772 struct macb_device *macb = dev_get_priv(dev);
779 * macb_halt should have been called at some point before now,
780 * so we'll assume the controller is idle.
783 /* initialize DMA descriptors */
784 paddr = macb->rx_buffer_dma;
785 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
786 if (i == (MACB_RX_RING_SIZE - 1))
787 paddr |= MACB_BIT(RX_WRAP);
788 macb->rx_ring[i].addr = paddr;
789 macb->rx_ring[i].ctrl = 0;
790 paddr += macb->rx_buffer_size;
792 macb_flush_ring_desc(macb, RX);
793 macb_flush_rx_buffer(macb);
795 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
796 macb->tx_ring[i].addr = 0;
797 if (i == (MACB_TX_RING_SIZE - 1))
798 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
801 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
803 macb_flush_ring_desc(macb, TX);
808 macb->next_rx_tail = 0;
810 #ifdef CONFIG_MACB_ZYNQ
811 gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
814 macb_writel(macb, RBQP, macb->rx_ring_dma);
815 macb_writel(macb, TBQP, macb->tx_ring_dma);
817 if (macb_is_gem(macb)) {
818 /* Initialize DMA properties */
819 gmac_configure_dma(macb);
820 /* Check the multi queue and initialize the queue for tx */
821 gmac_init_multi_queues(macb);
824 * When the GMAC IP with GE feature, this bit is used to
825 * select interface between RGMII and GMII.
826 * When the GMAC IP without GE feature, this bit is used
827 * to select interface between RMII and MII.
830 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
831 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
832 gem_writel(macb, USRIO, GEM_BIT(RGMII));
834 gem_writel(macb, USRIO, 0);
836 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
837 unsigned int ncfgr = macb_readl(macb, NCFGR);
839 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
840 macb_writel(macb, NCFGR, ncfgr);
843 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
844 gem_writel(macb, USRIO, GEM_BIT(RGMII));
846 gem_writel(macb, USRIO, 0);
850 /* choose RMII or MII mode. This depends on the board */
852 #ifdef CONFIG_AT91FAMILY
853 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
854 macb_writel(macb, USRIO,
855 MACB_BIT(RMII) | MACB_BIT(CLKEN));
857 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
860 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
861 macb_writel(macb, USRIO, 0);
863 macb_writel(macb, USRIO, MACB_BIT(MII));
867 #ifdef CONFIG_AT91FAMILY
868 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
870 macb_writel(macb, USRIO, 0);
873 #ifdef CONFIG_AT91FAMILY
874 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
876 macb_writel(macb, USRIO, MACB_BIT(MII));
878 #endif /* CONFIG_RMII */
883 ret = macb_phy_init(dev, name);
885 ret = macb_phy_init(macb, name);
890 /* Enable TX and RX */
891 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
896 static void _macb_halt(struct macb_device *macb)
900 /* Halt the controller and wait for any ongoing transmission to end. */
901 ncr = macb_readl(macb, NCR);
902 ncr |= MACB_BIT(THALT);
903 macb_writel(macb, NCR, ncr);
906 tsr = macb_readl(macb, TSR);
907 } while (tsr & MACB_BIT(TGO));
909 /* Disable TX and RX, and clear statistics */
910 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
913 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
918 /* set hardware address */
919 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
920 enetaddr[2] << 16 | enetaddr[3] << 24;
921 macb_writel(macb, SA1B, hwaddr_bottom);
922 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
923 macb_writel(macb, SA1T, hwaddr_top);
927 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
930 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
931 unsigned long macb_hz = macb->pclk_rate;
933 unsigned long macb_hz = get_macb_pclk_rate(id);
936 if (macb_hz < 20000000)
937 config = MACB_BF(CLK, MACB_CLK_DIV8);
938 else if (macb_hz < 40000000)
939 config = MACB_BF(CLK, MACB_CLK_DIV16);
940 else if (macb_hz < 80000000)
941 config = MACB_BF(CLK, MACB_CLK_DIV32);
943 config = MACB_BF(CLK, MACB_CLK_DIV64);
948 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
952 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
953 unsigned long macb_hz = macb->pclk_rate;
955 unsigned long macb_hz = get_macb_pclk_rate(id);
958 if (macb_hz < 20000000)
959 config = GEM_BF(CLK, GEM_CLK_DIV8);
960 else if (macb_hz < 40000000)
961 config = GEM_BF(CLK, GEM_CLK_DIV16);
962 else if (macb_hz < 80000000)
963 config = GEM_BF(CLK, GEM_CLK_DIV32);
964 else if (macb_hz < 120000000)
965 config = GEM_BF(CLK, GEM_CLK_DIV48);
966 else if (macb_hz < 160000000)
967 config = GEM_BF(CLK, GEM_CLK_DIV64);
968 else if (macb_hz < 240000000)
969 config = GEM_BF(CLK, GEM_CLK_DIV96);
970 else if (macb_hz < 320000000)
971 config = GEM_BF(CLK, GEM_CLK_DIV128);
973 config = GEM_BF(CLK, GEM_CLK_DIV224);
979 * Get the DMA bus width field of the network configuration register that we
980 * should program. We find the width from decoding the design configuration
981 * register to find the maximum supported data bus width.
983 static u32 macb_dbw(struct macb_device *macb)
985 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
987 return GEM_BF(DBW, GEM_DBW128);
989 return GEM_BF(DBW, GEM_DBW64);
992 return GEM_BF(DBW, GEM_DBW32);
996 static void _macb_eth_initialize(struct macb_device *macb)
998 int id = 0; /* This is not used by functions we call */
1001 if (macb_is_gem(macb))
1002 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1004 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1006 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
1007 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1009 &macb->rx_buffer_dma);
1010 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
1011 &macb->rx_ring_dma);
1012 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
1013 &macb->tx_ring_dma);
1014 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1015 &macb->dummy_desc_dma);
1018 * Do some basic initialization so that we at least can talk
1021 if (macb_is_gem(macb)) {
1022 ncfgr = gem_mdc_clk_div(id, macb);
1023 ncfgr |= macb_dbw(macb);
1025 ncfgr = macb_mdc_clk_div(id, macb);
1028 macb_writel(macb, NCFGR, ncfgr);
1031 #ifndef CONFIG_DM_ETH
1032 static int macb_send(struct eth_device *netdev, void *packet, int length)
1034 struct macb_device *macb = to_macb(netdev);
1036 return _macb_send(macb, netdev->name, packet, length);
1039 static int macb_recv(struct eth_device *netdev)
1041 struct macb_device *macb = to_macb(netdev);
1045 macb->wrapped = false;
1047 macb->next_rx_tail = macb->rx_tail;
1048 length = _macb_recv(macb, &packet);
1050 net_process_received_packet(packet, length);
1051 reclaim_rx_buffers(macb, macb->next_rx_tail);
1058 static int macb_init(struct eth_device *netdev, bd_t *bd)
1060 struct macb_device *macb = to_macb(netdev);
1062 return _macb_init(macb, netdev->name);
1065 static void macb_halt(struct eth_device *netdev)
1067 struct macb_device *macb = to_macb(netdev);
1069 return _macb_halt(macb);
1072 static int macb_write_hwaddr(struct eth_device *netdev)
1074 struct macb_device *macb = to_macb(netdev);
1076 return _macb_write_hwaddr(macb, netdev->enetaddr);
1079 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1081 struct macb_device *macb;
1082 struct eth_device *netdev;
1084 macb = malloc(sizeof(struct macb_device));
1086 printf("Error: Failed to allocate memory for MACB%d\n", id);
1089 memset(macb, 0, sizeof(struct macb_device));
1091 netdev = &macb->netdev;
1094 macb->phy_addr = phy_addr;
1096 if (macb_is_gem(macb))
1097 sprintf(netdev->name, "gmac%d", id);
1099 sprintf(netdev->name, "macb%d", id);
1101 netdev->init = macb_init;
1102 netdev->halt = macb_halt;
1103 netdev->send = macb_send;
1104 netdev->recv = macb_recv;
1105 netdev->write_hwaddr = macb_write_hwaddr;
1107 _macb_eth_initialize(macb);
1109 eth_register(netdev);
1111 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1113 struct mii_dev *mdiodev = mdio_alloc();
1116 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1117 mdiodev->read = macb_miiphy_read;
1118 mdiodev->write = macb_miiphy_write;
1120 retval = mdio_register(mdiodev);
1123 macb->bus = miiphy_get_dev_by_name(netdev->name);
1127 #endif /* !CONFIG_DM_ETH */
1129 #ifdef CONFIG_DM_ETH
1131 static int macb_start(struct udevice *dev)
1133 return _macb_init(dev, dev->name);
1136 static int macb_send(struct udevice *dev, void *packet, int length)
1138 struct macb_device *macb = dev_get_priv(dev);
1140 return _macb_send(macb, dev->name, packet, length);
1143 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1145 struct macb_device *macb = dev_get_priv(dev);
1147 macb->next_rx_tail = macb->rx_tail;
1148 macb->wrapped = false;
1150 return _macb_recv(macb, packetp);
1153 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1155 struct macb_device *macb = dev_get_priv(dev);
1157 reclaim_rx_buffers(macb, macb->next_rx_tail);
1162 static void macb_stop(struct udevice *dev)
1164 struct macb_device *macb = dev_get_priv(dev);
1169 static int macb_write_hwaddr(struct udevice *dev)
1171 struct eth_pdata *plat = dev_get_platdata(dev);
1172 struct macb_device *macb = dev_get_priv(dev);
1174 return _macb_write_hwaddr(macb, plat->enetaddr);
1177 static const struct eth_ops macb_eth_ops = {
1178 .start = macb_start,
1182 .free_pkt = macb_free_pkt,
1183 .write_hwaddr = macb_write_hwaddr,
1187 static int macb_enable_clk(struct udevice *dev)
1189 struct macb_device *macb = dev_get_priv(dev);
1194 ret = clk_get_by_index(dev, 0, &clk);
1199 * If clock driver didn't support enable or disable then
1200 * we get -ENOSYS from clk_enable(). To handle this, we
1201 * don't fail for ret == -ENOSYS.
1203 ret = clk_enable(&clk);
1204 if (ret && ret != -ENOSYS)
1207 clk_rate = clk_get_rate(&clk);
1211 macb->pclk_rate = clk_rate;
1217 static const struct macb_config default_gem_config = {
1218 .dma_burst_length = 16,
1222 static int macb_eth_probe(struct udevice *dev)
1224 struct eth_pdata *pdata = dev_get_platdata(dev);
1225 struct macb_device *macb = dev_get_priv(dev);
1226 const char *phy_mode;
1229 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1232 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1233 if (macb->phy_interface == -1) {
1234 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1238 macb->regs = (void *)pdata->iobase;
1240 macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
1242 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1244 macb->config = &default_gem_config;
1247 ret = macb_enable_clk(dev);
1252 _macb_eth_initialize(macb);
1254 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1255 macb->bus = mdio_alloc();
1258 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1259 macb->bus->read = macb_miiphy_read;
1260 macb->bus->write = macb_miiphy_write;
1262 ret = mdio_register(macb->bus);
1265 macb->bus = miiphy_get_dev_by_name(dev->name);
1271 static int macb_eth_remove(struct udevice *dev)
1273 struct macb_device *macb = dev_get_priv(dev);
1275 #ifdef CONFIG_PHYLIB
1278 mdio_unregister(macb->bus);
1279 mdio_free(macb->bus);
1285 * macb_late_eth_ofdata_to_platdata
1286 * @dev: udevice struct
1287 * Returns 0 when operation success and negative errno number
1288 * when operation failed.
1290 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1295 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1297 struct eth_pdata *pdata = dev_get_platdata(dev);
1299 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1303 return macb_late_eth_ofdata_to_platdata(dev);
1306 static const struct macb_config sama5d4_config = {
1307 .dma_burst_length = 4,
1311 static const struct macb_config sifive_config = {
1312 .dma_burst_length = 16,
1313 .clk_init = macb_sifive_clk_init,
1316 static const struct udevice_id macb_eth_ids[] = {
1317 { .compatible = "cdns,macb" },
1318 { .compatible = "cdns,at91sam9260-macb" },
1319 { .compatible = "cdns,sam9x60-macb" },
1320 { .compatible = "atmel,sama5d2-gem" },
1321 { .compatible = "atmel,sama5d3-gem" },
1322 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1323 { .compatible = "cdns,zynq-gem" },
1324 { .compatible = "sifive,fu540-c000-gem",
1325 .data = (ulong)&sifive_config },
1329 U_BOOT_DRIVER(eth_macb) = {
1332 .of_match = macb_eth_ids,
1333 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1334 .probe = macb_eth_probe,
1335 .remove = macb_eth_remove,
1336 .ops = &macb_eth_ops,
1337 .priv_auto_alloc_size = sizeof(struct macb_device),
1338 .platdata_auto_alloc_size = sizeof(struct eth_pdata),