1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
21 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
38 #include <linux/mii.h>
40 #include <asm/dma-mapping.h>
41 #include <asm/arch/clk.h>
42 #include <linux/errno.h>
46 DECLARE_GLOBAL_DATA_PTR;
49 * These buffer sizes must be power of 2 and divisible
50 * by RX_BUFFER_MULTIPLE
52 #define MACB_RX_BUFFER_SIZE 128
53 #define GEM_RX_BUFFER_SIZE 2048
54 #define RX_BUFFER_MULTIPLE 64
56 #define MACB_RX_RING_SIZE 32
57 #define MACB_TX_RING_SIZE 16
59 #define MACB_TX_TIMEOUT 1000
60 #define MACB_AUTONEG_TIMEOUT 5000000
62 #ifdef CONFIG_MACB_ZYNQ
63 /* INCR4 AHB bursts */
64 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
65 /* Use full configured addressable space (8 Kb) */
66 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
67 /* Use full configured addressable space (4 Kb) */
68 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
69 /* Set RXBUF with use of 128 byte */
70 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
71 #define MACB_ZYNQ_GEM_DMACR_INIT \
72 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
73 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
74 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
75 MACB_ZYNQ_GEM_DMACR_RXBUF)
78 struct macb_dma_desc {
83 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
84 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
85 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
86 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
88 #define RXBUF_FRMLEN_MASK 0x00000fff
89 #define TXBUF_FRMLEN_MASK 0x000007ff
96 const struct macb_config *config;
100 unsigned int tx_tail;
101 unsigned int next_rx_tail;
106 struct macb_dma_desc *rx_ring;
107 struct macb_dma_desc *tx_ring;
108 size_t rx_buffer_size;
110 unsigned long rx_buffer_dma;
111 unsigned long rx_ring_dma;
112 unsigned long tx_ring_dma;
114 struct macb_dma_desc *dummy_desc;
115 unsigned long dummy_desc_dma;
117 const struct device *dev;
118 #ifndef CONFIG_DM_ETH
119 struct eth_device netdev;
121 unsigned short phy_addr;
124 struct phy_device *phydev;
129 unsigned long pclk_rate;
131 phy_interface_t phy_interface;
136 unsigned int dma_burst_length;
138 int (*clk_init)(struct udevice *dev, ulong rate);
141 #ifndef CONFIG_DM_ETH
142 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
145 static int macb_is_gem(struct macb_device *macb)
147 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
150 #ifndef cpu_is_sama5d2
151 #define cpu_is_sama5d2() 0
154 #ifndef cpu_is_sama5d4
155 #define cpu_is_sama5d4() 0
158 static int gem_is_gigabit_capable(struct macb_device *macb)
161 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
162 * configured to support only 10/100.
164 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
167 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
169 unsigned long netctl;
170 unsigned long netstat;
173 netctl = macb_readl(macb, NCR);
174 netctl |= MACB_BIT(MPE);
175 macb_writel(macb, NCR, netctl);
177 frame = (MACB_BF(SOF, 1)
179 | MACB_BF(PHYA, macb->phy_addr)
182 | MACB_BF(DATA, value));
183 macb_writel(macb, MAN, frame);
186 netstat = macb_readl(macb, NSR);
187 } while (!(netstat & MACB_BIT(IDLE)));
189 netctl = macb_readl(macb, NCR);
190 netctl &= ~MACB_BIT(MPE);
191 macb_writel(macb, NCR, netctl);
194 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
196 unsigned long netctl;
197 unsigned long netstat;
200 netctl = macb_readl(macb, NCR);
201 netctl |= MACB_BIT(MPE);
202 macb_writel(macb, NCR, netctl);
204 frame = (MACB_BF(SOF, 1)
206 | MACB_BF(PHYA, macb->phy_addr)
209 macb_writel(macb, MAN, frame);
212 netstat = macb_readl(macb, NSR);
213 } while (!(netstat & MACB_BIT(IDLE)));
215 frame = macb_readl(macb, MAN);
217 netctl = macb_readl(macb, NCR);
218 netctl &= ~MACB_BIT(MPE);
219 macb_writel(macb, NCR, netctl);
221 return MACB_BFEXT(DATA, frame);
224 void __weak arch_get_mdio_control(const char *name)
229 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
231 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
235 struct udevice *dev = eth_get_dev_by_name(bus->name);
236 struct macb_device *macb = dev_get_priv(dev);
238 struct eth_device *dev = eth_get_dev_by_name(bus->name);
239 struct macb_device *macb = to_macb(dev);
242 if (macb->phy_addr != phy_adr)
245 arch_get_mdio_control(bus->name);
246 value = macb_mdio_read(macb, reg);
251 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
255 struct udevice *dev = eth_get_dev_by_name(bus->name);
256 struct macb_device *macb = dev_get_priv(dev);
258 struct eth_device *dev = eth_get_dev_by_name(bus->name);
259 struct macb_device *macb = to_macb(dev);
262 if (macb->phy_addr != phy_adr)
265 arch_get_mdio_control(bus->name);
266 macb_mdio_write(macb, reg, value);
274 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
277 invalidate_dcache_range(macb->rx_ring_dma,
278 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
281 invalidate_dcache_range(macb->tx_ring_dma,
282 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
286 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
289 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
290 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
292 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
293 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
296 static inline void macb_flush_rx_buffer(struct macb_device *macb)
298 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
299 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
303 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
305 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
306 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
310 #if defined(CONFIG_CMD_NET)
312 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
315 unsigned long paddr, ctrl;
316 unsigned int tx_head = macb->tx_head;
319 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
321 ctrl = length & TXBUF_FRMLEN_MASK;
322 ctrl |= MACB_BIT(TX_LAST);
323 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
324 ctrl |= MACB_BIT(TX_WRAP);
330 macb->tx_ring[tx_head].ctrl = ctrl;
331 macb->tx_ring[tx_head].addr = paddr;
333 macb_flush_ring_desc(macb, TX);
334 /* Do we need check paddr and length is dcache line aligned? */
335 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
336 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
339 * I guess this is necessary because the networking core may
340 * re-use the transmit buffer as soon as we return...
342 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
344 macb_invalidate_ring_desc(macb, TX);
345 ctrl = macb->tx_ring[tx_head].ctrl;
346 if (ctrl & MACB_BIT(TX_USED))
351 dma_unmap_single(packet, length, paddr);
353 if (i <= MACB_TX_TIMEOUT) {
354 if (ctrl & MACB_BIT(TX_UNDERRUN))
355 printf("%s: TX underrun\n", name);
356 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
357 printf("%s: TX buffers exhausted in mid frame\n", name);
359 printf("%s: TX timeout\n", name);
362 /* No one cares anyway */
366 static void reclaim_rx_buffers(struct macb_device *macb,
367 unsigned int new_tail)
373 macb_invalidate_ring_desc(macb, RX);
374 while (i > new_tail) {
375 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
377 if (i > MACB_RX_RING_SIZE)
381 while (i < new_tail) {
382 macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
387 macb_flush_ring_desc(macb, RX);
388 macb->rx_tail = new_tail;
391 static int _macb_recv(struct macb_device *macb, uchar **packetp)
393 unsigned int next_rx_tail = macb->next_rx_tail;
398 macb->wrapped = false;
400 macb_invalidate_ring_desc(macb, RX);
402 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
405 status = macb->rx_ring[next_rx_tail].ctrl;
406 if (status & MACB_BIT(RX_SOF)) {
407 if (next_rx_tail != macb->rx_tail)
408 reclaim_rx_buffers(macb, next_rx_tail);
409 macb->wrapped = false;
412 if (status & MACB_BIT(RX_EOF)) {
413 buffer = macb->rx_buffer +
414 macb->rx_buffer_size * macb->rx_tail;
415 length = status & RXBUF_FRMLEN_MASK;
417 macb_invalidate_rx_buffer(macb);
419 unsigned int headlen, taillen;
421 headlen = macb->rx_buffer_size *
422 (MACB_RX_RING_SIZE - macb->rx_tail);
423 taillen = length - headlen;
424 memcpy((void *)net_rx_packets[0],
426 memcpy((void *)net_rx_packets[0] + headlen,
427 macb->rx_buffer, taillen);
428 *packetp = (void *)net_rx_packets[0];
433 if (++next_rx_tail >= MACB_RX_RING_SIZE)
435 macb->next_rx_tail = next_rx_tail;
438 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
439 macb->wrapped = true;
447 static void macb_phy_reset(struct macb_device *macb, const char *name)
452 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
453 macb_mdio_write(macb, MII_ADVERTISE, adv);
454 printf("%s: Starting autonegotiation...\n", name);
455 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
458 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
459 status = macb_mdio_read(macb, MII_BMSR);
460 if (status & BMSR_ANEGCOMPLETE)
465 if (status & BMSR_ANEGCOMPLETE)
466 printf("%s: Autonegotiation complete\n", name);
468 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
472 static int macb_phy_find(struct macb_device *macb, const char *name)
477 /* Search for PHY... */
478 for (i = 0; i < 32; i++) {
480 phy_id = macb_mdio_read(macb, MII_PHYSID1);
481 if (phy_id != 0xffff) {
482 printf("%s: PHY present at %d\n", name, i);
487 /* PHY isn't up to snuff */
488 printf("%s: PHY not found\n", name);
494 * macb_linkspd_cb - Linkspeed change callback function
495 * @dev/@regs: MACB udevice (DM version) or
496 * Base Register of MACB devices (non-DM version)
498 * Returns 0 when operation success and negative errno number
499 * when operation failed.
502 static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
507 addr = dev_read_addr_index(dev, 1);
508 if (addr == FDT_ADDR_T_NONE)
511 gemgxl_regs = (void __iomem *)addr;
516 * SiFive GEMGXL TX clock operation mode:
518 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
519 * and output clock on GMII output signal GTX_CLK
520 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
522 writel(rate != 125000000, gemgxl_regs);
526 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
529 struct macb_device *macb = dev_get_priv(dev);
536 rate = 2500000; /* 2.5 MHz */
539 rate = 25000000; /* 25 MHz */
542 rate = 125000000; /* 125 MHz */
545 /* does not change anything */
549 if (macb->config->clk_init)
550 return macb->config->clk_init(dev, rate);
553 * "tx_clk" is an optional clock source for MACB.
554 * Ignore if it does not exist in DT.
556 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
561 ret = clk_set_rate(&tx_clk, rate);
570 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
577 static int macb_phy_init(struct udevice *dev, const char *name)
579 static int macb_phy_init(struct macb_device *macb, const char *name)
583 struct macb_device *macb = dev_get_priv(dev);
586 u16 phy_id, status, adv, lpa;
587 int media, speed, duplex;
591 arch_get_mdio_control(name);
592 /* Auto-detect phy_addr */
593 ret = macb_phy_find(macb, name);
597 /* Check if the PHY is up to snuff... */
598 phy_id = macb_mdio_read(macb, MII_PHYSID1);
599 if (phy_id == 0xffff) {
600 printf("%s: No PHY present\n", name);
606 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
607 macb->phy_interface);
609 /* need to consider other phy interface mode */
610 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
611 PHY_INTERFACE_MODE_RGMII);
614 printf("phy_connect failed\n");
618 phy_config(macb->phydev);
621 status = macb_mdio_read(macb, MII_BMSR);
622 if (!(status & BMSR_LSTATUS)) {
623 /* Try to re-negotiate if we don't have link already. */
624 macb_phy_reset(macb, name);
626 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
627 status = macb_mdio_read(macb, MII_BMSR);
628 if (status & BMSR_LSTATUS) {
630 * Delay a bit after the link is established,
631 * so that the next xfer does not fail
640 if (!(status & BMSR_LSTATUS)) {
641 printf("%s: link down (status: 0x%04x)\n",
646 /* First check for GMAC and that it is GiB capable */
647 if (gem_is_gigabit_capable(macb)) {
648 lpa = macb_mdio_read(macb, MII_STAT1000);
650 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
652 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
655 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
657 duplex ? "full" : "half",
660 ncfgr = macb_readl(macb, NCFGR);
661 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
662 ncfgr |= GEM_BIT(GBE);
665 ncfgr |= MACB_BIT(FD);
667 macb_writel(macb, NCFGR, ncfgr);
670 ret = macb_linkspd_cb(dev, _1000BASET);
672 ret = macb_linkspd_cb(macb->regs, _1000BASET);
681 /* fall back for EMAC checking */
682 adv = macb_mdio_read(macb, MII_ADVERTISE);
683 lpa = macb_mdio_read(macb, MII_LPA);
684 media = mii_nway_result(lpa & adv);
685 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
687 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
688 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
690 speed ? "100" : "10",
691 duplex ? "full" : "half",
694 ncfgr = macb_readl(macb, NCFGR);
695 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
697 ncfgr |= MACB_BIT(SPD);
699 ret = macb_linkspd_cb(dev, _100BASET);
701 ret = macb_linkspd_cb(macb->regs, _100BASET);
705 ret = macb_linkspd_cb(dev, _10BASET);
707 ret = macb_linkspd_cb(macb->regs, _10BASET);
715 ncfgr |= MACB_BIT(FD);
716 macb_writel(macb, NCFGR, ncfgr);
721 static int gmac_init_multi_queues(struct macb_device *macb)
723 int i, num_queues = 1;
726 /* bit 0 is never set but queue 0 always exists */
727 queue_mask = gem_readl(macb, DCFG6) & 0xff;
730 for (i = 1; i < MACB_MAX_QUEUES; i++)
731 if (queue_mask & (1 << i))
734 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
735 macb->dummy_desc->addr = 0;
736 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
737 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
739 for (i = 1; i < num_queues; i++)
740 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
745 static void gmac_configure_dma(struct macb_device *macb)
750 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
751 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
752 dmacfg |= GEM_BF(RXBS, buffer_size);
754 if (macb->config->dma_burst_length)
755 dmacfg = GEM_BFINS(FBLDO,
756 macb->config->dma_burst_length, dmacfg);
758 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
759 dmacfg &= ~GEM_BIT(ENDIA_PKT);
761 if (macb->is_big_endian)
762 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
764 dmacfg &= ~GEM_BIT(ENDIA_DESC);
766 dmacfg &= ~GEM_BIT(ADDR64);
767 gem_writel(macb, DMACFG, dmacfg);
771 static int _macb_init(struct udevice *dev, const char *name)
773 static int _macb_init(struct macb_device *macb, const char *name)
777 struct macb_device *macb = dev_get_priv(dev);
784 * macb_halt should have been called at some point before now,
785 * so we'll assume the controller is idle.
788 /* initialize DMA descriptors */
789 paddr = macb->rx_buffer_dma;
790 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
791 if (i == (MACB_RX_RING_SIZE - 1))
792 paddr |= MACB_BIT(RX_WRAP);
793 macb->rx_ring[i].addr = paddr;
794 macb->rx_ring[i].ctrl = 0;
795 paddr += macb->rx_buffer_size;
797 macb_flush_ring_desc(macb, RX);
798 macb_flush_rx_buffer(macb);
800 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
801 macb->tx_ring[i].addr = 0;
802 if (i == (MACB_TX_RING_SIZE - 1))
803 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
806 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
808 macb_flush_ring_desc(macb, TX);
813 macb->next_rx_tail = 0;
815 #ifdef CONFIG_MACB_ZYNQ
816 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
819 macb_writel(macb, RBQP, macb->rx_ring_dma);
820 macb_writel(macb, TBQP, macb->tx_ring_dma);
822 if (macb_is_gem(macb)) {
823 /* Initialize DMA properties */
824 gmac_configure_dma(macb);
825 /* Check the multi queue and initialize the queue for tx */
826 gmac_init_multi_queues(macb);
829 * When the GMAC IP with GE feature, this bit is used to
830 * select interface between RGMII and GMII.
831 * When the GMAC IP without GE feature, this bit is used
832 * to select interface between RMII and MII.
835 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
836 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
837 gem_writel(macb, USRIO, GEM_BIT(RGMII));
839 gem_writel(macb, USRIO, 0);
841 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
842 unsigned int ncfgr = macb_readl(macb, NCFGR);
844 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
845 macb_writel(macb, NCFGR, ncfgr);
848 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
849 gem_writel(macb, USRIO, GEM_BIT(RGMII));
851 gem_writel(macb, USRIO, 0);
855 /* choose RMII or MII mode. This depends on the board */
857 #ifdef CONFIG_AT91FAMILY
858 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
859 macb_writel(macb, USRIO,
860 MACB_BIT(RMII) | MACB_BIT(CLKEN));
862 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
865 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
866 macb_writel(macb, USRIO, 0);
868 macb_writel(macb, USRIO, MACB_BIT(MII));
872 #ifdef CONFIG_AT91FAMILY
873 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
875 macb_writel(macb, USRIO, 0);
878 #ifdef CONFIG_AT91FAMILY
879 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
881 macb_writel(macb, USRIO, MACB_BIT(MII));
883 #endif /* CONFIG_RMII */
888 ret = macb_phy_init(dev, name);
890 ret = macb_phy_init(macb, name);
895 /* Enable TX and RX */
896 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
901 static void _macb_halt(struct macb_device *macb)
905 /* Halt the controller and wait for any ongoing transmission to end. */
906 ncr = macb_readl(macb, NCR);
907 ncr |= MACB_BIT(THALT);
908 macb_writel(macb, NCR, ncr);
911 tsr = macb_readl(macb, TSR);
912 } while (tsr & MACB_BIT(TGO));
914 /* Disable TX and RX, and clear statistics */
915 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
918 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
923 /* set hardware address */
924 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
925 enetaddr[2] << 16 | enetaddr[3] << 24;
926 macb_writel(macb, SA1B, hwaddr_bottom);
927 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
928 macb_writel(macb, SA1T, hwaddr_top);
932 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
935 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
936 unsigned long macb_hz = macb->pclk_rate;
938 unsigned long macb_hz = get_macb_pclk_rate(id);
941 if (macb_hz < 20000000)
942 config = MACB_BF(CLK, MACB_CLK_DIV8);
943 else if (macb_hz < 40000000)
944 config = MACB_BF(CLK, MACB_CLK_DIV16);
945 else if (macb_hz < 80000000)
946 config = MACB_BF(CLK, MACB_CLK_DIV32);
948 config = MACB_BF(CLK, MACB_CLK_DIV64);
953 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
957 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
958 unsigned long macb_hz = macb->pclk_rate;
960 unsigned long macb_hz = get_macb_pclk_rate(id);
963 if (macb_hz < 20000000)
964 config = GEM_BF(CLK, GEM_CLK_DIV8);
965 else if (macb_hz < 40000000)
966 config = GEM_BF(CLK, GEM_CLK_DIV16);
967 else if (macb_hz < 80000000)
968 config = GEM_BF(CLK, GEM_CLK_DIV32);
969 else if (macb_hz < 120000000)
970 config = GEM_BF(CLK, GEM_CLK_DIV48);
971 else if (macb_hz < 160000000)
972 config = GEM_BF(CLK, GEM_CLK_DIV64);
973 else if (macb_hz < 240000000)
974 config = GEM_BF(CLK, GEM_CLK_DIV96);
975 else if (macb_hz < 320000000)
976 config = GEM_BF(CLK, GEM_CLK_DIV128);
978 config = GEM_BF(CLK, GEM_CLK_DIV224);
984 * Get the DMA bus width field of the network configuration register that we
985 * should program. We find the width from decoding the design configuration
986 * register to find the maximum supported data bus width.
988 static u32 macb_dbw(struct macb_device *macb)
990 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
992 return GEM_BF(DBW, GEM_DBW128);
994 return GEM_BF(DBW, GEM_DBW64);
997 return GEM_BF(DBW, GEM_DBW32);
1001 static void _macb_eth_initialize(struct macb_device *macb)
1003 int id = 0; /* This is not used by functions we call */
1006 if (macb_is_gem(macb))
1007 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1009 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1011 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
1012 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1014 &macb->rx_buffer_dma);
1015 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
1016 &macb->rx_ring_dma);
1017 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
1018 &macb->tx_ring_dma);
1019 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1020 &macb->dummy_desc_dma);
1023 * Do some basic initialization so that we at least can talk
1026 if (macb_is_gem(macb)) {
1027 ncfgr = gem_mdc_clk_div(id, macb);
1028 ncfgr |= macb_dbw(macb);
1030 ncfgr = macb_mdc_clk_div(id, macb);
1033 macb_writel(macb, NCFGR, ncfgr);
1036 #ifndef CONFIG_DM_ETH
1037 static int macb_send(struct eth_device *netdev, void *packet, int length)
1039 struct macb_device *macb = to_macb(netdev);
1041 return _macb_send(macb, netdev->name, packet, length);
1044 static int macb_recv(struct eth_device *netdev)
1046 struct macb_device *macb = to_macb(netdev);
1050 macb->wrapped = false;
1052 macb->next_rx_tail = macb->rx_tail;
1053 length = _macb_recv(macb, &packet);
1055 net_process_received_packet(packet, length);
1056 reclaim_rx_buffers(macb, macb->next_rx_tail);
1063 static int macb_init(struct eth_device *netdev, bd_t *bd)
1065 struct macb_device *macb = to_macb(netdev);
1067 return _macb_init(macb, netdev->name);
1070 static void macb_halt(struct eth_device *netdev)
1072 struct macb_device *macb = to_macb(netdev);
1074 return _macb_halt(macb);
1077 static int macb_write_hwaddr(struct eth_device *netdev)
1079 struct macb_device *macb = to_macb(netdev);
1081 return _macb_write_hwaddr(macb, netdev->enetaddr);
1084 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1086 struct macb_device *macb;
1087 struct eth_device *netdev;
1089 macb = malloc(sizeof(struct macb_device));
1091 printf("Error: Failed to allocate memory for MACB%d\n", id);
1094 memset(macb, 0, sizeof(struct macb_device));
1096 netdev = &macb->netdev;
1099 macb->phy_addr = phy_addr;
1101 if (macb_is_gem(macb))
1102 sprintf(netdev->name, "gmac%d", id);
1104 sprintf(netdev->name, "macb%d", id);
1106 netdev->init = macb_init;
1107 netdev->halt = macb_halt;
1108 netdev->send = macb_send;
1109 netdev->recv = macb_recv;
1110 netdev->write_hwaddr = macb_write_hwaddr;
1112 _macb_eth_initialize(macb);
1114 eth_register(netdev);
1116 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1118 struct mii_dev *mdiodev = mdio_alloc();
1121 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1122 mdiodev->read = macb_miiphy_read;
1123 mdiodev->write = macb_miiphy_write;
1125 retval = mdio_register(mdiodev);
1128 macb->bus = miiphy_get_dev_by_name(netdev->name);
1132 #endif /* !CONFIG_DM_ETH */
1134 #ifdef CONFIG_DM_ETH
1136 static int macb_start(struct udevice *dev)
1138 return _macb_init(dev, dev->name);
1141 static int macb_send(struct udevice *dev, void *packet, int length)
1143 struct macb_device *macb = dev_get_priv(dev);
1145 return _macb_send(macb, dev->name, packet, length);
1148 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1150 struct macb_device *macb = dev_get_priv(dev);
1152 macb->next_rx_tail = macb->rx_tail;
1153 macb->wrapped = false;
1155 return _macb_recv(macb, packetp);
1158 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1160 struct macb_device *macb = dev_get_priv(dev);
1162 reclaim_rx_buffers(macb, macb->next_rx_tail);
1167 static void macb_stop(struct udevice *dev)
1169 struct macb_device *macb = dev_get_priv(dev);
1174 static int macb_write_hwaddr(struct udevice *dev)
1176 struct eth_pdata *plat = dev_get_platdata(dev);
1177 struct macb_device *macb = dev_get_priv(dev);
1179 return _macb_write_hwaddr(macb, plat->enetaddr);
1182 static const struct eth_ops macb_eth_ops = {
1183 .start = macb_start,
1187 .free_pkt = macb_free_pkt,
1188 .write_hwaddr = macb_write_hwaddr,
1192 static int macb_enable_clk(struct udevice *dev)
1194 struct macb_device *macb = dev_get_priv(dev);
1199 ret = clk_get_by_index(dev, 0, &clk);
1204 * If clock driver didn't support enable or disable then
1205 * we get -ENOSYS from clk_enable(). To handle this, we
1206 * don't fail for ret == -ENOSYS.
1208 ret = clk_enable(&clk);
1209 if (ret && ret != -ENOSYS)
1212 clk_rate = clk_get_rate(&clk);
1216 macb->pclk_rate = clk_rate;
1222 static const struct macb_config default_gem_config = {
1223 .dma_burst_length = 16,
1227 static int macb_eth_probe(struct udevice *dev)
1229 struct eth_pdata *pdata = dev_get_platdata(dev);
1230 struct macb_device *macb = dev_get_priv(dev);
1231 const char *phy_mode;
1234 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1237 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1238 if (macb->phy_interface == -1) {
1239 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1243 macb->regs = (void *)pdata->iobase;
1245 macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
1247 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1249 macb->config = &default_gem_config;
1252 ret = macb_enable_clk(dev);
1257 _macb_eth_initialize(macb);
1259 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1260 macb->bus = mdio_alloc();
1263 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1264 macb->bus->read = macb_miiphy_read;
1265 macb->bus->write = macb_miiphy_write;
1267 ret = mdio_register(macb->bus);
1270 macb->bus = miiphy_get_dev_by_name(dev->name);
1276 static int macb_eth_remove(struct udevice *dev)
1278 struct macb_device *macb = dev_get_priv(dev);
1280 #ifdef CONFIG_PHYLIB
1283 mdio_unregister(macb->bus);
1284 mdio_free(macb->bus);
1290 * macb_late_eth_ofdata_to_platdata
1291 * @dev: udevice struct
1292 * Returns 0 when operation success and negative errno number
1293 * when operation failed.
1295 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1300 static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1302 struct eth_pdata *pdata = dev_get_platdata(dev);
1304 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1308 return macb_late_eth_ofdata_to_platdata(dev);
1311 static const struct macb_config sama5d4_config = {
1312 .dma_burst_length = 4,
1316 static const struct macb_config sifive_config = {
1317 .dma_burst_length = 16,
1318 .clk_init = macb_sifive_clk_init,
1321 static const struct udevice_id macb_eth_ids[] = {
1322 { .compatible = "cdns,macb" },
1323 { .compatible = "cdns,at91sam9260-macb" },
1324 { .compatible = "cdns,sam9x60-macb" },
1325 { .compatible = "atmel,sama5d2-gem" },
1326 { .compatible = "atmel,sama5d3-gem" },
1327 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1328 { .compatible = "cdns,zynq-gem" },
1329 { .compatible = "sifive,fu540-c000-gem",
1330 .data = (ulong)&sifive_config },
1334 U_BOOT_DRIVER(eth_macb) = {
1337 .of_match = macb_eth_ids,
1338 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1339 .probe = macb_eth_probe,
1340 .remove = macb_eth_remove,
1341 .ops = &macb_eth_ops,
1342 .priv_auto_alloc_size = sizeof(struct macb_device),
1343 .platdata_auto_alloc_size = sizeof(struct eth_pdata),