1 // SPDX-License-Identifier: GPL-2.0+
3 * LPC32xx Ethernet MAC interface driver
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
15 #include <linux/errno.h>
16 #include <asm/types.h>
17 #include <asm/system.h>
18 #include <asm/byteorder.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/config.h>
25 * 1. Unless specified otherwise, all references to tables or paragraphs
26 * are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
28 * 2. Only bitfield masks/values which are actually used by the driver
32 /* a single RX descriptor. The controller has an array of these */
33 struct lpc32xx_eth_rxdesc {
34 u32 packet; /* Receive packet pointer */
35 u32 control; /* Descriptor command status */
38 #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
40 /* RX control bitfields/masks (see Table 330) */
41 #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
42 #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
43 #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
45 /* a single RX status. The controller has an array of these */
46 struct lpc32xx_eth_rxstat {
47 u32 statusinfo; /* Transmit Descriptor status */
48 u32 statushashcrc; /* Transmit Descriptor CRCs */
51 #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
53 /* RX statusinfo bitfields/masks (see Table 333) */
54 #define RX_STAT_RXSIZE 0x000007FF
55 /* Helper: OR of all errors except RANGE */
56 #define RX_STAT_ERRORS 0x1B800000
58 /* a single TX descriptor. The controller has an array of these */
59 struct lpc32xx_eth_txdesc {
60 u32 packet; /* Transmit packet pointer */
61 u32 control; /* Descriptor control */
64 #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
66 /* TX control bitfields/masks (see Table 335) */
67 #define TX_CTRL_TXSIZE 0x000007FF
68 #define TX_CTRL_LAST 0x40000000
70 /* a single TX status. The controller has an array of these */
71 struct lpc32xx_eth_txstat {
72 u32 statusinfo; /* Transmit Descriptor status */
75 #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
77 /* Ethernet MAC interface registers (see Table 283) */
78 struct lpc32xx_eth_registers {
79 /* MAC registers - 0x3106_0000 to 0x3106_01FC */
80 u32 mac1; /* MAC configuration register 1 */
81 u32 mac2; /* MAC configuration register 2 */
82 u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
83 u32 ipgr; /* Non-back-to-back IPG register */
84 u32 clrt; /* Collision Window / Retry register */
85 u32 maxf; /* Maximum Frame register */
86 u32 supp; /* Phy Support register */
88 u32 mcfg; /* MII management configuration reg. */
89 u32 mcmd; /* MII management command register */
90 u32 madr; /* MII management address register */
91 u32 mwtd; /* MII management wite data register */
92 u32 mrdd; /* MII management read data register */
93 u32 mind; /* MII management indicators register */
95 u32 sa0; /* Station address register 0 */
96 u32 sa1; /* Station address register 1 */
97 u32 sa2; /* Station address register 2 */
99 /* Control registers */
104 u32 rxdescriptornumber; /* actually, number MINUS ONE */
105 u32 rxproduceindex; /* head of rx desc fifo */
106 u32 rxconsumeindex; /* tail of rx desc fifo */
109 u32 txdescriptornumber; /* actually, number MINUS ONE */
110 u32 txproduceindex; /* head of rx desc fifo */
111 u32 txconsumeindex; /* tail of rx desc fifo */
113 u32 tsv0; /* Transmit status vector register 0 */
114 u32 tsv1; /* Transmit status vector register 1 */
115 u32 rsv; /* Receive status vector register */
117 u32 flowcontrolcounter;
118 u32 flowcontrolstatus;
120 /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
122 u32 rxfilterwolstatus;
123 u32 rxfilterwolclear;
128 /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
129 u32 intstatus; /* Interrupt status register */
138 /* MAC1 register bitfields/masks and offsets (see Table 283) */
139 #define MAC1_RECV_ENABLE 0x00000001
140 #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
141 #define MAC1_SOFT_RESET 0x00008000
142 /* Helper: general reset */
143 #define MAC1_RESETS 0x0000CF00
145 /* MAC2 register bitfields/masks and offsets (see Table 284) */
146 #define MAC2_FULL_DUPLEX 0x00000001
147 #define MAC2_CRC_ENABLE 0x00000010
148 #define MAC2_PAD_CRC_ENABLE 0x00000020
150 /* SUPP register bitfields/masks and offsets (see Table 290) */
151 #define SUPP_SPEED 0x00000100
153 /* MCFG register bitfields/masks and offsets (see Table 292) */
154 #define MCFG_RESET_MII_MGMT 0x00008000
155 /* divide clock by 28 (see Table 293) */
156 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
158 /* MADR register bitfields/masks and offsets (see Table 295) */
159 #define MADR_REG_MASK 0x0000001F
160 #define MADR_PHY_MASK 0x00001F00
161 #define MADR_REG_OFFSET 0
162 #define MADR_PHY_OFFSET 8
164 /* MIND register bitfields/masks (see Table 298) */
165 #define MIND_BUSY 0x00000001
167 /* COMMAND register bitfields/masks and offsets (see Table 283) */
168 #define COMMAND_RXENABLE 0x00000001
169 #define COMMAND_TXENABLE 0x00000002
170 #define COMMAND_PASSRUNTFRAME 0x00000040
171 #define COMMAND_RMII 0x00000200
172 #define COMMAND_FULL_DUPLEX 0x00000400
173 /* Helper: general reset */
174 #define COMMAND_RESETS 0x00000038
176 /* STATUS register bitfields/masks and offsets (see Table 283) */
177 #define STATUS_RXSTATUS 0x00000001
178 #define STATUS_TXSTATUS 0x00000002
180 /* RXFILTERCTRL register bitfields/masks (see Table 319) */
181 #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
182 #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
184 /* Buffers and descriptors */
186 #define ATTRS(n) __aligned(n)
188 #define TX_BUF_COUNT 4
189 #define RX_BUF_COUNT 4
191 struct lpc32xx_eth_buffers {
192 ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
193 ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
194 ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
195 ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
196 ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
197 ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
200 /* port device data struct */
201 struct lpc32xx_eth_device {
202 struct eth_device dev;
203 struct lpc32xx_eth_registers *regs;
204 struct lpc32xx_eth_buffers *bufs;
208 #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
211 #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
213 /* timeout for MII polling */
214 #define MII_TIMEOUT 10000000
216 /* limits for PHY and register addresses */
217 #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
219 #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
221 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
223 * mii_reg_read - miiphy_read callback function.
225 * Returns 16bit phy register value, or 0xffff on error
227 static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad,
231 struct eth_device *dev = eth_get_dev_by_name(bus->name);
232 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
233 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
237 /* check parameters */
238 if (phy_adr > MII_MAX_PHY) {
239 printf("%s:%u: Invalid PHY address %d\n",
240 __func__, __LINE__, phy_adr);
243 if (reg_ofs > MII_MAX_REG) {
244 printf("%s:%u: Invalid register offset %d\n",
245 __func__, __LINE__, reg_ofs);
249 /* write the phy and reg addressse into the MII address reg */
250 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
253 /* write 1 to the MII command register to cause a read */
254 writel(1, ®s->mcmd);
256 /* wait till the MII is not busy */
257 timeout = MII_TIMEOUT;
259 /* read MII indicators register */
260 mind_reg = readl(®s->mind);
263 } while (mind_reg & MIND_BUSY);
265 /* write 0 to the MII command register to finish the read */
266 writel(0, ®s->mcmd);
269 printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
273 data = (u16) readl(®s->mrdd);
275 debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
282 * mii_reg_write - imiiphy_write callback function.
284 * Returns 0 if write succeed, -EINVAL on bad parameters
287 static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
288 int reg_ofs, u16 data)
290 struct eth_device *dev = eth_get_dev_by_name(bus->name);
291 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
292 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
296 /* check parameters */
297 if (phy_adr > MII_MAX_PHY) {
298 printf("%s:%u: Invalid PHY address %d\n",
299 __func__, __LINE__, phy_adr);
302 if (reg_ofs > MII_MAX_REG) {
303 printf("%s:%u: Invalid register offset %d\n",
304 __func__, __LINE__, reg_ofs);
308 /* write the phy and reg addressse into the MII address reg */
309 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
312 /* write data to the MII write register */
313 writel(data, ®s->mwtd);
315 /* wait till the MII is not busy */
316 timeout = MII_TIMEOUT;
318 /* read MII indicators register */
319 mind_reg = readl(®s->mind);
322 } while (mind_reg & MIND_BUSY);
325 printf("%s:%u: MII busy timeout\n", __func__,
330 /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
338 * Provide default Ethernet buffers base address if target did not.
339 * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
340 * maximize throughput.
342 #if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
343 #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
346 static struct lpc32xx_eth_device lpc32xx_eth = {
347 .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
348 .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
349 #if defined(CONFIG_RMII)
354 #define TX_TIMEOUT 10000
356 static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
358 struct lpc32xx_eth_device *lpc32xx_eth_device =
359 container_of(dev, struct lpc32xx_eth_device, dev);
360 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
361 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
362 int timeout, tx_index;
364 /* time out if transmit descriptor array remains full too long */
365 timeout = TX_TIMEOUT;
366 while ((readl(®s->status) & STATUS_TXSTATUS) &&
367 (readl(®s->txconsumeindex)
368 == readl(®s->txproduceindex))) {
373 /* determine next transmit packet index to use */
374 tx_index = readl(®s->txproduceindex);
376 /* set up transmit packet */
377 memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN],
378 (void *)dataptr, datasize);
379 writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
380 &bufs->tx_desc[tx_index].control);
381 writel(0, &bufs->tx_stat[tx_index].statusinfo);
383 /* pass transmit packet to DMA engine */
384 tx_index = (tx_index + 1) % TX_BUF_COUNT;
385 writel(tx_index, ®s->txproduceindex);
387 /* transmission succeeded */
391 #define RX_TIMEOUT 1000000
393 static int lpc32xx_eth_recv(struct eth_device *dev)
395 struct lpc32xx_eth_device *lpc32xx_eth_device =
396 container_of(dev, struct lpc32xx_eth_device, dev);
397 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
398 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
399 int timeout, rx_index;
401 /* time out if receive descriptor array remains empty too long */
402 timeout = RX_TIMEOUT;
403 while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) {
408 /* determine next receive packet index to use */
409 rx_index = readl(®s->rxconsumeindex);
411 /* if data was valid, pass it on */
412 if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
413 net_process_received_packet(
414 &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
415 (bufs->rx_stat[rx_index].statusinfo
416 & RX_STAT_RXSIZE) + 1);
419 /* pass receive slot back to DMA engine */
420 rx_index = (rx_index + 1) % RX_BUF_COUNT;
421 writel(rx_index, ®s->rxconsumeindex);
423 /* reception successful */
427 static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
429 struct lpc32xx_eth_device *lpc32xx_eth_device =
430 container_of(dev, struct lpc32xx_eth_device, dev);
431 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
433 /* Save station address */
434 writel((unsigned long) (dev->enetaddr[0] |
435 (dev->enetaddr[1] << 8)), ®s->sa2);
436 writel((unsigned long) (dev->enetaddr[2] |
437 (dev->enetaddr[3] << 8)), ®s->sa1);
438 writel((unsigned long) (dev->enetaddr[4] |
439 (dev->enetaddr[5] << 8)), ®s->sa0);
444 static int lpc32xx_eth_init(struct eth_device *dev)
446 struct lpc32xx_eth_device *lpc32xx_eth_device =
447 container_of(dev, struct lpc32xx_eth_device, dev);
448 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
449 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
452 /* Initial MAC initialization */
453 writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1);
454 writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2);
455 writel(PKTSIZE_ALIGN, ®s->maxf);
457 /* Retries: 15 (0xF). Collision window: 57 (0x37). */
458 writel(0x370F, ®s->clrt);
460 /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
461 writel(0x0012, ®s->ipgr);
463 /* pass runt (smaller than 64 bytes) frames */
464 if (lpc32xx_eth_device->phy_rmii)
465 writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command);
467 writel(COMMAND_PASSRUNTFRAME, ®s->command);
469 /* Configure Full/Half Duplex mode */
470 if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
471 setbits_le32(®s->mac2, MAC2_FULL_DUPLEX);
472 setbits_le32(®s->command, COMMAND_FULL_DUPLEX);
473 writel(0x15, ®s->ipgt);
475 writel(0x12, ®s->ipgt);
478 /* Configure 100MBit/10MBit mode */
479 if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
480 writel(SUPP_SPEED, ®s->supp);
482 writel(0, ®s->supp);
484 /* Save station address */
485 writel((unsigned long) (dev->enetaddr[0] |
486 (dev->enetaddr[1] << 8)), ®s->sa2);
487 writel((unsigned long) (dev->enetaddr[2] |
488 (dev->enetaddr[3] << 8)), ®s->sa1);
489 writel((unsigned long) (dev->enetaddr[4] |
490 (dev->enetaddr[5] << 8)), ®s->sa0);
492 /* set up transmit buffers */
493 for (index = 0; index < TX_BUF_COUNT; index++) {
494 bufs->tx_desc[index].control = 0;
495 bufs->tx_stat[index].statusinfo = 0;
497 writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor);
498 writel((u32)(&bufs->tx_stat), ®s->txstatus);
499 writel(TX_BUF_COUNT-1, ®s->txdescriptornumber);
501 /* set up receive buffers */
502 for (index = 0; index < RX_BUF_COUNT; index++) {
503 bufs->rx_desc[index].packet =
504 (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
505 bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
506 bufs->rx_stat[index].statusinfo = 0;
507 bufs->rx_stat[index].statushashcrc = 0;
509 writel((u32)(&bufs->rx_desc), ®s->rxdescriptor);
510 writel((u32)(&bufs->rx_stat), ®s->rxstatus);
511 writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber);
513 /* set up transmit buffers */
514 for (index = 0; index < TX_BUF_COUNT; index++)
515 bufs->tx_desc[index].packet =
516 (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN);
518 /* Enable broadcast and matching address packets */
519 writel(RXFILTERCTRL_ACCEPTBROADCAST |
520 RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl);
522 /* Clear and disable interrupts */
523 writel(0xFFFF, ®s->intclear);
524 writel(0, ®s->intenable);
526 /* Enable receive and transmit mode of MAC ethernet core */
527 setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
528 setbits_le32(®s->mac1, MAC1_RECV_ENABLE);
531 * Perform a 'dummy' first send to work around Ethernet.1
532 * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
533 * Use zeroed "index" variable as the dummy.
537 lpc32xx_eth_send(dev, &index, 4);
542 static int lpc32xx_eth_halt(struct eth_device *dev)
544 struct lpc32xx_eth_device *lpc32xx_eth_device =
545 container_of(dev, struct lpc32xx_eth_device, dev);
546 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
548 /* Reset all MAC logic */
549 writel(MAC1_RESETS, ®s->mac1);
550 writel(COMMAND_RESETS, ®s->command);
551 /* Let reset condition settle */
557 #if defined(CONFIG_PHYLIB)
558 int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
560 struct lpc32xx_eth_device *lpc32xx_eth_device =
561 container_of(dev, struct lpc32xx_eth_device, dev);
563 struct phy_device *phydev;
568 printf("mdio_alloc failed\n");
571 bus->read = mii_reg_read;
572 bus->write = mii_reg_write;
573 strcpy(bus->name, dev->name);
575 ret = mdio_register(bus);
577 printf("mdio_register failed\n");
582 if (lpc32xx_eth_device->phy_rmii)
583 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
585 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
588 printf("phy_connect failed\n");
599 int lpc32xx_eth_initialize(bd_t *bis)
601 struct eth_device *dev = &lpc32xx_eth.dev;
602 struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
605 * Set RMII management clock rate. With HCLK at 104 MHz and
606 * a divider of 28, this will be 3.72 MHz.
608 writel(MCFG_RESET_MII_MGMT, ®s->mcfg);
609 writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg);
611 /* Reset all MAC logic */
612 writel(MAC1_RESETS, ®s->mac1);
613 writel(COMMAND_RESETS, ®s->command);
615 /* wait 10 ms for the whole I/F to reset */
618 /* must be less than sizeof(dev->name) */
619 strcpy(dev->name, "eth0");
621 dev->init = (void *)lpc32xx_eth_init;
622 dev->halt = (void *)lpc32xx_eth_halt;
623 dev->send = (void *)lpc32xx_eth_send;
624 dev->recv = (void *)lpc32xx_eth_recv;
625 dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
627 /* Release SOFT reset to let MII talk to PHY */
628 clrbits_le32(®s->mac1, MAC1_SOFT_RESET);
630 /* register driver before talking to phy */
633 #if defined(CONFIG_PHYLIB)
634 lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
635 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
637 struct mii_dev *mdiodev = mdio_alloc();
640 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
641 mdiodev->read = mii_reg_read;
642 mdiodev->write = mii_reg_write;
644 retval = mdio_register(mdiodev);