drivers/net/higmacv300.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019, Linaro Limited
   4  */
   5
   6 #include <cpu_func.h>
   7 #include <log.h>
   8 #include <malloc.h>
   9 #include <asm/cache.h>
  10 #include <asm/io.h>
  11 #include <common.h>
  12 #include <console.h>
  13 #include <linux/bug.h>
  14 #include <linux/mii.h>
  15 #include <miiphy.h>
  16 #include <net.h>
  17 #include <reset.h>
  18 #include <wait_bit.h>
  19
  20 #define STATION_ADDR_LOW                0x0000
  21 #define STATION_ADDR_HIGH               0x0004
  22 #define MAC_DUPLEX_HALF_CTRL            0x0008
  23 #define PORT_MODE                       0x0040
  24 #define PORT_EN                         0x0044
  25 #define BIT_TX_EN                       BIT(2)
  26 #define BIT_RX_EN                       BIT(1)
  27 #define MODE_CHANGE_EN                  0x01b4
  28 #define BIT_MODE_CHANGE_EN              BIT(0)
  29 #define MDIO_SINGLE_CMD                 0x03c0
  30 #define BIT_MDIO_BUSY                   BIT(20)
  31 #define MDIO_READ                       (BIT(17) | BIT_MDIO_BUSY)
  32 #define MDIO_WRITE                      (BIT(16) | BIT_MDIO_BUSY)
  33 #define MDIO_SINGLE_DATA                0x03c4
  34 #define MDIO_RDATA_STATUS               0x03d0
  35 #define BIT_MDIO_RDATA_INVALID          BIT(0)
  36 #define RX_FQ_START_ADDR                0x0500
  37 #define RX_FQ_DEPTH                     0x0504
  38 #define RX_FQ_WR_ADDR                   0x0508
  39 #define RX_FQ_RD_ADDR                   0x050c
  40 #define RX_FQ_REG_EN                    0x0518
  41 #define RX_BQ_START_ADDR                0x0520
  42 #define RX_BQ_DEPTH                     0x0524
  43 #define RX_BQ_WR_ADDR                   0x0528
  44 #define RX_BQ_RD_ADDR                   0x052c
  45 #define RX_BQ_REG_EN                    0x0538
  46 #define TX_BQ_START_ADDR                0x0580
  47 #define TX_BQ_DEPTH                     0x0584
  48 #define TX_BQ_WR_ADDR                   0x0588
  49 #define TX_BQ_RD_ADDR                   0x058c
  50 #define TX_BQ_REG_EN                    0x0598
  51 #define TX_RQ_START_ADDR                0x05a0
  52 #define TX_RQ_DEPTH                     0x05a4
  53 #define TX_RQ_WR_ADDR                   0x05a8
  54 #define TX_RQ_RD_ADDR                   0x05ac
  55 #define TX_RQ_REG_EN                    0x05b8
  56 #define BIT_START_ADDR_EN               BIT(2)
  57 #define BIT_DEPTH_EN                    BIT(1)
  58 #define DESC_WR_RD_ENA                  0x05cc
  59 #define BIT_RX_OUTCFF_WR                BIT(3)
  60 #define BIT_RX_CFF_RD                   BIT(2)
  61 #define BIT_TX_OUTCFF_WR                BIT(1)
  62 #define BIT_TX_CFF_RD                   BIT(0)
  63 #define BITS_DESC_ENA                   (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
  64                                          BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
  65
  66 /* MACIF_CTRL */
  67 #define RGMII_SPEED_1000                0x2c
  68 #define RGMII_SPEED_100                 0x2f
  69 #define RGMII_SPEED_10                  0x2d
  70 #define MII_SPEED_100                   0x0f
  71 #define MII_SPEED_10                    0x0d
  72 #define GMAC_SPEED_1000                 0x05
  73 #define GMAC_SPEED_100                  0x01
  74 #define GMAC_SPEED_10                   0x00
  75 #define GMAC_FULL_DUPLEX                BIT(4)
  76
  77 #define RX_DESC_NUM                     64
  78 #define TX_DESC_NUM                     2
  79 #define DESC_SIZE                       32
  80 #define DESC_WORD_SHIFT                 3
  81 #define DESC_BYTE_SHIFT                 5
  82 #define DESC_CNT(n)                     ((n) >> DESC_BYTE_SHIFT)
  83 #define DESC_BYTE(n)                    ((n) << DESC_BYTE_SHIFT)
  84 #define DESC_VLD_FREE                   0
  85 #define DESC_VLD_BUSY                   1
  86
  87 #define MAC_MAX_FRAME_SIZE              1600
  88
  89 enum higmac_queue {
  90         RX_FQ,
  91         RX_BQ,
  92         TX_BQ,
  93         TX_RQ,
  94 };
  95
  96 struct higmac_desc {
  97         unsigned int buf_addr;
  98         unsigned int buf_len:11;
  99         unsigned int reserve0:5;
 100         unsigned int data_len:11;
 101         unsigned int reserve1:2;
 102         unsigned int fl:2;
 103         unsigned int descvid:1;
 104         unsigned int reserve2[6];
 105 };
 106
 107 struct higmac_priv {
 108         void __iomem *base;
 109         void __iomem *macif_ctrl;
 110         struct reset_ctl rst_phy;
 111         struct higmac_desc *rxfq;
 112         struct higmac_desc *rxbq;
 113         struct higmac_desc *txbq;
 114         struct higmac_desc *txrq;
 115         int rxdesc_in_use;
 116         struct mii_dev *bus;
 117         struct phy_device *phydev;
 118         int phyintf;
 119         int phyaddr;
 120 };
 121
 122 #define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
 123 #define invalidate_desc(d) \
 124         invalidate_dcache_range((unsigned long)(d), \
 125                                 (unsigned long)(d) + sizeof(*(d)))
 126
 127 static int higmac_write_hwaddr(struct udevice *dev)
 128 {
 129         struct eth_pdata *pdata = dev_get_platdata(dev);
 130         struct higmac_priv *priv = dev_get_priv(dev);
 131         unsigned char *mac = pdata->enetaddr;
 132         u32 val;
 133
 134         val = mac[1] | (mac[0] << 8);
 135         writel(val, priv->base + STATION_ADDR_HIGH);
 136
 137         val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
 138         writel(val, priv->base + STATION_ADDR_LOW);
 139
 140         return 0;
 141 }
 142
 143 static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
 144 {
 145         struct higmac_priv *priv = dev_get_priv(dev);
 146
 147         /* Inform GMAC that the RX descriptor is no longer in use */
 148         writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
 149
 150         return 0;
 151 }
 152
 153 static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
 154 {
 155         struct higmac_priv *priv = dev_get_priv(dev);
 156         struct higmac_desc *fqd = priv->rxfq;
 157         struct higmac_desc *bqd = priv->rxbq;
 158         int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
 159         int timeout = 100000;
 160         int len = 0;
 161         int space;
 162         int i;
 163
 164         fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
 165         fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
 166
 167         if (fqw_pos >= fqr_pos)
 168                 space = RX_DESC_NUM - (fqw_pos - fqr_pos);
 169         else
 170                 space = fqr_pos - fqw_pos;
 171
 172         /* Leave one free to distinguish full filled from empty buffer */
 173         for (i = 0; i < space - 1; i++) {
 174                 fqd = priv->rxfq + fqw_pos;
 175                 invalidate_dcache_range(fqd->buf_addr,
 176                                         fqd->buf_addr + MAC_MAX_FRAME_SIZE);
 177
 178                 if (++fqw_pos >= RX_DESC_NUM)
 179                         fqw_pos = 0;
 180
 181                 writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
 182         }
 183
 184         bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
 185         bqd += bqr_pos;
 186         /* BQ is only ever written by GMAC */
 187         invalidate_desc(bqd);
 188
 189         do {
 190                 bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
 191                 udelay(1);
 192         } while (--timeout && bqw_pos == bqr_pos);
 193
 194         if (!timeout)
 195                 return -ETIMEDOUT;
 196
 197         if (++bqr_pos >= RX_DESC_NUM)
 198                 bqr_pos = 0;
 199
 200         len = bqd->data_len;
 201
 202         /* CPU should not have touched this buffer since we added it to FQ */
 203         invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
 204         *packetp = (void *)(unsigned long)bqd->buf_addr;
 205
 206         /* Record the RX_BQ descriptor that is holding RX data */
 207         priv->rxdesc_in_use = bqr_pos;
 208
 209         return len;
 210 }
 211
 212 static int higmac_send(struct udevice *dev, void *packet, int length)
 213 {
 214         struct higmac_priv *priv = dev_get_priv(dev);
 215         struct higmac_desc *bqd = priv->txbq;
 216         int bqw_pos, rqw_pos, rqr_pos;
 217         int timeout = 1000;
 218
 219         flush_cache((unsigned long)packet, length);
 220
 221         bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
 222         bqd += bqw_pos;
 223         bqd->buf_addr = (unsigned long)packet;
 224         bqd->descvid = DESC_VLD_BUSY;
 225         bqd->data_len = length;
 226         flush_desc(bqd);
 227
 228         if (++bqw_pos >= TX_DESC_NUM)
 229                 bqw_pos = 0;
 230
 231         writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
 232
 233         rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
 234         if (++rqr_pos >= TX_DESC_NUM)
 235                 rqr_pos = 0;
 236
 237         do {
 238                 rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
 239                 udelay(1);
 240         } while (--timeout && rqr_pos != rqw_pos);
 241
 242         if (!timeout)
 243                 return -ETIMEDOUT;
 244
 245         writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
 246
 247         return 0;
 248 }
 249
 250 static int higmac_adjust_link(struct higmac_priv *priv)
 251 {
 252         struct phy_device *phydev = priv->phydev;
 253         int interface = priv->phyintf;
 254         u32 val;
 255
 256         switch (interface) {
 257         case PHY_INTERFACE_MODE_RGMII:
 258                 if (phydev->speed == SPEED_1000)
 259                         val = RGMII_SPEED_1000;
 260                 else if (phydev->speed == SPEED_100)
 261                         val = RGMII_SPEED_100;
 262                 else
 263                         val = RGMII_SPEED_10;
 264                 break;
 265         case PHY_INTERFACE_MODE_MII:
 266                 if (phydev->speed == SPEED_100)
 267                         val = MII_SPEED_100;
 268                 else
 269                         val = MII_SPEED_10;
 270                 break;
 271         default:
 272                 debug("unsupported mode: %d\n", interface);
 273                 return -EINVAL;
 274         }
 275
 276         if (phydev->duplex)
 277                 val |= GMAC_FULL_DUPLEX;
 278
 279         writel(val, priv->macif_ctrl);
 280
 281         if (phydev->speed == SPEED_1000)
 282                 val = GMAC_SPEED_1000;
 283         else if (phydev->speed == SPEED_100)
 284                 val = GMAC_SPEED_100;
 285         else
 286                 val = GMAC_SPEED_10;
 287
 288         writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
 289         writel(val, priv->base + PORT_MODE);
 290         writel(0, priv->base + MODE_CHANGE_EN);
 291         writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
 292
 293         return 0;
 294 }
 295
 296 static int higmac_start(struct udevice *dev)
 297 {
 298         struct higmac_priv *priv = dev_get_priv(dev);
 299         struct phy_device *phydev = priv->phydev;
 300         int ret;
 301
 302         ret = phy_startup(phydev);
 303         if (ret)
 304                 return ret;
 305
 306         if (!phydev->link) {
 307                 debug("%s: link down\n", phydev->dev->name);
 308                 return -ENODEV;
 309         }
 310
 311         ret = higmac_adjust_link(priv);
 312         if (ret)
 313                 return ret;
 314
 315         /* Enable port */
 316         writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
 317         writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
 318
 319         return 0;
 320 }
 321
 322 static void higmac_stop(struct udevice *dev)
 323 {
 324         struct higmac_priv *priv = dev_get_priv(dev);
 325
 326         /* Disable port */
 327         writel(0, priv->base + PORT_EN);
 328         writel(0, priv->base + DESC_WR_RD_ENA);
 329 }
 330
 331 static const struct eth_ops higmac_ops = {
 332         .start          = higmac_start,
 333         .send           = higmac_send,
 334         .recv           = higmac_recv,
 335         .free_pkt       = higmac_free_pkt,
 336         .stop           = higmac_stop,
 337         .write_hwaddr   = higmac_write_hwaddr,
 338 };
 339
 340 static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 341 {
 342         struct higmac_priv *priv = bus->priv;
 343         int ret;
 344
 345         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 346                                 false, 1000, false);
 347         if (ret)
 348                 return ret;
 349
 350         writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 351
 352         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 353                                 false, 1000, false);
 354         if (ret)
 355                 return ret;
 356
 357         if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
 358                 return -EINVAL;
 359
 360         return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
 361 }
 362
 363 static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
 364                              int reg, u16 value)
 365 {
 366         struct higmac_priv *priv = bus->priv;
 367         int ret;
 368
 369         ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
 370                                 false, 1000, false);
 371         if (ret)
 372                 return ret;
 373
 374         writel(value, priv->base + MDIO_SINGLE_DATA);
 375         writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
 376
 377         return 0;
 378 }
 379
 380 static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
 381 {
 382         int i;
 383
 384         for (i = 0; i < num; i++) {
 385                 struct higmac_desc *desc = &descs[i];
 386
 387                 desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 388                                                          MAC_MAX_FRAME_SIZE);
 389                 if (!desc->buf_addr)
 390                         goto free_bufs;
 391
 392                 desc->descvid = DESC_VLD_FREE;
 393                 desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
 394                 flush_desc(desc);
 395         }
 396
 397         return 0;
 398
 399 free_bufs:
 400         while (--i > 0)
 401                 free((void *)(unsigned long)descs[i].buf_addr);
 402         return -ENOMEM;
 403 }
 404
 405 static int higmac_init_hw_queue(struct higmac_priv *priv,
 406                                 enum higmac_queue queue)
 407 {
 408         struct higmac_desc *desc, **pdesc;
 409         u32 regaddr, regen, regdep;
 410         int depth;
 411         int len;
 412
 413         switch (queue) {
 414         case RX_FQ:
 415                 regaddr = RX_FQ_START_ADDR;
 416                 regen = RX_FQ_REG_EN;
 417                 regdep = RX_FQ_DEPTH;
 418                 depth = RX_DESC_NUM;
 419                 pdesc = &priv->rxfq;
 420                 break;
 421         case RX_BQ:
 422                 regaddr = RX_BQ_START_ADDR;
 423                 regen = RX_BQ_REG_EN;
 424                 regdep = RX_BQ_DEPTH;
 425                 depth = RX_DESC_NUM;
 426                 pdesc = &priv->rxbq;
 427                 break;
 428         case TX_BQ:
 429                 regaddr = TX_BQ_START_ADDR;
 430                 regen = TX_BQ_REG_EN;
 431                 regdep = TX_BQ_DEPTH;
 432                 depth = TX_DESC_NUM;
 433                 pdesc = &priv->txbq;
 434                 break;
 435         case TX_RQ:
 436                 regaddr = TX_RQ_START_ADDR;
 437                 regen = TX_RQ_REG_EN;
 438                 regdep = TX_RQ_DEPTH;
 439                 depth = TX_DESC_NUM;
 440                 pdesc = &priv->txrq;
 441                 break;
 442         }
 443
 444         /* Enable depth */
 445         writel(BIT_DEPTH_EN, priv->base + regen);
 446         writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
 447         writel(0, priv->base + regen);
 448
 449         len = depth * sizeof(*desc);
 450         desc = memalign(ARCH_DMA_MINALIGN, len);
 451         if (!desc)
 452                 return -ENOMEM;
 453         memset(desc, 0, len);
 454         flush_cache((unsigned long)desc, len);
 455         *pdesc = desc;
 456
 457         /* Set up RX_FQ descriptors */
 458         if (queue == RX_FQ)
 459                 higmac_init_rx_descs(desc, depth);
 460
 461         /* Enable start address */
 462         writel(BIT_START_ADDR_EN, priv->base + regen);
 463         writel((unsigned long)desc, priv->base + regaddr);
 464         writel(0, priv->base + regen);
 465
 466         return 0;
 467 }
 468
 469 static int higmac_hw_init(struct higmac_priv *priv)
 470 {
 471         int ret;
 472
 473         /* Initialize hardware queues */
 474         ret = higmac_init_hw_queue(priv, RX_FQ);
 475         if (ret)
 476                 return ret;
 477
 478         ret = higmac_init_hw_queue(priv, RX_BQ);
 479         if (ret)
 480                 goto free_rx_fq;
 481
 482         ret = higmac_init_hw_queue(priv, TX_BQ);
 483         if (ret)
 484                 goto free_rx_bq;
 485
 486         ret = higmac_init_hw_queue(priv, TX_RQ);
 487         if (ret)
 488                 goto free_tx_bq;
 489
 490         /* Reset phy */
 491         reset_deassert(&priv->rst_phy);
 492         mdelay(10);
 493         reset_assert(&priv->rst_phy);
 494         mdelay(30);
 495         reset_deassert(&priv->rst_phy);
 496         mdelay(30);
 497
 498         return 0;
 499
 500 free_tx_bq:
 501         free(priv->txbq);
 502 free_rx_bq:
 503         free(priv->rxbq);
 504 free_rx_fq:
 505         free(priv->rxfq);
 506         return ret;
 507 }
 508
 509 static int higmac_probe(struct udevice *dev)
 510 {
 511         struct higmac_priv *priv = dev_get_priv(dev);
 512         struct phy_device *phydev;
 513         struct mii_dev *bus;
 514         int ret;
 515
 516         ret = higmac_hw_init(priv);
 517         if (ret)
 518                 return ret;
 519
 520         bus = mdio_alloc();
 521         if (!bus)
 522                 return -ENOMEM;
 523
 524         bus->read = higmac_mdio_read;
 525         bus->write = higmac_mdio_write;
 526         bus->priv = priv;
 527         priv->bus = bus;
 528
 529         ret = mdio_register_seq(bus, dev->seq);
 530         if (ret)
 531                 return ret;
 532
 533         phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
 534         if (!phydev)
 535                 return -ENODEV;
 536
 537         phydev->supported &= PHY_GBIT_FEATURES;
 538         phydev->advertising = phydev->supported;
 539         priv->phydev = phydev;
 540
 541         return phy_config(phydev);
 542 }
 543
 544 static int higmac_remove(struct udevice *dev)
 545 {
 546         struct higmac_priv *priv = dev_get_priv(dev);
 547         int i;
 548
 549         mdio_unregister(priv->bus);
 550         mdio_free(priv->bus);
 551
 552         /* Free RX packet buffers */
 553         for (i = 0; i < RX_DESC_NUM; i++)
 554                 free((void *)(unsigned long)priv->rxfq[i].buf_addr);
 555
 556         return 0;
 557 }
 558
 559 static int higmac_ofdata_to_platdata(struct udevice *dev)
 560 {
 561         struct higmac_priv *priv = dev_get_priv(dev);
 562         int phyintf = PHY_INTERFACE_MODE_NONE;
 563         const char *phy_mode;
 564         ofnode phy_node;
 565
 566         priv->base = dev_remap_addr_index(dev, 0);
 567         priv->macif_ctrl = dev_remap_addr_index(dev, 1);
 568
 569         phy_mode = dev_read_string(dev, "phy-mode");
 570         if (phy_mode)
 571                 phyintf = phy_get_interface_by_name(phy_mode);
 572         if (phyintf == PHY_INTERFACE_MODE_NONE)
 573                 return -ENODEV;
 574         priv->phyintf = phyintf;
 575
 576         phy_node = dev_read_subnode(dev, "phy");
 577         if (!ofnode_valid(phy_node)) {
 578                 debug("failed to find phy node\n");
 579                 return -ENODEV;
 580         }
 581         priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
 582
 583         return reset_get_by_name(dev, "phy", &priv->rst_phy);
 584 }
 585
 586 static const struct udevice_id higmac_ids[] = {
 587         { .compatible = "hisilicon,hi3798cv200-gmac" },
 588         { }
 589 };
 590
 591 U_BOOT_DRIVER(eth_higmac) = {
 592         .name   = "eth_higmac",
 593         .id     = UCLASS_ETH,
 594         .of_match = higmac_ids,
 595         .ofdata_to_platdata = higmac_ofdata_to_platdata,
 596         .probe  = higmac_probe,
 597         .remove = higmac_remove,
 598         .ops    = &higmac_ops,
 599         .priv_auto_alloc_size = sizeof(struct higmac_priv),
 600         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 601 };