1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
21 #include <linux/mii.h>
22 #include <asm/immap.h>
23 #include <asm/fsl_mcdmafec.h>
30 /* Ethernet Transmit and Receive Buffers */
31 #define DBUF_LENGTH 1520
32 #define PKT_MAXBUF_SIZE 1518
33 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
35 /* RxBD bits definitions */
36 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
37 BD_ENET_RX_OV | BD_ENET_RX_TR)
39 DECLARE_GLOBAL_DATA_PTR;
41 static void init_eth_info(struct fec_info_dma *info)
43 /* setup Receive and Transmit buffer descriptor */
44 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
48 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
50 info->rxbd = (cbd_t *)DBUF_LENGTH;
52 info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
53 tmp = (u32)info->rxbd;
55 (cbd_t *)((u32)info->txbd + tmp +
56 (PKTBUFSRX * sizeof(cbd_t)));
57 tmp = (u32)info->txbd;
59 (char *)((u32)info->txbuf + tmp +
60 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
61 tmp = (u32)info->txbuf;
64 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
65 (PKTBUFSRX * sizeof(cbd_t)));
67 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
68 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
70 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
74 printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
76 info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
79 static void fec_halt(struct udevice *dev)
81 struct fec_info_dma *info = dev->priv;
82 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
85 /* issue graceful stop command to the FEC transmitter if necessary */
86 fecp->tcr |= FEC_TCR_GTS;
88 /* wait for graceful stop to register */
89 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
92 /* Disable DMA tasks */
93 MCD_killDma(info->tx_task);
94 MCD_killDma(info->rx_task);
96 /* Disable the Ethernet Controller */
97 fecp->ecr &= ~FEC_ECR_ETHER_EN;
99 /* Clear FIFO status registers */
100 fecp->rfsr &= FIFO_ERRSTAT;
101 fecp->tfsr &= FIFO_ERRSTAT;
103 fecp->frst = 0x01000000;
105 /* Issue a reset command to the FEC chip */
106 fecp->ecr |= FEC_ECR_RESET;
108 /* wait at least 20 clock cycles */
112 printf("Ethernet task stopped\n");
117 static void dbg_fec_regs(struct eth_device *dev)
119 struct fec_info_dma *info = dev->priv;
120 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
123 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
124 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
125 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
126 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
127 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
128 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
129 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
130 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
131 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
132 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
133 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
134 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
135 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
136 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
137 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
138 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
139 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
140 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
141 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
142 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
143 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
144 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
145 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
146 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
147 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
148 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
149 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
150 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
151 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
152 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
153 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
154 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
155 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
156 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
157 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
161 static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
165 if ((dup_spd >> 16) == FULL) {
166 /* Set maximum frame length */
167 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
168 FEC_RCR_PROM | 0x100;
169 fecp->tcr = FEC_TCR_FDEN;
171 /* Half duplex mode */
172 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
173 FEC_RCR_MII_MODE | FEC_RCR_DRT;
174 fecp->tcr &= ~FEC_TCR_FDEN;
177 if ((dup_spd & 0xFFFF) == _100BASET) {
181 bd->bi_ethspeed = 100;
186 bd->bi_ethspeed = 10;
190 static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
192 u8 curr_byte; /* byte for which to compute the CRC */
193 int byte; /* loop - counter */
194 int bit; /* loop - counter */
195 u32 crc = 0xffffffff; /* initial value */
197 for (byte = 0; byte < 6; byte++) {
198 curr_byte = mac[byte];
199 for (bit = 0; bit < 8; bit++) {
200 if ((curr_byte & 0x01) ^ (crc & 0x01)) {
202 crc = crc ^ 0xedb88320;
212 /* Set individual hash table register */
214 fecp->ialr = (1 << (crc - 32));
218 fecp->iaur = (1 << crc);
221 /* Set physical address */
222 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
223 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
225 /* Clear multicast address hash table */
230 static int fec_init(struct udevice *dev)
232 struct fec_info_dma *info = dev->priv;
233 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
238 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
241 fecpin_setclear(info, 1);
244 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
245 defined (CONFIG_SYS_DISCOVER_PHY)
248 set_fec_duplex_speed(fecp, info->dup_spd);
250 #ifndef CONFIG_SYS_DISCOVER_PHY
251 set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
252 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
253 #endif /* CONFIG_CMD_MII || CONFIG_MII */
255 /* We use strictly polling mode only */
258 /* Clear any pending interrupt */
259 fecp->eir = 0xffffffff;
261 /* Set station address */
262 if (info->index == 0)
263 rval = eth_env_get_enetaddr("ethaddr", enetaddr);
265 rval = eth_env_get_enetaddr("eth1addr", enetaddr);
268 puts("Please set a valid MAC address\n");
272 fec_set_hwaddr(fecp, enetaddr);
274 /* Set Opcode/Pause Duration Register */
275 fecp->opd = 0x00010020;
277 /* Setup Buffers and Buffer Descriptors */
281 /* Setup Receiver Buffer Descriptors (13.14.24.18)
282 * Settings: Empty, Wrap */
283 for (i = 0; i < PKTBUFSRX; i++) {
284 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
285 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
286 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
288 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
290 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
291 * Settings: Last, Tx CRC */
292 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
293 info->txbd[i].cbd_sc = 0;
294 info->txbd[i].cbd_datlen = 0;
295 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
297 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
299 info->used_tbd_idx = 0;
300 info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
302 /* Set Rx FIFO alarm and granularity value */
303 fecp->rfcr = 0x0c000000;
304 fecp->rfar = 0x0000030c;
306 /* Set Tx FIFO granularity value */
307 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
308 fecp->tfar = 0x00000080;
311 fecp->ctcwr = 0x03000000;
313 /* Enable DMA receive task */
314 MCD_startDma(info->rx_task,
323 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
324 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
327 /* Enable DMA tx task with no ready buffer descriptors */
328 MCD_startDma(info->tx_task,
337 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
338 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
341 /* Now enable the transmit and receive processing */
342 fecp->ecr |= FEC_ECR_ETHER_EN;
347 static int mcdmafec_init(struct udevice *dev)
349 return fec_init(dev);
352 static int mcdmafec_send(struct udevice *dev, void *packet, int length)
354 struct fec_info_dma *info = dev->priv;
355 cbd_t *p_tbd, *p_used_tbd;
358 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
360 /* process all the consumed TBDs */
361 while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
362 p_used_tbd = &info->txbd[info->used_tbd_idx];
363 if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
365 printf("Cannot clean TBD %d, in use\n",
366 info->clean_tbd_num);
371 /* clean this buffer descriptor */
372 if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
373 p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
375 p_used_tbd->cbd_sc = 0;
377 /* update some indeces for a correct handling of TBD ring */
378 info->clean_tbd_num++;
379 info->used_tbd_idx = (info->used_tbd_idx + 1)
380 % CONFIG_SYS_TX_ETH_BUFFER;
383 /* Check for valid length of data. */
384 if (length > 1500 || length <= 0)
387 /* Check the number of vacant TxBDs. */
388 if (info->clean_tbd_num < 1) {
389 printf("No available TxBDs ...\n");
393 /* Get the first TxBD to send the mac header */
394 p_tbd = &info->txbd[info->tx_idx];
395 p_tbd->cbd_datlen = length;
396 p_tbd->cbd_bufaddr = (u32)packet;
397 p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
398 info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
400 /* Enable DMA transmit task */
401 MCD_continDma(info->tx_task);
403 info->clean_tbd_num -= 1;
405 /* wait until frame is sent . */
406 while (p_tbd->cbd_sc & BD_ENET_TX_READY)
409 return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
412 static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
414 struct fec_info_dma *info = dev->priv;
415 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
417 cbd_t *prbd = &info->rxbd[info->rx_idx];
419 int frame_length, len = 0;
421 /* Check if any critical events have happened */
426 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
427 printf("fec_recv: error\n");
433 if (ievent & FEC_EIR_HBERR) {
434 /* Heartbeat error */
435 fecp->tcr |= FEC_TCR_GTS;
438 if (ievent & FEC_EIR_GRA) {
439 /* Graceful stop complete */
440 if (fecp->tcr & FEC_TCR_GTS) {
441 printf("fec_recv: tcr_gts\n");
443 fecp->tcr &= ~FEC_TCR_GTS;
449 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
450 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
451 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
452 ((prbd->cbd_datlen - 4) > 14)) {
453 /* Get buffer address and size */
454 frame_length = prbd->cbd_datlen - 4;
456 /* Fill the buffer and pass it to upper layers */
457 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
462 /* Reset buffer descriptor as empty */
463 if (info->rx_idx == (PKTBUFSRX - 1))
464 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
466 prbd->cbd_sc = BD_ENET_RX_EMPTY;
468 prbd->cbd_datlen = PKTSIZE_ALIGN;
470 /* Now, we have an empty RxBD, restart the DMA receive task */
471 MCD_continDma(info->rx_task);
473 /* Increment BD count */
474 info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
480 static void mcdmafec_halt(struct udevice *dev)
485 static const struct eth_ops mcdmafec_ops = {
486 .start = mcdmafec_init,
487 .send = mcdmafec_send,
488 .recv = mcdmafec_recv,
489 .stop = mcdmafec_halt,
493 * Boot sequence, called just after mcffec_ofdata_to_platdata,
494 * as DM way, it replaces old mcffec_initialize.
496 static int mcdmafec_probe(struct udevice *dev)
498 struct fec_info_dma *info = dev->priv;
499 struct eth_pdata *pdata = dev_get_platdata(dev);
500 int node = dev_of_offset(dev);
504 info->index = dev->seq;
505 info->iobase = pdata->iobase;
506 info->miibase = pdata->iobase;
509 val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
511 info->rx_task = fdt32_to_cpu(*val);
513 val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
515 info->tx_task = fdt32_to_cpu(*val);
517 val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
519 info->rx_pri = fdt32_to_cpu(*val);
521 val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
523 info->tx_pri = fdt32_to_cpu(*val);
525 val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
527 info->rx_init = fdt32_to_cpu(*val);
529 val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
531 info->tx_init = fdt32_to_cpu(*val);
533 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
534 u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
538 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
539 info->bus = mdio_alloc();
542 strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
543 info->bus->read = mcffec_miiphy_read;
544 info->bus->write = mcffec_miiphy_write;
546 retval = mdio_register(info->bus);
554 static int mcdmafec_remove(struct udevice *dev)
556 struct fec_info_dma *priv = dev_get_priv(dev);
558 mdio_unregister(priv->bus);
559 mdio_free(priv->bus);
565 * Boot sequence, called 1st
567 static int mcdmafec_ofdata_to_platdata(struct udevice *dev)
569 struct eth_pdata *pdata = dev_get_platdata(dev);
572 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
573 /* Default to 10Mbit/s */
574 pdata->max_speed = 10;
576 val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
578 pdata->max_speed = fdt32_to_cpu(*val);
583 static const struct udevice_id mcdmafec_ids[] = {
584 { .compatible = "fsl,mcf-dma-fec" },
588 U_BOOT_DRIVER(mcffec) = {
591 .of_match = mcdmafec_ids,
592 .ofdata_to_platdata = mcdmafec_ofdata_to_platdata,
593 .probe = mcdmafec_probe,
594 .remove = mcdmafec_remove,
595 .ops = &mcdmafec_ops,
596 .priv_auto_alloc_size = sizeof(struct fec_info_dma),
597 .platdata_auto_alloc_size = sizeof(struct eth_pdata),