drivers/net/e1000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**************************************************************************
   3 Intel Pro 1000 for ppcboot/das-u-boot
   4 Drivers are port from Intel's Linux driver e1000-4.3.15
   5 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   6 tested on both gig copper and gig fiber boards
   7 ***************************************************************************/
   8 /*******************************************************************************
   9
  10
  11   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  12
  13
  14   Contact Information:
  15   Linux NICS <linux.nics@intel.com>
  16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18 *******************************************************************************/
  19 /*
  20  *  Copyright (C) Archway Digital Solutions.
  21  *
  22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23  *  2/9/2002
  24  *
  25  *  Copyright (C) Linux Networx.
  26  *  Massive upgrade to work with the new intel gigabit NICs.
  27  *  <ebiederman at lnxi dot com>
  28  *
  29  *  Copyright 2011 Freescale Semiconductor, Inc.
  30  */
  31
  32 #include <common.h>
  33 #include <command.h>
  34 #include <cpu_func.h>
  35 #include <dm.h>
  36 #include <errno.h>
  37 #include <malloc.h>
  38 #include <memalign.h>
  39 #include <net.h>
  40 #include <pci.h>
  41 #include "e1000.h"
  42 #include <asm/cache.h>
  43
  44 #define TOUT_LOOP   100000
  45
  46 #ifdef CONFIG_DM_ETH
  47 #define virt_to_bus(devno, v)   dm_pci_virt_to_mem(devno, (void *) (v))
  48 #define bus_to_phys(devno, a)   dm_pci_mem_to_phys(devno, a)
  49 #else
  50 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  51 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  52 #endif
  53
  54 #define E1000_DEFAULT_PCI_PBA   0x00000030
  55 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  56
  57 /* NIC specific static variables go here */
  58
  59 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  60 #define E1000_BUFFER_ALIGN      128
  61
  62 /*
  63  * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  64  * Concurrent receiving on multiple active Ethernet devices will not work.
  65  * Normally U-Boot does not support this anyway. To fix it in this driver,
  66  * move these buffers and the tx/rx pointers to struct e1000_hw.
  67  */
  68 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  69 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  70 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  71
  72 static int tx_tail;
  73 static int rx_tail, rx_last;
  74 #ifdef CONFIG_DM_ETH
  75 static int num_cards;   /* Number of E1000 devices seen so far */
  76 #endif
  77
  78 static struct pci_device_id e1000_supported[] = {
  79         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  80         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  81         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  82         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  83         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  84         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  85         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  86         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  87         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  88         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  89         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  90         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  91         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  92         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  93         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  94         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  95         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  96         /* E1000 PCIe card */
  97         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  98         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  99         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
 100         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
 101         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
 102         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
 103         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
 104         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
 105         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
 106         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
 107         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
 108         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
 109         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
 110         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
 111         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
 112         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
 113         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
 114         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
 115         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
 116         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
 117         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
 118         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
 119         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
 120         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
 121         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
 122         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
 123         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
 124         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
 125         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
 126         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
 127
 128         {}
 129 };
 130
 131 /* Function forward declarations */
 132 static int e1000_setup_link(struct e1000_hw *hw);
 133 static int e1000_setup_fiber_link(struct e1000_hw *hw);
 134 static int e1000_setup_copper_link(struct e1000_hw *hw);
 135 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 136 static void e1000_config_collision_dist(struct e1000_hw *hw);
 137 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 138 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 139 static int e1000_check_for_link(struct e1000_hw *hw);
 140 static int e1000_wait_autoneg(struct e1000_hw *hw);
 141 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 142                                        uint16_t * duplex);
 143 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 144                               uint16_t * phy_data);
 145 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 146                                uint16_t phy_data);
 147 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 148 static int e1000_phy_reset(struct e1000_hw *hw);
 149 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 150 static void e1000_set_media_type(struct e1000_hw *hw);
 151
 152 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 153 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
 154 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 155
 156 #ifndef CONFIG_E1000_NO_NVM
 157 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 158 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
 159 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 160                 uint16_t words,
 161                 uint16_t *data);
 162 /******************************************************************************
 163  * Raises the EEPROM's clock input.
 164  *
 165  * hw - Struct containing variables accessed by shared code
 166  * eecd - EECD's current value
 167  *****************************************************************************/
 168 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 169 {
 170         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 171          * wait 50 microseconds.
 172          */
 173         *eecd = *eecd | E1000_EECD_SK;
 174         E1000_WRITE_REG(hw, EECD, *eecd);
 175         E1000_WRITE_FLUSH(hw);
 176         udelay(50);
 177 }
 178
 179 /******************************************************************************
 180  * Lowers the EEPROM's clock input.
 181  *
 182  * hw - Struct containing variables accessed by shared code
 183  * eecd - EECD's current value
 184  *****************************************************************************/
 185 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 186 {
 187         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 188          * wait 50 microseconds.
 189          */
 190         *eecd = *eecd & ~E1000_EECD_SK;
 191         E1000_WRITE_REG(hw, EECD, *eecd);
 192         E1000_WRITE_FLUSH(hw);
 193         udelay(50);
 194 }
 195
 196 /******************************************************************************
 197  * Shift data bits out to the EEPROM.
 198  *
 199  * hw - Struct containing variables accessed by shared code
 200  * data - data to send to the EEPROM
 201  * count - number of bits to shift out
 202  *****************************************************************************/
 203 static void
 204 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 205 {
 206         uint32_t eecd;
 207         uint32_t mask;
 208
 209         /* We need to shift "count" bits out to the EEPROM. So, value in the
 210          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 211          * In order to do this, "data" must be broken down into bits.
 212          */
 213         mask = 0x01 << (count - 1);
 214         eecd = E1000_READ_REG(hw, EECD);
 215         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 216         do {
 217                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 218                  * and then raising and then lowering the clock (the SK bit controls
 219                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 220                  * by setting "DI" to "0" and then raising and then lowering the clock.
 221                  */
 222                 eecd &= ~E1000_EECD_DI;
 223
 224                 if (data & mask)
 225                         eecd |= E1000_EECD_DI;
 226
 227                 E1000_WRITE_REG(hw, EECD, eecd);
 228                 E1000_WRITE_FLUSH(hw);
 229
 230                 udelay(50);
 231
 232                 e1000_raise_ee_clk(hw, &eecd);
 233                 e1000_lower_ee_clk(hw, &eecd);
 234
 235                 mask = mask >> 1;
 236
 237         } while (mask);
 238
 239         /* We leave the "DI" bit set to "0" when we leave this routine. */
 240         eecd &= ~E1000_EECD_DI;
 241         E1000_WRITE_REG(hw, EECD, eecd);
 242 }
 243
 244 /******************************************************************************
 245  * Shift data bits in from the EEPROM
 246  *
 247  * hw - Struct containing variables accessed by shared code
 248  *****************************************************************************/
 249 static uint16_t
 250 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 251 {
 252         uint32_t eecd;
 253         uint32_t i;
 254         uint16_t data;
 255
 256         /* In order to read a register from the EEPROM, we need to shift 'count'
 257          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 258          * input to the EEPROM (setting the SK bit), and then reading the
 259          * value of the "DO" bit.  During this "shifting in" process the
 260          * "DI" bit should always be clear.
 261          */
 262
 263         eecd = E1000_READ_REG(hw, EECD);
 264
 265         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 266         data = 0;
 267
 268         for (i = 0; i < count; i++) {
 269                 data = data << 1;
 270                 e1000_raise_ee_clk(hw, &eecd);
 271
 272                 eecd = E1000_READ_REG(hw, EECD);
 273
 274                 eecd &= ~(E1000_EECD_DI);
 275                 if (eecd & E1000_EECD_DO)
 276                         data |= 1;
 277
 278                 e1000_lower_ee_clk(hw, &eecd);
 279         }
 280
 281         return data;
 282 }
 283
 284 /******************************************************************************
 285  * Returns EEPROM to a "standby" state
 286  *
 287  * hw - Struct containing variables accessed by shared code
 288  *****************************************************************************/
 289 void e1000_standby_eeprom(struct e1000_hw *hw)
 290 {
 291         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 292         uint32_t eecd;
 293
 294         eecd = E1000_READ_REG(hw, EECD);
 295
 296         if (eeprom->type == e1000_eeprom_microwire) {
 297                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 298                 E1000_WRITE_REG(hw, EECD, eecd);
 299                 E1000_WRITE_FLUSH(hw);
 300                 udelay(eeprom->delay_usec);
 301
 302                 /* Clock high */
 303                 eecd |= E1000_EECD_SK;
 304                 E1000_WRITE_REG(hw, EECD, eecd);
 305                 E1000_WRITE_FLUSH(hw);
 306                 udelay(eeprom->delay_usec);
 307
 308                 /* Select EEPROM */
 309                 eecd |= E1000_EECD_CS;
 310                 E1000_WRITE_REG(hw, EECD, eecd);
 311                 E1000_WRITE_FLUSH(hw);
 312                 udelay(eeprom->delay_usec);
 313
 314                 /* Clock low */
 315                 eecd &= ~E1000_EECD_SK;
 316                 E1000_WRITE_REG(hw, EECD, eecd);
 317                 E1000_WRITE_FLUSH(hw);
 318                 udelay(eeprom->delay_usec);
 319         } else if (eeprom->type == e1000_eeprom_spi) {
 320                 /* Toggle CS to flush commands */
 321                 eecd |= E1000_EECD_CS;
 322                 E1000_WRITE_REG(hw, EECD, eecd);
 323                 E1000_WRITE_FLUSH(hw);
 324                 udelay(eeprom->delay_usec);
 325                 eecd &= ~E1000_EECD_CS;
 326                 E1000_WRITE_REG(hw, EECD, eecd);
 327                 E1000_WRITE_FLUSH(hw);
 328                 udelay(eeprom->delay_usec);
 329         }
 330 }
 331
 332 /***************************************************************************
 333 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 334 *
 335 * hw - Struct containing variables accessed by shared code
 336 ****************************************************************************/
 337 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 338 {
 339         uint32_t eecd = 0;
 340
 341         DEBUGFUNC();
 342
 343         if (hw->mac_type == e1000_ich8lan)
 344                 return false;
 345
 346         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 347                 eecd = E1000_READ_REG(hw, EECD);
 348
 349                 /* Isolate bits 15 & 16 */
 350                 eecd = ((eecd >> 15) & 0x03);
 351
 352                 /* If both bits are set, device is Flash type */
 353                 if (eecd == 0x03)
 354                         return false;
 355         }
 356         return true;
 357 }
 358
 359 /******************************************************************************
 360  * Prepares EEPROM for access
 361  *
 362  * hw - Struct containing variables accessed by shared code
 363  *
 364  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 365  * function should be called before issuing a command to the EEPROM.
 366  *****************************************************************************/
 367 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 368 {
 369         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 370         uint32_t eecd, i = 0;
 371
 372         DEBUGFUNC();
 373
 374         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 375                 return -E1000_ERR_SWFW_SYNC;
 376         eecd = E1000_READ_REG(hw, EECD);
 377
 378         if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
 379                 /* Request EEPROM Access */
 380                 if (hw->mac_type > e1000_82544) {
 381                         eecd |= E1000_EECD_REQ;
 382                         E1000_WRITE_REG(hw, EECD, eecd);
 383                         eecd = E1000_READ_REG(hw, EECD);
 384                         while ((!(eecd & E1000_EECD_GNT)) &&
 385                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 386                                 i++;
 387                                 udelay(5);
 388                                 eecd = E1000_READ_REG(hw, EECD);
 389                         }
 390                         if (!(eecd & E1000_EECD_GNT)) {
 391                                 eecd &= ~E1000_EECD_REQ;
 392                                 E1000_WRITE_REG(hw, EECD, eecd);
 393                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 394                                 return -E1000_ERR_EEPROM;
 395                         }
 396                 }
 397         }
 398
 399         /* Setup EEPROM for Read/Write */
 400
 401         if (eeprom->type == e1000_eeprom_microwire) {
 402                 /* Clear SK and DI */
 403                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 404                 E1000_WRITE_REG(hw, EECD, eecd);
 405
 406                 /* Set CS */
 407                 eecd |= E1000_EECD_CS;
 408                 E1000_WRITE_REG(hw, EECD, eecd);
 409         } else if (eeprom->type == e1000_eeprom_spi) {
 410                 /* Clear SK and CS */
 411                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 412                 E1000_WRITE_REG(hw, EECD, eecd);
 413                 udelay(1);
 414         }
 415
 416         return E1000_SUCCESS;
 417 }
 418
 419 /******************************************************************************
 420  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 421  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 422  * registers must be mapped, or this will crash.
 423  *
 424  * hw - Struct containing variables accessed by shared code
 425  *****************************************************************************/
 426 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 427 {
 428         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 429         uint32_t eecd;
 430         int32_t ret_val = E1000_SUCCESS;
 431         uint16_t eeprom_size;
 432
 433         if (hw->mac_type == e1000_igb)
 434                 eecd = E1000_READ_REG(hw, I210_EECD);
 435         else
 436                 eecd = E1000_READ_REG(hw, EECD);
 437
 438         DEBUGFUNC();
 439
 440         switch (hw->mac_type) {
 441         case e1000_82542_rev2_0:
 442         case e1000_82542_rev2_1:
 443         case e1000_82543:
 444         case e1000_82544:
 445                 eeprom->type = e1000_eeprom_microwire;
 446                 eeprom->word_size = 64;
 447                 eeprom->opcode_bits = 3;
 448                 eeprom->address_bits = 6;
 449                 eeprom->delay_usec = 50;
 450                 eeprom->use_eerd = false;
 451                 eeprom->use_eewr = false;
 452         break;
 453         case e1000_82540:
 454         case e1000_82545:
 455         case e1000_82545_rev_3:
 456         case e1000_82546:
 457         case e1000_82546_rev_3:
 458                 eeprom->type = e1000_eeprom_microwire;
 459                 eeprom->opcode_bits = 3;
 460                 eeprom->delay_usec = 50;
 461                 if (eecd & E1000_EECD_SIZE) {
 462                         eeprom->word_size = 256;
 463                         eeprom->address_bits = 8;
 464                 } else {
 465                         eeprom->word_size = 64;
 466                         eeprom->address_bits = 6;
 467                 }
 468                 eeprom->use_eerd = false;
 469                 eeprom->use_eewr = false;
 470                 break;
 471         case e1000_82541:
 472         case e1000_82541_rev_2:
 473         case e1000_82547:
 474         case e1000_82547_rev_2:
 475                 if (eecd & E1000_EECD_TYPE) {
 476                         eeprom->type = e1000_eeprom_spi;
 477                         eeprom->opcode_bits = 8;
 478                         eeprom->delay_usec = 1;
 479                         if (eecd & E1000_EECD_ADDR_BITS) {
 480                                 eeprom->page_size = 32;
 481                                 eeprom->address_bits = 16;
 482                         } else {
 483                                 eeprom->page_size = 8;
 484                                 eeprom->address_bits = 8;
 485                         }
 486                 } else {
 487                         eeprom->type = e1000_eeprom_microwire;
 488                         eeprom->opcode_bits = 3;
 489                         eeprom->delay_usec = 50;
 490                         if (eecd & E1000_EECD_ADDR_BITS) {
 491                                 eeprom->word_size = 256;
 492                                 eeprom->address_bits = 8;
 493                         } else {
 494                                 eeprom->word_size = 64;
 495                                 eeprom->address_bits = 6;
 496                         }
 497                 }
 498                 eeprom->use_eerd = false;
 499                 eeprom->use_eewr = false;
 500                 break;
 501         case e1000_82571:
 502         case e1000_82572:
 503                 eeprom->type = e1000_eeprom_spi;
 504                 eeprom->opcode_bits = 8;
 505                 eeprom->delay_usec = 1;
 506                 if (eecd & E1000_EECD_ADDR_BITS) {
 507                         eeprom->page_size = 32;
 508                         eeprom->address_bits = 16;
 509                 } else {
 510                         eeprom->page_size = 8;
 511                         eeprom->address_bits = 8;
 512                 }
 513                 eeprom->use_eerd = false;
 514                 eeprom->use_eewr = false;
 515                 break;
 516         case e1000_82573:
 517         case e1000_82574:
 518                 eeprom->type = e1000_eeprom_spi;
 519                 eeprom->opcode_bits = 8;
 520                 eeprom->delay_usec = 1;
 521                 if (eecd & E1000_EECD_ADDR_BITS) {
 522                         eeprom->page_size = 32;
 523                         eeprom->address_bits = 16;
 524                 } else {
 525                         eeprom->page_size = 8;
 526                         eeprom->address_bits = 8;
 527                 }
 528                 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 529                         eeprom->use_eerd = true;
 530                         eeprom->use_eewr = true;
 531
 532                         eeprom->type = e1000_eeprom_flash;
 533                         eeprom->word_size = 2048;
 534
 535                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 536                  * Flash update issue on parts which use a FLASH for NVM. */
 537                         eecd &= ~E1000_EECD_AUPDEN;
 538                         E1000_WRITE_REG(hw, EECD, eecd);
 539                 }
 540                 break;
 541         case e1000_80003es2lan:
 542                 eeprom->type = e1000_eeprom_spi;
 543                 eeprom->opcode_bits = 8;
 544                 eeprom->delay_usec = 1;
 545                 if (eecd & E1000_EECD_ADDR_BITS) {
 546                         eeprom->page_size = 32;
 547                         eeprom->address_bits = 16;
 548                 } else {
 549                         eeprom->page_size = 8;
 550                         eeprom->address_bits = 8;
 551                 }
 552                 eeprom->use_eerd = true;
 553                 eeprom->use_eewr = false;
 554                 break;
 555         case e1000_igb:
 556                 /* i210 has 4k of iNVM mapped as EEPROM */
 557                 eeprom->type = e1000_eeprom_invm;
 558                 eeprom->opcode_bits = 8;
 559                 eeprom->delay_usec = 1;
 560                 eeprom->page_size = 32;
 561                 eeprom->address_bits = 16;
 562                 eeprom->use_eerd = true;
 563                 eeprom->use_eewr = false;
 564                 break;
 565         default:
 566                 break;
 567         }
 568
 569         if (eeprom->type == e1000_eeprom_spi ||
 570             eeprom->type == e1000_eeprom_invm) {
 571                 /* eeprom_size will be an enum [0..8] that maps
 572                  * to eeprom sizes 128B to
 573                  * 32KB (incremented by powers of 2).
 574                  */
 575                 if (hw->mac_type <= e1000_82547_rev_2) {
 576                         /* Set to default value for initial eeprom read. */
 577                         eeprom->word_size = 64;
 578                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 579                                         &eeprom_size);
 580                         if (ret_val)
 581                                 return ret_val;
 582                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 583                                 >> EEPROM_SIZE_SHIFT;
 584                         /* 256B eeprom size was not supported in earlier
 585                          * hardware, so we bump eeprom_size up one to
 586                          * ensure that "1" (which maps to 256B) is never
 587                          * the result used in the shifting logic below. */
 588                         if (eeprom_size)
 589                                 eeprom_size++;
 590                 } else {
 591                         eeprom_size = (uint16_t)((eecd &
 592                                 E1000_EECD_SIZE_EX_MASK) >>
 593                                 E1000_EECD_SIZE_EX_SHIFT);
 594                 }
 595
 596                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 597         }
 598         return ret_val;
 599 }
 600
 601 /******************************************************************************
 602  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 603  *
 604  * hw - Struct containing variables accessed by shared code
 605  *****************************************************************************/
 606 static int32_t
 607 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 608 {
 609         uint32_t attempts = 100000;
 610         uint32_t i, reg = 0;
 611         int32_t done = E1000_ERR_EEPROM;
 612
 613         for (i = 0; i < attempts; i++) {
 614                 if (eerd == E1000_EEPROM_POLL_READ) {
 615                         if (hw->mac_type == e1000_igb)
 616                                 reg = E1000_READ_REG(hw, I210_EERD);
 617                         else
 618                                 reg = E1000_READ_REG(hw, EERD);
 619                 } else {
 620                         if (hw->mac_type == e1000_igb)
 621                                 reg = E1000_READ_REG(hw, I210_EEWR);
 622                         else
 623                                 reg = E1000_READ_REG(hw, EEWR);
 624                 }
 625
 626                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 627                         done = E1000_SUCCESS;
 628                         break;
 629                 }
 630                 udelay(5);
 631         }
 632
 633         return done;
 634 }
 635
 636 /******************************************************************************
 637  * Reads a 16 bit word from the EEPROM using the EERD register.
 638  *
 639  * hw - Struct containing variables accessed by shared code
 640  * offset - offset of  word in the EEPROM to read
 641  * data - word read from the EEPROM
 642  * words - number of words to read
 643  *****************************************************************************/
 644 static int32_t
 645 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 646                         uint16_t offset,
 647                         uint16_t words,
 648                         uint16_t *data)
 649 {
 650         uint32_t i, eerd = 0;
 651         int32_t error = 0;
 652
 653         for (i = 0; i < words; i++) {
 654                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 655                         E1000_EEPROM_RW_REG_START;
 656
 657                 if (hw->mac_type == e1000_igb)
 658                         E1000_WRITE_REG(hw, I210_EERD, eerd);
 659                 else
 660                         E1000_WRITE_REG(hw, EERD, eerd);
 661
 662                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 663
 664                 if (error)
 665                         break;
 666
 667                 if (hw->mac_type == e1000_igb) {
 668                         data[i] = (E1000_READ_REG(hw, I210_EERD) >>
 669                                 E1000_EEPROM_RW_REG_DATA);
 670                 } else {
 671                         data[i] = (E1000_READ_REG(hw, EERD) >>
 672                                 E1000_EEPROM_RW_REG_DATA);
 673                 }
 674
 675         }
 676
 677         return error;
 678 }
 679
 680 void e1000_release_eeprom(struct e1000_hw *hw)
 681 {
 682         uint32_t eecd;
 683
 684         DEBUGFUNC();
 685
 686         eecd = E1000_READ_REG(hw, EECD);
 687
 688         if (hw->eeprom.type == e1000_eeprom_spi) {
 689                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 690                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 691
 692                 E1000_WRITE_REG(hw, EECD, eecd);
 693
 694                 udelay(hw->eeprom.delay_usec);
 695         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 696                 /* cleanup eeprom */
 697
 698                 /* CS on Microwire is active-high */
 699                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 700
 701                 E1000_WRITE_REG(hw, EECD, eecd);
 702
 703                 /* Rising edge of clock */
 704                 eecd |= E1000_EECD_SK;
 705                 E1000_WRITE_REG(hw, EECD, eecd);
 706                 E1000_WRITE_FLUSH(hw);
 707                 udelay(hw->eeprom.delay_usec);
 708
 709                 /* Falling edge of clock */
 710                 eecd &= ~E1000_EECD_SK;
 711                 E1000_WRITE_REG(hw, EECD, eecd);
 712                 E1000_WRITE_FLUSH(hw);
 713                 udelay(hw->eeprom.delay_usec);
 714         }
 715
 716         /* Stop requesting EEPROM access */
 717         if (hw->mac_type > e1000_82544) {
 718                 eecd &= ~E1000_EECD_REQ;
 719                 E1000_WRITE_REG(hw, EECD, eecd);
 720         }
 721
 722         e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 723 }
 724
 725 /******************************************************************************
 726  * Reads a 16 bit word from the EEPROM.
 727  *
 728  * hw - Struct containing variables accessed by shared code
 729  *****************************************************************************/
 730 static int32_t
 731 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 732 {
 733         uint16_t retry_count = 0;
 734         uint8_t spi_stat_reg;
 735
 736         DEBUGFUNC();
 737
 738         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 739          * EEPROM will signal that the command has been completed by clearing
 740          * bit 0 of the internal status register.  If it's not cleared within
 741          * 5 milliseconds, then error out.
 742          */
 743         retry_count = 0;
 744         do {
 745                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 746                         hw->eeprom.opcode_bits);
 747                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 748                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 749                         break;
 750
 751                 udelay(5);
 752                 retry_count += 5;
 753
 754                 e1000_standby_eeprom(hw);
 755         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 756
 757         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 758          * only 0-5mSec on 5V devices)
 759          */
 760         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 761                 DEBUGOUT("SPI EEPROM Status error\n");
 762                 return -E1000_ERR_EEPROM;
 763         }
 764
 765         return E1000_SUCCESS;
 766 }
 767
 768 /******************************************************************************
 769  * Reads a 16 bit word from the EEPROM.
 770  *
 771  * hw - Struct containing variables accessed by shared code
 772  * offset - offset of  word in the EEPROM to read
 773  * data - word read from the EEPROM
 774  *****************************************************************************/
 775 static int32_t
 776 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 777                 uint16_t words, uint16_t *data)
 778 {
 779         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 780         uint32_t i = 0;
 781
 782         DEBUGFUNC();
 783
 784         /* If eeprom is not yet detected, do so now */
 785         if (eeprom->word_size == 0)
 786                 e1000_init_eeprom_params(hw);
 787
 788         /* A check for invalid values:  offset too large, too many words,
 789          * and not enough words.
 790          */
 791         if ((offset >= eeprom->word_size) ||
 792                 (words > eeprom->word_size - offset) ||
 793                 (words == 0)) {
 794                 DEBUGOUT("\"words\" parameter out of bounds."
 795                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 796                 return -E1000_ERR_EEPROM;
 797         }
 798
 799         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 800          * directly. In this case, we need to acquire the EEPROM so that
 801          * FW or other port software does not interrupt.
 802          */
 803         if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 804                 hw->eeprom.use_eerd == false) {
 805
 806                 /* Prepare the EEPROM for bit-bang reading */
 807                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 808                         return -E1000_ERR_EEPROM;
 809         }
 810
 811         /* Eerd register EEPROM access requires no eeprom aquire/release */
 812         if (eeprom->use_eerd == true)
 813                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 814
 815         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 816          * acquired the EEPROM at this point, so any returns should relase it */
 817         if (eeprom->type == e1000_eeprom_spi) {
 818                 uint16_t word_in;
 819                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 820
 821                 if (e1000_spi_eeprom_ready(hw)) {
 822                         e1000_release_eeprom(hw);
 823                         return -E1000_ERR_EEPROM;
 824                 }
 825
 826                 e1000_standby_eeprom(hw);
 827
 828                 /* Some SPI eeproms use the 8th address bit embedded in
 829                  * the opcode */
 830                 if ((eeprom->address_bits == 8) && (offset >= 128))
 831                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 832
 833                 /* Send the READ command (opcode + addr)  */
 834                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 835                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 836                                 eeprom->address_bits);
 837
 838                 /* Read the data.  The address of the eeprom internally
 839                  * increments with each byte (spi) being read, saving on the
 840                  * overhead of eeprom setup and tear-down.  The address
 841                  * counter will roll over if reading beyond the size of
 842                  * the eeprom, thus allowing the entire memory to be read
 843                  * starting from any offset. */
 844                 for (i = 0; i < words; i++) {
 845                         word_in = e1000_shift_in_ee_bits(hw, 16);
 846                         data[i] = (word_in >> 8) | (word_in << 8);
 847                 }
 848         } else if (eeprom->type == e1000_eeprom_microwire) {
 849                 for (i = 0; i < words; i++) {
 850                         /* Send the READ command (opcode + addr)  */
 851                         e1000_shift_out_ee_bits(hw,
 852                                 EEPROM_READ_OPCODE_MICROWIRE,
 853                                 eeprom->opcode_bits);
 854                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 855                                 eeprom->address_bits);
 856
 857                         /* Read the data.  For microwire, each word requires
 858                          * the overhead of eeprom setup and tear-down. */
 859                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 860                         e1000_standby_eeprom(hw);
 861                 }
 862         }
 863
 864         /* End this read operation */
 865         e1000_release_eeprom(hw);
 866
 867         return E1000_SUCCESS;
 868 }
 869
 870 #ifndef CONFIG_DM_ETH
 871 /******************************************************************************
 872  *  e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
 873  *  @hw: pointer to the HW structure
 874  *  @offset: offset within the Shadow Ram to be written to
 875  *  @words: number of words to write
 876  *  @data: 16 bit word(s) to be written to the Shadow Ram
 877  *
 878  *  Writes data to Shadow Ram at offset using EEWR register.
 879  *
 880  *  If e1000_update_eeprom_checksum_i210 is not called after this function, the
 881  *  Shadow Ram will most likely contain an invalid checksum.
 882  *****************************************************************************/
 883 static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
 884                                        uint16_t words, uint16_t *data)
 885 {
 886         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 887         uint32_t i, k, eewr = 0;
 888         uint32_t attempts = 100000;
 889         int32_t ret_val = 0;
 890
 891         /* A check for invalid values:  offset too large, too many words,
 892          * too many words for the offset, and not enough words.
 893          */
 894         if ((offset >= eeprom->word_size) ||
 895             (words > (eeprom->word_size - offset)) || (words == 0)) {
 896                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 897                 ret_val = -E1000_ERR_EEPROM;
 898                 goto out;
 899         }
 900
 901         for (i = 0; i < words; i++) {
 902                 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
 903                                 | (data[i] << E1000_EEPROM_RW_REG_DATA) |
 904                                 E1000_EEPROM_RW_REG_START;
 905
 906                 E1000_WRITE_REG(hw, I210_EEWR, eewr);
 907
 908                 for (k = 0; k < attempts; k++) {
 909                         if (E1000_EEPROM_RW_REG_DONE &
 910                             E1000_READ_REG(hw, I210_EEWR)) {
 911                                 ret_val = 0;
 912                                 break;
 913                         }
 914                         udelay(5);
 915                 }
 916
 917                 if (ret_val) {
 918                         DEBUGOUT("Shadow RAM write EEWR timed out\n");
 919                         break;
 920                 }
 921         }
 922
 923 out:
 924         return ret_val;
 925 }
 926
 927 /******************************************************************************
 928  *  e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
 929  *  @hw: pointer to the HW structure
 930  *
 931  *****************************************************************************/
 932 static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
 933 {
 934         int32_t ret_val = -E1000_ERR_EEPROM;
 935         uint32_t i, reg;
 936
 937         for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
 938                 reg = E1000_READ_REG(hw, EECD);
 939                 if (reg & E1000_EECD_FLUDONE_I210) {
 940                         ret_val = 0;
 941                         break;
 942                 }
 943                 udelay(5);
 944         }
 945
 946         return ret_val;
 947 }
 948
 949 /******************************************************************************
 950  *  e1000_update_flash_i210 - Commit EEPROM to the flash
 951  *  @hw: pointer to the HW structure
 952  *
 953  *****************************************************************************/
 954 static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
 955 {
 956         int32_t ret_val = 0;
 957         uint32_t flup;
 958
 959         ret_val = e1000_pool_flash_update_done_i210(hw);
 960         if (ret_val == -E1000_ERR_EEPROM) {
 961                 DEBUGOUT("Flash update time out\n");
 962                 goto out;
 963         }
 964
 965         flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
 966         E1000_WRITE_REG(hw, EECD, flup);
 967
 968         ret_val = e1000_pool_flash_update_done_i210(hw);
 969         if (ret_val)
 970                 DEBUGOUT("Flash update time out\n");
 971         else
 972                 DEBUGOUT("Flash update complete\n");
 973
 974 out:
 975         return ret_val;
 976 }
 977
 978 /******************************************************************************
 979  *  e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
 980  *  @hw: pointer to the HW structure
 981  *
 982  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 983  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 984  *  value to the EEPROM. Next commit EEPROM data onto the Flash.
 985  *****************************************************************************/
 986 static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
 987 {
 988         int32_t ret_val = 0;
 989         uint16_t checksum = 0;
 990         uint16_t i, nvm_data;
 991
 992         /* Read the first word from the EEPROM. If this times out or fails, do
 993          * not continue or we could be in for a very long wait while every
 994          * EEPROM read fails
 995          */
 996         ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
 997         if (ret_val) {
 998                 DEBUGOUT("EEPROM read failed\n");
 999                 goto out;
1000         }
1001
1002         if (!(e1000_get_hw_eeprom_semaphore(hw))) {
1003                 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
1004                  * because we do not want to take the synchronization
1005                  * semaphores twice here.
1006                  */
1007
1008                 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1009                         ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1010                         if (ret_val) {
1011                                 e1000_put_hw_eeprom_semaphore(hw);
1012                                 DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1013                                 goto out;
1014                         }
1015                         checksum += nvm_data;
1016                 }
1017                 checksum = (uint16_t)EEPROM_SUM - checksum;
1018                 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1019                                                   &checksum);
1020                 if (ret_val) {
1021                         e1000_put_hw_eeprom_semaphore(hw);
1022                         DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1023                         goto out;
1024                 }
1025
1026                 e1000_put_hw_eeprom_semaphore(hw);
1027
1028                 ret_val = e1000_update_flash_i210(hw);
1029         } else {
1030                 ret_val = -E1000_ERR_SWFW_SYNC;
1031         }
1032
1033 out:
1034         return ret_val;
1035 }
1036 #endif
1037
1038 /******************************************************************************
1039  * Verifies that the EEPROM has a valid checksum
1040  *
1041  * hw - Struct containing variables accessed by shared code
1042  *
1043  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
1044  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
1045  * valid.
1046  *****************************************************************************/
1047 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
1048 {
1049         uint16_t i, checksum, checksum_reg, *buf;
1050
1051         DEBUGFUNC();
1052
1053         /* Allocate a temporary buffer */
1054         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1055         if (!buf) {
1056                 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
1057                 return -E1000_ERR_EEPROM;
1058         }
1059
1060         /* Read the EEPROM */
1061         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
1062                 E1000_ERR(hw, "Unable to read EEPROM!\n");
1063                 return -E1000_ERR_EEPROM;
1064         }
1065
1066         /* Compute the checksum */
1067         checksum = 0;
1068         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1069                 checksum += buf[i];
1070         checksum = ((uint16_t)EEPROM_SUM) - checksum;
1071         checksum_reg = buf[i];
1072
1073         /* Verify it! */
1074         if (checksum == checksum_reg)
1075                 return 0;
1076
1077         /* Hrm, verification failed, print an error */
1078         E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1079         E1000_ERR(hw, "  ...register was 0x%04hx, calculated 0x%04hx\n",
1080                   checksum_reg, checksum);
1081
1082         return -E1000_ERR_EEPROM;
1083 }
1084 #endif /* CONFIG_E1000_NO_NVM */
1085
1086 /*****************************************************************************
1087  * Set PHY to class A mode
1088  * Assumes the following operations will follow to enable the new class mode.
1089  *  1. Do a PHY soft reset
1090  *  2. Restart auto-negotiation or force link.
1091  *
1092  * hw - Struct containing variables accessed by shared code
1093  ****************************************************************************/
1094 static int32_t
1095 e1000_set_phy_mode(struct e1000_hw *hw)
1096 {
1097 #ifndef CONFIG_E1000_NO_NVM
1098         int32_t ret_val;
1099         uint16_t eeprom_data;
1100
1101         DEBUGFUNC();
1102
1103         if ((hw->mac_type == e1000_82545_rev_3) &&
1104                 (hw->media_type == e1000_media_type_copper)) {
1105                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1106                                 1, &eeprom_data);
1107                 if (ret_val)
1108                         return ret_val;
1109
1110                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1111                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
1112                         ret_val = e1000_write_phy_reg(hw,
1113                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
1114                         if (ret_val)
1115                                 return ret_val;
1116                         ret_val = e1000_write_phy_reg(hw,
1117                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
1118                         if (ret_val)
1119                                 return ret_val;
1120
1121                         hw->phy_reset_disable = false;
1122                 }
1123         }
1124 #endif
1125         return E1000_SUCCESS;
1126 }
1127
1128 #ifndef CONFIG_E1000_NO_NVM
1129 /***************************************************************************
1130  *
1131  * Obtaining software semaphore bit (SMBI) before resetting PHY.
1132  *
1133  * hw: Struct containing variables accessed by shared code
1134  *
1135  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1136  *            E1000_SUCCESS at any other case.
1137  *
1138  ***************************************************************************/
1139 static int32_t
1140 e1000_get_software_semaphore(struct e1000_hw *hw)
1141 {
1142          int32_t timeout = hw->eeprom.word_size + 1;
1143          uint32_t swsm;
1144
1145         DEBUGFUNC();
1146
1147         if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
1148                 return E1000_SUCCESS;
1149
1150         while (timeout) {
1151                 swsm = E1000_READ_REG(hw, SWSM);
1152                 /* If SMBI bit cleared, it is now set and we hold
1153                  * the semaphore */
1154                 if (!(swsm & E1000_SWSM_SMBI))
1155                         break;
1156                 mdelay(1);
1157                 timeout--;
1158         }
1159
1160         if (!timeout) {
1161                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1162                 return -E1000_ERR_RESET;
1163         }
1164
1165         return E1000_SUCCESS;
1166 }
1167 #endif
1168
1169 /***************************************************************************
1170  * This function clears HW semaphore bits.
1171  *
1172  * hw: Struct containing variables accessed by shared code
1173  *
1174  * returns: - None.
1175  *
1176  ***************************************************************************/
1177 static void
1178 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1179 {
1180 #ifndef CONFIG_E1000_NO_NVM
1181          uint32_t swsm;
1182
1183         DEBUGFUNC();
1184
1185         if (!hw->eeprom_semaphore_present)
1186                 return;
1187
1188         swsm = E1000_READ_REG(hw, SWSM);
1189         if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1190                 /* Release both semaphores. */
1191                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1192         } else
1193                 swsm &= ~(E1000_SWSM_SWESMBI);
1194         E1000_WRITE_REG(hw, SWSM, swsm);
1195 #endif
1196 }
1197
1198 /***************************************************************************
1199  *
1200  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1201  * adapter or Eeprom access.
1202  *
1203  * hw: Struct containing variables accessed by shared code
1204  *
1205  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1206  *            E1000_SUCCESS at any other case.
1207  *
1208  ***************************************************************************/
1209 static int32_t
1210 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1211 {
1212 #ifndef CONFIG_E1000_NO_NVM
1213         int32_t timeout;
1214         uint32_t swsm;
1215
1216         DEBUGFUNC();
1217
1218         if (!hw->eeprom_semaphore_present)
1219                 return E1000_SUCCESS;
1220
1221         if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1222                 /* Get the SW semaphore. */
1223                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1224                         return -E1000_ERR_EEPROM;
1225         }
1226
1227         /* Get the FW semaphore. */
1228         timeout = hw->eeprom.word_size + 1;
1229         while (timeout) {
1230                 swsm = E1000_READ_REG(hw, SWSM);
1231                 swsm |= E1000_SWSM_SWESMBI;
1232                 E1000_WRITE_REG(hw, SWSM, swsm);
1233                 /* if we managed to set the bit we got the semaphore. */
1234                 swsm = E1000_READ_REG(hw, SWSM);
1235                 if (swsm & E1000_SWSM_SWESMBI)
1236                         break;
1237
1238                 udelay(50);
1239                 timeout--;
1240         }
1241
1242         if (!timeout) {
1243                 /* Release semaphores */
1244                 e1000_put_hw_eeprom_semaphore(hw);
1245                 DEBUGOUT("Driver can't access the Eeprom - "
1246                                 "SWESMBI bit is set.\n");
1247                 return -E1000_ERR_EEPROM;
1248         }
1249 #endif
1250         return E1000_SUCCESS;
1251 }
1252
1253 /* Take ownership of the PHY */
1254 static int32_t
1255 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1256 {
1257         uint32_t swfw_sync = 0;
1258         uint32_t swmask = mask;
1259         uint32_t fwmask = mask << 16;
1260         int32_t timeout = 200;
1261
1262         DEBUGFUNC();
1263         while (timeout) {
1264                 if (e1000_get_hw_eeprom_semaphore(hw))
1265                         return -E1000_ERR_SWFW_SYNC;
1266
1267                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1268                 if (!(swfw_sync & (fwmask | swmask)))
1269                         break;
1270
1271                 /* firmware currently using resource (fwmask) */
1272                 /* or other software thread currently using resource (swmask) */
1273                 e1000_put_hw_eeprom_semaphore(hw);
1274                 mdelay(5);
1275                 timeout--;
1276         }
1277
1278         if (!timeout) {
1279                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1280                 return -E1000_ERR_SWFW_SYNC;
1281         }
1282
1283         swfw_sync |= swmask;
1284         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1285
1286         e1000_put_hw_eeprom_semaphore(hw);
1287         return E1000_SUCCESS;
1288 }
1289
1290 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1291 {
1292         uint32_t swfw_sync = 0;
1293
1294         DEBUGFUNC();
1295         while (e1000_get_hw_eeprom_semaphore(hw))
1296                 ; /* Empty */
1297
1298         swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1299         swfw_sync &= ~mask;
1300         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1301
1302         e1000_put_hw_eeprom_semaphore(hw);
1303 }
1304
1305 static bool e1000_is_second_port(struct e1000_hw *hw)
1306 {
1307         switch (hw->mac_type) {
1308         case e1000_80003es2lan:
1309         case e1000_82546:
1310         case e1000_82571:
1311                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1312                         return true;
1313                 /* Fallthrough */
1314         default:
1315                 return false;
1316         }
1317 }
1318
1319 #ifndef CONFIG_E1000_NO_NVM
1320 /******************************************************************************
1321  * Reads the adapter's MAC address from the EEPROM
1322  *
1323  * hw - Struct containing variables accessed by shared code
1324  * enetaddr - buffering where the MAC address will be stored
1325  *****************************************************************************/
1326 static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
1327                                            unsigned char enetaddr[6])
1328 {
1329         uint16_t offset;
1330         uint16_t eeprom_data;
1331         int i;
1332
1333         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1334                 offset = i >> 1;
1335                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1336                         DEBUGOUT("EEPROM Read Error\n");
1337                         return -E1000_ERR_EEPROM;
1338                 }
1339                 enetaddr[i] = eeprom_data & 0xff;
1340                 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1341         }
1342
1343         return 0;
1344 }
1345
1346 /******************************************************************************
1347  * Reads the adapter's MAC address from the RAL/RAH registers
1348  *
1349  * hw - Struct containing variables accessed by shared code
1350  * enetaddr - buffering where the MAC address will be stored
1351  *****************************************************************************/
1352 static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
1353                                          unsigned char enetaddr[6])
1354 {
1355         uint16_t offset, tmp;
1356         uint32_t reg_data = 0;
1357         int i;
1358
1359         if (hw->mac_type != e1000_igb)
1360                 return -E1000_ERR_MAC_TYPE;
1361
1362         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1363                 offset = i >> 1;
1364
1365                 if (offset == 0)
1366                         reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1367                 else if (offset == 1)
1368                         reg_data >>= 16;
1369                 else if (offset == 2)
1370                         reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1371                 tmp = reg_data & 0xffff;
1372
1373                 enetaddr[i] = tmp & 0xff;
1374                 enetaddr[i + 1] = (tmp >> 8) & 0xff;
1375         }
1376
1377         return 0;
1378 }
1379
1380 /******************************************************************************
1381  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1382  * second function of dual function devices
1383  *
1384  * hw - Struct containing variables accessed by shared code
1385  * enetaddr - buffering where the MAC address will be stored
1386  *****************************************************************************/
1387 static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1388 {
1389         int ret_val;
1390
1391         if (hw->mac_type == e1000_igb) {
1392                 /* i210 preloads MAC address into RAL/RAH registers */
1393                 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1394         } else {
1395                 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1396         }
1397         if (ret_val)
1398                 return ret_val;
1399
1400         /* Invert the last bit if this is the second device */
1401         if (e1000_is_second_port(hw))
1402                 enetaddr[5] ^= 1;
1403
1404         return 0;
1405 }
1406 #endif
1407
1408 /******************************************************************************
1409  * Initializes receive address filters.
1410  *
1411  * hw - Struct containing variables accessed by shared code
1412  *
1413  * Places the MAC address in receive address register 0 and clears the rest
1414  * of the receive addresss registers. Clears the multicast table. Assumes
1415  * the receiver is in reset when the routine is called.
1416  *****************************************************************************/
1417 static void
1418 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1419 {
1420         uint32_t i;
1421         uint32_t addr_low;
1422         uint32_t addr_high;
1423
1424         DEBUGFUNC();
1425
1426         /* Setup the receive address. */
1427         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1428         addr_low = (enetaddr[0] |
1429                     (enetaddr[1] << 8) |
1430                     (enetaddr[2] << 16) | (enetaddr[3] << 24));
1431
1432         addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1433
1434         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1435         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1436
1437         /* Zero out the other 15 receive addresses. */
1438         DEBUGOUT("Clearing RAR[1-15]\n");
1439         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1440                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1441                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1442         }
1443 }
1444
1445 /******************************************************************************
1446  * Clears the VLAN filer table
1447  *
1448  * hw - Struct containing variables accessed by shared code
1449  *****************************************************************************/
1450 static void
1451 e1000_clear_vfta(struct e1000_hw *hw)
1452 {
1453         uint32_t offset;
1454
1455         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1456                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1457 }
1458
1459 /******************************************************************************
1460  * Set the mac type member in the hw struct.
1461  *
1462  * hw - Struct containing variables accessed by shared code
1463  *****************************************************************************/
1464 int32_t
1465 e1000_set_mac_type(struct e1000_hw *hw)
1466 {
1467         DEBUGFUNC();
1468
1469         switch (hw->device_id) {
1470         case E1000_DEV_ID_82542:
1471                 switch (hw->revision_id) {
1472                 case E1000_82542_2_0_REV_ID:
1473                         hw->mac_type = e1000_82542_rev2_0;
1474                         break;
1475                 case E1000_82542_2_1_REV_ID:
1476                         hw->mac_type = e1000_82542_rev2_1;
1477                         break;
1478                 default:
1479                         /* Invalid 82542 revision ID */
1480                         return -E1000_ERR_MAC_TYPE;
1481                 }
1482                 break;
1483         case E1000_DEV_ID_82543GC_FIBER:
1484         case E1000_DEV_ID_82543GC_COPPER:
1485                 hw->mac_type = e1000_82543;
1486                 break;
1487         case E1000_DEV_ID_82544EI_COPPER:
1488         case E1000_DEV_ID_82544EI_FIBER:
1489         case E1000_DEV_ID_82544GC_COPPER:
1490         case E1000_DEV_ID_82544GC_LOM:
1491                 hw->mac_type = e1000_82544;
1492                 break;
1493         case E1000_DEV_ID_82540EM:
1494         case E1000_DEV_ID_82540EM_LOM:
1495         case E1000_DEV_ID_82540EP:
1496         case E1000_DEV_ID_82540EP_LOM:
1497         case E1000_DEV_ID_82540EP_LP:
1498                 hw->mac_type = e1000_82540;
1499                 break;
1500         case E1000_DEV_ID_82545EM_COPPER:
1501         case E1000_DEV_ID_82545EM_FIBER:
1502                 hw->mac_type = e1000_82545;
1503                 break;
1504         case E1000_DEV_ID_82545GM_COPPER:
1505         case E1000_DEV_ID_82545GM_FIBER:
1506         case E1000_DEV_ID_82545GM_SERDES:
1507                 hw->mac_type = e1000_82545_rev_3;
1508                 break;
1509         case E1000_DEV_ID_82546EB_COPPER:
1510         case E1000_DEV_ID_82546EB_FIBER:
1511         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1512                 hw->mac_type = e1000_82546;
1513                 break;
1514         case E1000_DEV_ID_82546GB_COPPER:
1515         case E1000_DEV_ID_82546GB_FIBER:
1516         case E1000_DEV_ID_82546GB_SERDES:
1517         case E1000_DEV_ID_82546GB_PCIE:
1518         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1519         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1520                 hw->mac_type = e1000_82546_rev_3;
1521                 break;
1522         case E1000_DEV_ID_82541EI:
1523         case E1000_DEV_ID_82541EI_MOBILE:
1524         case E1000_DEV_ID_82541ER_LOM:
1525                 hw->mac_type = e1000_82541;
1526                 break;
1527         case E1000_DEV_ID_82541ER:
1528         case E1000_DEV_ID_82541GI:
1529         case E1000_DEV_ID_82541GI_LF:
1530         case E1000_DEV_ID_82541GI_MOBILE:
1531                 hw->mac_type = e1000_82541_rev_2;
1532                 break;
1533         case E1000_DEV_ID_82547EI:
1534         case E1000_DEV_ID_82547EI_MOBILE:
1535                 hw->mac_type = e1000_82547;
1536                 break;
1537         case E1000_DEV_ID_82547GI:
1538                 hw->mac_type = e1000_82547_rev_2;
1539                 break;
1540         case E1000_DEV_ID_82571EB_COPPER:
1541         case E1000_DEV_ID_82571EB_FIBER:
1542         case E1000_DEV_ID_82571EB_SERDES:
1543         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1544         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1545         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1546         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1547         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1548         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1549                 hw->mac_type = e1000_82571;
1550                 break;
1551         case E1000_DEV_ID_82572EI_COPPER:
1552         case E1000_DEV_ID_82572EI_FIBER:
1553         case E1000_DEV_ID_82572EI_SERDES:
1554         case E1000_DEV_ID_82572EI:
1555                 hw->mac_type = e1000_82572;
1556                 break;
1557         case E1000_DEV_ID_82573E:
1558         case E1000_DEV_ID_82573E_IAMT:
1559         case E1000_DEV_ID_82573L:
1560                 hw->mac_type = e1000_82573;
1561                 break;
1562         case E1000_DEV_ID_82574L:
1563                 hw->mac_type = e1000_82574;
1564                 break;
1565         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1566         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1567         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1568         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1569                 hw->mac_type = e1000_80003es2lan;
1570                 break;
1571         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1572         case E1000_DEV_ID_ICH8_IGP_AMT:
1573         case E1000_DEV_ID_ICH8_IGP_C:
1574         case E1000_DEV_ID_ICH8_IFE:
1575         case E1000_DEV_ID_ICH8_IFE_GT:
1576         case E1000_DEV_ID_ICH8_IFE_G:
1577         case E1000_DEV_ID_ICH8_IGP_M:
1578                 hw->mac_type = e1000_ich8lan;
1579                 break;
1580         case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1581         case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1582         case PCI_DEVICE_ID_INTEL_I210_COPPER:
1583         case PCI_DEVICE_ID_INTEL_I211_COPPER:
1584         case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1585         case PCI_DEVICE_ID_INTEL_I210_SERDES:
1586         case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1587         case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1588                 hw->mac_type = e1000_igb;
1589                 break;
1590         default:
1591                 /* Should never have loaded on this device */
1592                 return -E1000_ERR_MAC_TYPE;
1593         }
1594         return E1000_SUCCESS;
1595 }
1596
1597 /******************************************************************************
1598  * Reset the transmit and receive units; mask and clear all interrupts.
1599  *
1600  * hw - Struct containing variables accessed by shared code
1601  *****************************************************************************/
1602 void
1603 e1000_reset_hw(struct e1000_hw *hw)
1604 {
1605         uint32_t ctrl;
1606         uint32_t ctrl_ext;
1607         uint32_t manc;
1608         uint32_t pba = 0;
1609         uint32_t reg;
1610
1611         DEBUGFUNC();
1612
1613         /* get the correct pba value for both PCI and PCIe*/
1614         if (hw->mac_type <  e1000_82571)
1615                 pba = E1000_DEFAULT_PCI_PBA;
1616         else
1617                 pba = E1000_DEFAULT_PCIE_PBA;
1618
1619         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1620         if (hw->mac_type == e1000_82542_rev2_0) {
1621                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1622 #ifdef CONFIG_DM_ETH
1623                 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1624                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1625 #else
1626                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1627                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1628 #endif
1629         }
1630
1631         /* Clear interrupt mask to stop board from generating interrupts */
1632         DEBUGOUT("Masking off all interrupts\n");
1633         if (hw->mac_type == e1000_igb)
1634                 E1000_WRITE_REG(hw, I210_IAM, 0);
1635         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1636
1637         /* Disable the Transmit and Receive units.  Then delay to allow
1638          * any pending transactions to complete before we hit the MAC with
1639          * the global reset.
1640          */
1641         E1000_WRITE_REG(hw, RCTL, 0);
1642         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1643         E1000_WRITE_FLUSH(hw);
1644
1645         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1646         hw->tbi_compatibility_on = false;
1647
1648         /* Delay to allow any outstanding PCI transactions to complete before
1649          * resetting the device
1650          */
1651         mdelay(10);
1652
1653         /* Issue a global reset to the MAC.  This will reset the chip's
1654          * transmit, receive, DMA, and link units.  It will not effect
1655          * the current PCI configuration.  The global reset bit is self-
1656          * clearing, and should clear within a microsecond.
1657          */
1658         DEBUGOUT("Issuing a global reset to MAC\n");
1659         ctrl = E1000_READ_REG(hw, CTRL);
1660
1661         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1662
1663         /* Force a reload from the EEPROM if necessary */
1664         if (hw->mac_type == e1000_igb) {
1665                 mdelay(20);
1666                 reg = E1000_READ_REG(hw, STATUS);
1667                 if (reg & E1000_STATUS_PF_RST_DONE)
1668                         DEBUGOUT("PF OK\n");
1669                 reg = E1000_READ_REG(hw, I210_EECD);
1670                 if (reg & E1000_EECD_AUTO_RD)
1671                         DEBUGOUT("EEC OK\n");
1672         } else if (hw->mac_type < e1000_82540) {
1673                 /* Wait for reset to complete */
1674                 udelay(10);
1675                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1676                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1677                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1678                 E1000_WRITE_FLUSH(hw);
1679                 /* Wait for EEPROM reload */
1680                 mdelay(2);
1681         } else {
1682                 /* Wait for EEPROM reload (it happens automatically) */
1683                 mdelay(4);
1684                 /* Dissable HW ARPs on ASF enabled adapters */
1685                 manc = E1000_READ_REG(hw, MANC);
1686                 manc &= ~(E1000_MANC_ARP_EN);
1687                 E1000_WRITE_REG(hw, MANC, manc);
1688         }
1689
1690         /* Clear interrupt mask to stop board from generating interrupts */
1691         DEBUGOUT("Masking off all interrupts\n");
1692         if (hw->mac_type == e1000_igb)
1693                 E1000_WRITE_REG(hw, I210_IAM, 0);
1694         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1695
1696         /* Clear any pending interrupt events. */
1697         E1000_READ_REG(hw, ICR);
1698
1699         /* If MWI was previously enabled, reenable it. */
1700         if (hw->mac_type == e1000_82542_rev2_0) {
1701 #ifdef CONFIG_DM_ETH
1702                 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1703 #else
1704                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1705 #endif
1706         }
1707         if (hw->mac_type != e1000_igb)
1708                 E1000_WRITE_REG(hw, PBA, pba);
1709 }
1710
1711 /******************************************************************************
1712  *
1713  * Initialize a number of hardware-dependent bits
1714  *
1715  * hw: Struct containing variables accessed by shared code
1716  *
1717  * This function contains hardware limitation workarounds for PCI-E adapters
1718  *
1719  *****************************************************************************/
1720 static void
1721 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1722 {
1723         if ((hw->mac_type >= e1000_82571) &&
1724                         (!hw->initialize_hw_bits_disable)) {
1725                 /* Settings common to all PCI-express silicon */
1726                 uint32_t reg_ctrl, reg_ctrl_ext;
1727                 uint32_t reg_tarc0, reg_tarc1;
1728                 uint32_t reg_tctl;
1729                 uint32_t reg_txdctl, reg_txdctl1;
1730
1731                 /* link autonegotiation/sync workarounds */
1732                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1733                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1734
1735                 /* Enable not-done TX descriptor counting */
1736                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1737                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1738                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1739
1740                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1741                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1742                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1743
1744
1745                 switch (hw->mac_type) {
1746                 case e1000_igb:                 /* IGB is cool */
1747                         return;
1748                 case e1000_82571:
1749                 case e1000_82572:
1750                         /* Clear PHY TX compatible mode bits */
1751                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1752                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1753
1754                         /* link autonegotiation/sync workarounds */
1755                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1756
1757                         /* TX ring control fixes */
1758                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1759
1760                         /* Multiple read bit is reversed polarity */
1761                         reg_tctl = E1000_READ_REG(hw, TCTL);
1762                         if (reg_tctl & E1000_TCTL_MULR)
1763                                 reg_tarc1 &= ~(1 << 28);
1764                         else
1765                                 reg_tarc1 |= (1 << 28);
1766
1767                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1768                         break;
1769                 case e1000_82573:
1770                 case e1000_82574:
1771                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1772                         reg_ctrl_ext &= ~(1 << 23);
1773                         reg_ctrl_ext |= (1 << 22);
1774
1775                         /* TX byte count fix */
1776                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1777                         reg_ctrl &= ~(1 << 29);
1778
1779                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1780                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1781                         break;
1782                 case e1000_80003es2lan:
1783         /* improve small packet performace for fiber/serdes */
1784                         if ((hw->media_type == e1000_media_type_fiber)
1785                         || (hw->media_type ==
1786                                 e1000_media_type_internal_serdes)) {
1787                                 reg_tarc0 &= ~(1 << 20);
1788                         }
1789
1790                 /* Multiple read bit is reversed polarity */
1791                         reg_tctl = E1000_READ_REG(hw, TCTL);
1792                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1793                         if (reg_tctl & E1000_TCTL_MULR)
1794                                 reg_tarc1 &= ~(1 << 28);
1795                         else
1796                                 reg_tarc1 |= (1 << 28);
1797
1798                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1799                         break;
1800                 case e1000_ich8lan:
1801                         /* Reduce concurrent DMA requests to 3 from 4 */
1802                         if ((hw->revision_id < 3) ||
1803                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1804                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1805                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1806
1807                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1808                         reg_ctrl_ext |= (1 << 22);
1809                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1810
1811                         /* workaround TX hang with TSO=on */
1812                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1813
1814                         /* Multiple read bit is reversed polarity */
1815                         reg_tctl = E1000_READ_REG(hw, TCTL);
1816                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1817                         if (reg_tctl & E1000_TCTL_MULR)
1818                                 reg_tarc1 &= ~(1 << 28);
1819                         else
1820                                 reg_tarc1 |= (1 << 28);
1821
1822                         /* workaround TX hang with TSO=on */
1823                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1824
1825                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1826                         break;
1827                 default:
1828                         break;
1829                 }
1830
1831                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1832         }
1833 }
1834
1835 /******************************************************************************
1836  * Performs basic configuration of the adapter.
1837  *
1838  * hw - Struct containing variables accessed by shared code
1839  *
1840  * Assumes that the controller has previously been reset and is in a
1841  * post-reset uninitialized state. Initializes the receive address registers,
1842  * multicast table, and VLAN filter table. Calls routines to setup link
1843  * configuration and flow control settings. Clears all on-chip counters. Leaves
1844  * the transmit and receive units disabled and uninitialized.
1845  *****************************************************************************/
1846 static int
1847 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1848 {
1849         uint32_t ctrl;
1850         uint32_t i;
1851         int32_t ret_val;
1852         uint16_t pcix_cmd_word;
1853         uint16_t pcix_stat_hi_word;
1854         uint16_t cmd_mmrbc;
1855         uint16_t stat_mmrbc;
1856         uint32_t mta_size;
1857         uint32_t reg_data;
1858         uint32_t ctrl_ext;
1859         DEBUGFUNC();
1860         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1861         if ((hw->mac_type == e1000_ich8lan) &&
1862                 ((hw->revision_id < 3) ||
1863                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1864                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1865                         reg_data = E1000_READ_REG(hw, STATUS);
1866                         reg_data &= ~0x80000000;
1867                         E1000_WRITE_REG(hw, STATUS, reg_data);
1868         }
1869         /* Do not need initialize Identification LED */
1870
1871         /* Set the media type and TBI compatibility */
1872         e1000_set_media_type(hw);
1873
1874         /* Must be called after e1000_set_media_type
1875          * because media_type is used */
1876         e1000_initialize_hardware_bits(hw);
1877
1878         /* Disabling VLAN filtering. */
1879         DEBUGOUT("Initializing the IEEE VLAN\n");
1880         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1881         if (hw->mac_type != e1000_ich8lan) {
1882                 if (hw->mac_type < e1000_82545_rev_3)
1883                         E1000_WRITE_REG(hw, VET, 0);
1884                 e1000_clear_vfta(hw);
1885         }
1886
1887         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1888         if (hw->mac_type == e1000_82542_rev2_0) {
1889                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1890 #ifdef CONFIG_DM_ETH
1891                 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1892                                       hw->
1893                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1894 #else
1895                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1896                                       hw->
1897                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1898 #endif
1899                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1900                 E1000_WRITE_FLUSH(hw);
1901                 mdelay(5);
1902         }
1903
1904         /* Setup the receive address. This involves initializing all of the Receive
1905          * Address Registers (RARs 0 - 15).
1906          */
1907         e1000_init_rx_addrs(hw, enetaddr);
1908
1909         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1910         if (hw->mac_type == e1000_82542_rev2_0) {
1911                 E1000_WRITE_REG(hw, RCTL, 0);
1912                 E1000_WRITE_FLUSH(hw);
1913                 mdelay(1);
1914 #ifdef CONFIG_DM_ETH
1915                 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1916 #else
1917                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1918 #endif
1919         }
1920
1921         /* Zero out the Multicast HASH table */
1922         DEBUGOUT("Zeroing the MTA\n");
1923         mta_size = E1000_MC_TBL_SIZE;
1924         if (hw->mac_type == e1000_ich8lan)
1925                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1926         for (i = 0; i < mta_size; i++) {
1927                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1928                 /* use write flush to prevent Memory Write Block (MWB) from
1929                  * occuring when accessing our register space */
1930                 E1000_WRITE_FLUSH(hw);
1931         }
1932
1933         switch (hw->mac_type) {
1934         case e1000_82545_rev_3:
1935         case e1000_82546_rev_3:
1936         case e1000_igb:
1937                 break;
1938         default:
1939         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1940         if (hw->bus_type == e1000_bus_type_pcix) {
1941 #ifdef CONFIG_DM_ETH
1942                 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1943                                      &pcix_cmd_word);
1944                 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1945                                      &pcix_stat_hi_word);
1946 #else
1947                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1948                                      &pcix_cmd_word);
1949                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1950                                      &pcix_stat_hi_word);
1951 #endif
1952                 cmd_mmrbc =
1953                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1954                     PCIX_COMMAND_MMRBC_SHIFT;
1955                 stat_mmrbc =
1956                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1957                     PCIX_STATUS_HI_MMRBC_SHIFT;
1958                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1959                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1960                 if (cmd_mmrbc > stat_mmrbc) {
1961                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1962                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1963 #ifdef CONFIG_DM_ETH
1964                         dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1965                                               pcix_cmd_word);
1966 #else
1967                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1968                                               pcix_cmd_word);
1969 #endif
1970                 }
1971         }
1972                 break;
1973         }
1974
1975         /* More time needed for PHY to initialize */
1976         if (hw->mac_type == e1000_ich8lan)
1977                 mdelay(15);
1978         if (hw->mac_type == e1000_igb)
1979                 mdelay(15);
1980
1981         /* Call a subroutine to configure the link and setup flow control. */
1982         ret_val = e1000_setup_link(hw);
1983
1984         /* Set the transmit descriptor write-back policy */
1985         if (hw->mac_type > e1000_82544) {
1986                 ctrl = E1000_READ_REG(hw, TXDCTL);
1987                 ctrl =
1988                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1989                     E1000_TXDCTL_FULL_TX_DESC_WB;
1990                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1991         }
1992
1993         /* Set the receive descriptor write back policy */
1994         if (hw->mac_type >= e1000_82571) {
1995                 ctrl = E1000_READ_REG(hw, RXDCTL);
1996                 ctrl =
1997                     (ctrl & ~E1000_RXDCTL_WTHRESH) |
1998                     E1000_RXDCTL_FULL_RX_DESC_WB;
1999                 E1000_WRITE_REG(hw, RXDCTL, ctrl);
2000         }
2001
2002         switch (hw->mac_type) {
2003         default:
2004                 break;
2005         case e1000_80003es2lan:
2006                 /* Enable retransmit on late collisions */
2007                 reg_data = E1000_READ_REG(hw, TCTL);
2008                 reg_data |= E1000_TCTL_RTLC;
2009                 E1000_WRITE_REG(hw, TCTL, reg_data);
2010
2011                 /* Configure Gigabit Carry Extend Padding */
2012                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
2013                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
2014                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
2015                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
2016
2017                 /* Configure Transmit Inter-Packet Gap */
2018                 reg_data = E1000_READ_REG(hw, TIPG);
2019                 reg_data &= ~E1000_TIPG_IPGT_MASK;
2020                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2021                 E1000_WRITE_REG(hw, TIPG, reg_data);
2022
2023                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
2024                 reg_data &= ~0x00100000;
2025                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
2026                 /* Fall through */
2027         case e1000_82571:
2028         case e1000_82572:
2029         case e1000_ich8lan:
2030                 ctrl = E1000_READ_REG(hw, TXDCTL1);
2031                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
2032                         | E1000_TXDCTL_FULL_TX_DESC_WB;
2033                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
2034                 break;
2035         case e1000_82573:
2036         case e1000_82574:
2037                 reg_data = E1000_READ_REG(hw, GCR);
2038                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2039                 E1000_WRITE_REG(hw, GCR, reg_data);
2040         case e1000_igb:
2041                 break;
2042         }
2043
2044         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
2045                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
2046                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2047                 /* Relaxed ordering must be disabled to avoid a parity
2048                  * error crash in a PCI slot. */
2049                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2050                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2051         }
2052
2053         return ret_val;
2054 }
2055
2056 /******************************************************************************
2057  * Configures flow control and link settings.
2058  *
2059  * hw - Struct containing variables accessed by shared code
2060  *
2061  * Determines which flow control settings to use. Calls the apropriate media-
2062  * specific link configuration function. Configures the flow control settings.
2063  * Assuming the adapter has a valid link partner, a valid link should be
2064  * established. Assumes the hardware has previously been reset and the
2065  * transmitter and receiver are not enabled.
2066  *****************************************************************************/
2067 static int
2068 e1000_setup_link(struct e1000_hw *hw)
2069 {
2070         int32_t ret_val;
2071 #ifndef CONFIG_E1000_NO_NVM
2072         uint32_t ctrl_ext;
2073         uint16_t eeprom_data;
2074 #endif
2075
2076         DEBUGFUNC();
2077
2078         /* In the case of the phy reset being blocked, we already have a link.
2079          * We do not have to set it up again. */
2080         if (e1000_check_phy_reset_block(hw))
2081                 return E1000_SUCCESS;
2082
2083 #ifndef CONFIG_E1000_NO_NVM
2084         /* Read and store word 0x0F of the EEPROM. This word contains bits
2085          * that determine the hardware's default PAUSE (flow control) mode,
2086          * a bit that determines whether the HW defaults to enabling or
2087          * disabling auto-negotiation, and the direction of the
2088          * SW defined pins. If there is no SW over-ride of the flow
2089          * control setting, then the variable hw->fc will
2090          * be initialized based on a value in the EEPROM.
2091          */
2092         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2093                                 &eeprom_data) < 0) {
2094                 DEBUGOUT("EEPROM Read Error\n");
2095                 return -E1000_ERR_EEPROM;
2096         }
2097 #endif
2098         if (hw->fc == e1000_fc_default) {
2099                 switch (hw->mac_type) {
2100                 case e1000_ich8lan:
2101                 case e1000_82573:
2102                 case e1000_82574:
2103                 case e1000_igb:
2104                         hw->fc = e1000_fc_full;
2105                         break;
2106                 default:
2107 #ifndef CONFIG_E1000_NO_NVM
2108                         ret_val = e1000_read_eeprom(hw,
2109                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2110                         if (ret_val) {
2111                                 DEBUGOUT("EEPROM Read Error\n");
2112                                 return -E1000_ERR_EEPROM;
2113                         }
2114                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2115                                 hw->fc = e1000_fc_none;
2116                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2117                                     EEPROM_WORD0F_ASM_DIR)
2118                                 hw->fc = e1000_fc_tx_pause;
2119                         else
2120 #endif
2121                                 hw->fc = e1000_fc_full;
2122                         break;
2123                 }
2124         }
2125
2126         /* We want to save off the original Flow Control configuration just
2127          * in case we get disconnected and then reconnected into a different
2128          * hub or switch with different Flow Control capabilities.
2129          */
2130         if (hw->mac_type == e1000_82542_rev2_0)
2131                 hw->fc &= (~e1000_fc_tx_pause);
2132
2133         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2134                 hw->fc &= (~e1000_fc_rx_pause);
2135
2136         hw->original_fc = hw->fc;
2137
2138         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2139
2140 #ifndef CONFIG_E1000_NO_NVM
2141         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
2142          * polarity value for the SW controlled pins, and setup the
2143          * Extended Device Control reg with that info.
2144          * This is needed because one of the SW controlled pins is used for
2145          * signal detection.  So this should be done before e1000_setup_pcs_link()
2146          * or e1000_phy_setup() is called.
2147          */
2148         if (hw->mac_type == e1000_82543) {
2149                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2150                             SWDPIO__EXT_SHIFT);
2151                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2152         }
2153 #endif
2154
2155         /* Call the necessary subroutine to configure the link. */
2156         ret_val = (hw->media_type == e1000_media_type_fiber) ?
2157             e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
2158         if (ret_val < 0) {
2159                 return ret_val;
2160         }
2161
2162         /* Initialize the flow control address, type, and PAUSE timer
2163          * registers to their default values.  This is done even if flow
2164          * control is disabled, because it does not hurt anything to
2165          * initialize these registers.
2166          */
2167         DEBUGOUT("Initializing the Flow Control address, type"
2168                         "and timer regs\n");
2169
2170         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
2171         if (hw->mac_type != e1000_ich8lan) {
2172                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2173                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2174                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2175         }
2176
2177         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2178
2179         /* Set the flow control receive threshold registers.  Normally,
2180          * these registers will be set to a default threshold that may be
2181          * adjusted later by the driver's runtime code.  However, if the
2182          * ability to transmit pause frames in not enabled, then these
2183          * registers will be set to 0.
2184          */
2185         if (!(hw->fc & e1000_fc_tx_pause)) {
2186                 E1000_WRITE_REG(hw, FCRTL, 0);
2187                 E1000_WRITE_REG(hw, FCRTH, 0);
2188         } else {
2189                 /* We need to set up the Receive Threshold high and low water marks
2190                  * as well as (optionally) enabling the transmission of XON frames.
2191                  */
2192                 if (hw->fc_send_xon) {
2193                         E1000_WRITE_REG(hw, FCRTL,
2194                                         (hw->fc_low_water | E1000_FCRTL_XONE));
2195                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2196                 } else {
2197                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2198                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2199                 }
2200         }
2201         return ret_val;
2202 }
2203
2204 /******************************************************************************
2205  * Sets up link for a fiber based adapter
2206  *
2207  * hw - Struct containing variables accessed by shared code
2208  *
2209  * Manipulates Physical Coding Sublayer functions in order to configure
2210  * link. Assumes the hardware has been previously reset and the transmitter
2211  * and receiver are not enabled.
2212  *****************************************************************************/
2213 static int
2214 e1000_setup_fiber_link(struct e1000_hw *hw)
2215 {
2216         uint32_t ctrl;
2217         uint32_t status;
2218         uint32_t txcw = 0;
2219         uint32_t i;
2220         uint32_t signal;
2221         int32_t ret_val;
2222
2223         DEBUGFUNC();
2224         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2225          * set when the optics detect a signal. On older adapters, it will be
2226          * cleared when there is a signal
2227          */
2228         ctrl = E1000_READ_REG(hw, CTRL);
2229         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2230                 signal = E1000_CTRL_SWDPIN1;
2231         else
2232                 signal = 0;
2233
2234         printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2235                ctrl);
2236         /* Take the link out of reset */
2237         ctrl &= ~(E1000_CTRL_LRST);
2238
2239         e1000_config_collision_dist(hw);
2240
2241         /* Check for a software override of the flow control settings, and setup
2242          * the device accordingly.  If auto-negotiation is enabled, then software
2243          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2244          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2245          * auto-negotiation is disabled, then software will have to manually
2246          * configure the two flow control enable bits in the CTRL register.
2247          *
2248          * The possible values of the "fc" parameter are:
2249          *      0:  Flow control is completely disabled
2250          *      1:  Rx flow control is enabled (we can receive pause frames, but
2251          *          not send pause frames).
2252          *      2:  Tx flow control is enabled (we can send pause frames but we do
2253          *          not support receiving pause frames).
2254          *      3:  Both Rx and TX flow control (symmetric) are enabled.
2255          */
2256         switch (hw->fc) {
2257         case e1000_fc_none:
2258                 /* Flow control is completely disabled by a software over-ride. */
2259                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2260                 break;
2261         case e1000_fc_rx_pause:
2262                 /* RX Flow control is enabled and TX Flow control is disabled by a
2263                  * software over-ride. Since there really isn't a way to advertise
2264                  * that we are capable of RX Pause ONLY, we will advertise that we
2265                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2266                  *  disable the adapter's ability to send PAUSE frames.
2267                  */
2268                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2269                 break;
2270         case e1000_fc_tx_pause:
2271                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2272                  * software over-ride.
2273                  */
2274                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2275                 break;
2276         case e1000_fc_full:
2277                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2278                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2279                 break;
2280         default:
2281                 DEBUGOUT("Flow control param set incorrectly\n");
2282                 return -E1000_ERR_CONFIG;
2283                 break;
2284         }
2285
2286         /* Since auto-negotiation is enabled, take the link out of reset (the link
2287          * will be in reset, because we previously reset the chip). This will
2288          * restart auto-negotiation.  If auto-neogtiation is successful then the
2289          * link-up status bit will be set and the flow control enable bits (RFCE
2290          * and TFCE) will be set according to their negotiated value.
2291          */
2292         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2293
2294         E1000_WRITE_REG(hw, TXCW, txcw);
2295         E1000_WRITE_REG(hw, CTRL, ctrl);
2296         E1000_WRITE_FLUSH(hw);
2297
2298         hw->txcw = txcw;
2299         mdelay(1);
2300
2301         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2302          * indication in the Device Status Register.  Time-out if a link isn't
2303          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2304          * less than 500 milliseconds even if the other end is doing it in SW).
2305          */
2306         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2307                 DEBUGOUT("Looking for Link\n");
2308                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2309                         mdelay(10);
2310                         status = E1000_READ_REG(hw, STATUS);
2311                         if (status & E1000_STATUS_LU)
2312                                 break;
2313                 }
2314                 if (i == (LINK_UP_TIMEOUT / 10)) {
2315                         /* AutoNeg failed to achieve a link, so we'll call
2316                          * e1000_check_for_link. This routine will force the link up if we
2317                          * detect a signal. This will allow us to communicate with
2318                          * non-autonegotiating link partners.
2319                          */
2320                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2321                         hw->autoneg_failed = 1;
2322                         ret_val = e1000_check_for_link(hw);
2323                         if (ret_val < 0) {
2324                                 DEBUGOUT("Error while checking for link\n");
2325                                 return ret_val;
2326                         }
2327                         hw->autoneg_failed = 0;
2328                 } else {
2329                         hw->autoneg_failed = 0;
2330                         DEBUGOUT("Valid Link Found\n");
2331                 }
2332         } else {
2333                 DEBUGOUT("No Signal Detected\n");
2334                 return -E1000_ERR_NOLINK;
2335         }
2336         return 0;
2337 }
2338
2339 /******************************************************************************
2340 * Make sure we have a valid PHY and change PHY mode before link setup.
2341 *
2342 * hw - Struct containing variables accessed by shared code
2343 ******************************************************************************/
2344 static int32_t
2345 e1000_copper_link_preconfig(struct e1000_hw *hw)
2346 {
2347         uint32_t ctrl;
2348         int32_t ret_val;
2349         uint16_t phy_data;
2350
2351         DEBUGFUNC();
2352
2353         ctrl = E1000_READ_REG(hw, CTRL);
2354         /* With 82543, we need to force speed and duplex on the MAC equal to what
2355          * the PHY speed and duplex configuration is. In addition, we need to
2356          * perform a hardware reset on the PHY to take it out of reset.
2357          */
2358         if (hw->mac_type > e1000_82543) {
2359                 ctrl |= E1000_CTRL_SLU;
2360                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2361                 E1000_WRITE_REG(hw, CTRL, ctrl);
2362         } else {
2363                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2364                                 | E1000_CTRL_SLU);
2365                 E1000_WRITE_REG(hw, CTRL, ctrl);
2366                 ret_val = e1000_phy_hw_reset(hw);
2367                 if (ret_val)
2368                         return ret_val;
2369         }
2370
2371         /* Make sure we have a valid PHY */
2372         ret_val = e1000_detect_gig_phy(hw);
2373         if (ret_val) {
2374                 DEBUGOUT("Error, did not detect valid phy.\n");
2375                 return ret_val;
2376         }
2377         DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2378
2379         /* Set PHY to class A mode (if necessary) */
2380         ret_val = e1000_set_phy_mode(hw);
2381         if (ret_val)
2382                 return ret_val;
2383         if ((hw->mac_type == e1000_82545_rev_3) ||
2384                 (hw->mac_type == e1000_82546_rev_3)) {
2385                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2386                                 &phy_data);
2387                 phy_data |= 0x00000008;
2388                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2389                                 phy_data);
2390         }
2391
2392         if (hw->mac_type <= e1000_82543 ||
2393                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2394                 hw->mac_type == e1000_82541_rev_2
2395                 || hw->mac_type == e1000_82547_rev_2)
2396                         hw->phy_reset_disable = false;
2397
2398         return E1000_SUCCESS;
2399 }
2400
2401 /*****************************************************************************
2402  *
2403  * This function sets the lplu state according to the active flag.  When
2404  * activating lplu this function also disables smart speed and vise versa.
2405  * lplu will not be activated unless the device autonegotiation advertisment
2406  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2407  * hw: Struct containing variables accessed by shared code
2408  * active - true to enable lplu false to disable lplu.
2409  *
2410  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2411  *            E1000_SUCCESS at any other case.
2412  *
2413  ****************************************************************************/
2414
2415 static int32_t
2416 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2417 {
2418         uint32_t phy_ctrl = 0;
2419         int32_t ret_val;
2420         uint16_t phy_data;
2421         DEBUGFUNC();
2422
2423         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2424             && hw->phy_type != e1000_phy_igp_3)
2425                 return E1000_SUCCESS;
2426
2427         /* During driver activity LPLU should not be used or it will attain link
2428          * from the lowest speeds starting from 10Mbps. The capability is used
2429          * for Dx transitions and states */
2430         if (hw->mac_type == e1000_82541_rev_2
2431                         || hw->mac_type == e1000_82547_rev_2) {
2432                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2433                                 &phy_data);
2434                 if (ret_val)
2435                         return ret_val;
2436         } else if (hw->mac_type == e1000_ich8lan) {
2437                 /* MAC writes into PHY register based on the state transition
2438                  * and start auto-negotiation. SW driver can overwrite the
2439                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2440                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2441         } else {
2442                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2443                                 &phy_data);
2444                 if (ret_val)
2445                         return ret_val;
2446         }
2447
2448         if (!active) {
2449                 if (hw->mac_type == e1000_82541_rev_2 ||
2450                         hw->mac_type == e1000_82547_rev_2) {
2451                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2452                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2453                                         phy_data);
2454                         if (ret_val)
2455                                 return ret_val;
2456                 } else {
2457                         if (hw->mac_type == e1000_ich8lan) {
2458                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2459                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2460                         } else {
2461                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2462                                 ret_val = e1000_write_phy_reg(hw,
2463                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2464                                 if (ret_val)
2465                                         return ret_val;
2466                         }
2467                 }
2468
2469         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2470          * Dx states where the power conservation is most important.  During
2471          * driver activity we should enable SmartSpeed, so performance is
2472          * maintained. */
2473                 if (hw->smart_speed == e1000_smart_speed_on) {
2474                         ret_val = e1000_read_phy_reg(hw,
2475                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2476                         if (ret_val)
2477                                 return ret_val;
2478
2479                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2480                         ret_val = e1000_write_phy_reg(hw,
2481                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2482                         if (ret_val)
2483                                 return ret_val;
2484                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2485                         ret_val = e1000_read_phy_reg(hw,
2486                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2487                         if (ret_val)
2488                                 return ret_val;
2489
2490                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2491                         ret_val = e1000_write_phy_reg(hw,
2492                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2493                         if (ret_val)
2494                                 return ret_val;
2495                 }
2496
2497         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2498                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2499                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2500
2501                 if (hw->mac_type == e1000_82541_rev_2 ||
2502                     hw->mac_type == e1000_82547_rev_2) {
2503                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2504                         ret_val = e1000_write_phy_reg(hw,
2505                                         IGP01E1000_GMII_FIFO, phy_data);
2506                         if (ret_val)
2507                                 return ret_val;
2508                 } else {
2509                         if (hw->mac_type == e1000_ich8lan) {
2510                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2511                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2512                         } else {
2513                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2514                                 ret_val = e1000_write_phy_reg(hw,
2515                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2516                                 if (ret_val)
2517                                         return ret_val;
2518                         }
2519                 }
2520
2521                 /* When LPLU is enabled we should disable SmartSpeed */
2522                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2523                                 &phy_data);
2524                 if (ret_val)
2525                         return ret_val;
2526
2527                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2528                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2529                                 phy_data);
2530                 if (ret_val)
2531                         return ret_val;
2532         }
2533         return E1000_SUCCESS;
2534 }
2535
2536 /*****************************************************************************
2537  *
2538  * This function sets the lplu d0 state according to the active flag.  When
2539  * activating lplu this function also disables smart speed and vise versa.
2540  * lplu will not be activated unless the device autonegotiation advertisment
2541  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2542  * hw: Struct containing variables accessed by shared code
2543  * active - true to enable lplu false to disable lplu.
2544  *
2545  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2546  *            E1000_SUCCESS at any other case.
2547  *
2548  ****************************************************************************/
2549
2550 static int32_t
2551 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2552 {
2553         uint32_t phy_ctrl = 0;
2554         int32_t ret_val;
2555         uint16_t phy_data;
2556         DEBUGFUNC();
2557
2558         if (hw->mac_type <= e1000_82547_rev_2)
2559                 return E1000_SUCCESS;
2560
2561         if (hw->mac_type == e1000_ich8lan) {
2562                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2563         } else if (hw->mac_type == e1000_igb) {
2564                 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2565         } else {
2566                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2567                                 &phy_data);
2568                 if (ret_val)
2569                         return ret_val;
2570         }
2571
2572         if (!active) {
2573                 if (hw->mac_type == e1000_ich8lan) {
2574                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2575                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2576                 } else if (hw->mac_type == e1000_igb) {
2577                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2578                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2579                 } else {
2580                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2581                         ret_val = e1000_write_phy_reg(hw,
2582                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2583                         if (ret_val)
2584                                 return ret_val;
2585                 }
2586
2587                 if (hw->mac_type == e1000_igb)
2588                         return E1000_SUCCESS;
2589
2590         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2591          * Dx states where the power conservation is most important.  During
2592          * driver activity we should enable SmartSpeed, so performance is
2593          * maintained. */
2594                 if (hw->smart_speed == e1000_smart_speed_on) {
2595                         ret_val = e1000_read_phy_reg(hw,
2596                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2597                         if (ret_val)
2598                                 return ret_val;
2599
2600                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2601                         ret_val = e1000_write_phy_reg(hw,
2602                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2603                         if (ret_val)
2604                                 return ret_val;
2605                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2606                         ret_val = e1000_read_phy_reg(hw,
2607                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2608                         if (ret_val)
2609                                 return ret_val;
2610
2611                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2612                         ret_val = e1000_write_phy_reg(hw,
2613                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2614                         if (ret_val)
2615                                 return ret_val;
2616                 }
2617
2618
2619         } else {
2620
2621                 if (hw->mac_type == e1000_ich8lan) {
2622                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2623                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2624                 } else if (hw->mac_type == e1000_igb) {
2625                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2626                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2627                 } else {
2628                         phy_data |= IGP02E1000_PM_D0_LPLU;
2629                         ret_val = e1000_write_phy_reg(hw,
2630                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2631                         if (ret_val)
2632                                 return ret_val;
2633                 }
2634
2635                 if (hw->mac_type == e1000_igb)
2636                         return E1000_SUCCESS;
2637
2638                 /* When LPLU is enabled we should disable SmartSpeed */
2639                 ret_val = e1000_read_phy_reg(hw,
2640                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2641                 if (ret_val)
2642                         return ret_val;
2643
2644                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2645                 ret_val = e1000_write_phy_reg(hw,
2646                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2647                 if (ret_val)
2648                         return ret_val;
2649
2650         }
2651         return E1000_SUCCESS;
2652 }
2653
2654 /********************************************************************
2655 * Copper link setup for e1000_phy_igp series.
2656 *
2657 * hw - Struct containing variables accessed by shared code
2658 *********************************************************************/
2659 static int32_t
2660 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2661 {
2662         uint32_t led_ctrl;
2663         int32_t ret_val;
2664         uint16_t phy_data;
2665
2666         DEBUGFUNC();
2667
2668         if (hw->phy_reset_disable)
2669                 return E1000_SUCCESS;
2670
2671         ret_val = e1000_phy_reset(hw);
2672         if (ret_val) {
2673                 DEBUGOUT("Error Resetting the PHY\n");
2674                 return ret_val;
2675         }
2676
2677         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2678         mdelay(15);
2679         if (hw->mac_type != e1000_ich8lan) {
2680                 /* Configure activity LED after PHY reset */
2681                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2682                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2683                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2684                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2685         }
2686
2687         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2688         if (hw->phy_type == e1000_phy_igp) {
2689                 /* disable lplu d3 during driver init */
2690                 ret_val = e1000_set_d3_lplu_state(hw, false);
2691                 if (ret_val) {
2692                         DEBUGOUT("Error Disabling LPLU D3\n");
2693                         return ret_val;
2694                 }
2695         }
2696
2697         /* disable lplu d0 during driver init */
2698         ret_val = e1000_set_d0_lplu_state(hw, false);
2699         if (ret_val) {
2700                 DEBUGOUT("Error Disabling LPLU D0\n");
2701                 return ret_val;
2702         }
2703         /* Configure mdi-mdix settings */
2704         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2705         if (ret_val)
2706                 return ret_val;
2707
2708         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2709                 hw->dsp_config_state = e1000_dsp_config_disabled;
2710                 /* Force MDI for earlier revs of the IGP PHY */
2711                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2712                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2713                 hw->mdix = 1;
2714
2715         } else {
2716                 hw->dsp_config_state = e1000_dsp_config_enabled;
2717                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2718
2719                 switch (hw->mdix) {
2720                 case 1:
2721                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2722                         break;
2723                 case 2:
2724                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2725                         break;
2726                 case 0:
2727                 default:
2728                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2729                         break;
2730                 }
2731         }
2732         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2733         if (ret_val)
2734                 return ret_val;
2735
2736         /* set auto-master slave resolution settings */
2737         if (hw->autoneg) {
2738                 e1000_ms_type phy_ms_setting = hw->master_slave;
2739
2740                 if (hw->ffe_config_state == e1000_ffe_config_active)
2741                         hw->ffe_config_state = e1000_ffe_config_enabled;
2742
2743                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2744                         hw->dsp_config_state = e1000_dsp_config_enabled;
2745
2746                 /* when autonegotiation advertisment is only 1000Mbps then we
2747                   * should disable SmartSpeed and enable Auto MasterSlave
2748                   * resolution as hardware default. */
2749                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2750                         /* Disable SmartSpeed */
2751                         ret_val = e1000_read_phy_reg(hw,
2752                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2753                         if (ret_val)
2754                                 return ret_val;
2755                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2756                         ret_val = e1000_write_phy_reg(hw,
2757                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2758                         if (ret_val)
2759                                 return ret_val;
2760                         /* Set auto Master/Slave resolution process */
2761                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2762                                         &phy_data);
2763                         if (ret_val)
2764                                 return ret_val;
2765                         phy_data &= ~CR_1000T_MS_ENABLE;
2766                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2767                                         phy_data);
2768                         if (ret_val)
2769                                 return ret_val;
2770                 }
2771
2772                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2773                 if (ret_val)
2774                         return ret_val;
2775
2776                 /* load defaults for future use */
2777                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2778                                 ((phy_data & CR_1000T_MS_VALUE) ?
2779                                 e1000_ms_force_master :
2780                                 e1000_ms_force_slave) :
2781                                 e1000_ms_auto;
2782
2783                 switch (phy_ms_setting) {
2784                 case e1000_ms_force_master:
2785                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2786                         break;
2787                 case e1000_ms_force_slave:
2788                         phy_data |= CR_1000T_MS_ENABLE;
2789                         phy_data &= ~(CR_1000T_MS_VALUE);
2790                         break;
2791                 case e1000_ms_auto:
2792                         phy_data &= ~CR_1000T_MS_ENABLE;
2793                 default:
2794                         break;
2795                 }
2796                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2797                 if (ret_val)
2798                         return ret_val;
2799         }
2800
2801         return E1000_SUCCESS;
2802 }
2803
2804 /*****************************************************************************
2805  * This function checks the mode of the firmware.
2806  *
2807  * returns  - true when the mode is IAMT or false.
2808  ****************************************************************************/
2809 bool
2810 e1000_check_mng_mode(struct e1000_hw *hw)
2811 {
2812         uint32_t fwsm;
2813         DEBUGFUNC();
2814
2815         fwsm = E1000_READ_REG(hw, FWSM);
2816
2817         if (hw->mac_type == e1000_ich8lan) {
2818                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2819                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2820                         return true;
2821         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2822                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2823                         return true;
2824
2825         return false;
2826 }
2827
2828 static int32_t
2829 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2830 {
2831         uint16_t swfw = E1000_SWFW_PHY0_SM;
2832         uint32_t reg_val;
2833         DEBUGFUNC();
2834
2835         if (e1000_is_second_port(hw))
2836                 swfw = E1000_SWFW_PHY1_SM;
2837
2838         if (e1000_swfw_sync_acquire(hw, swfw))
2839                 return -E1000_ERR_SWFW_SYNC;
2840
2841         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2842                         & E1000_KUMCTRLSTA_OFFSET) | data;
2843         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2844         udelay(2);
2845
2846         return E1000_SUCCESS;
2847 }
2848
2849 static int32_t
2850 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2851 {
2852         uint16_t swfw = E1000_SWFW_PHY0_SM;
2853         uint32_t reg_val;
2854         DEBUGFUNC();
2855
2856         if (e1000_is_second_port(hw))
2857                 swfw = E1000_SWFW_PHY1_SM;
2858
2859         if (e1000_swfw_sync_acquire(hw, swfw)) {
2860                 debug("%s[%i]\n", __func__, __LINE__);
2861                 return -E1000_ERR_SWFW_SYNC;
2862         }
2863
2864         /* Write register address */
2865         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2866                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2867         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2868         udelay(2);
2869
2870         /* Read the data returned */
2871         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2872         *data = (uint16_t)reg_val;
2873
2874         return E1000_SUCCESS;
2875 }
2876
2877 /********************************************************************
2878 * Copper link setup for e1000_phy_gg82563 series.
2879 *
2880 * hw - Struct containing variables accessed by shared code
2881 *********************************************************************/
2882 static int32_t
2883 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2884 {
2885         int32_t ret_val;
2886         uint16_t phy_data;
2887         uint32_t reg_data;
2888
2889         DEBUGFUNC();
2890
2891         if (!hw->phy_reset_disable) {
2892                 /* Enable CRS on TX for half-duplex operation. */
2893                 ret_val = e1000_read_phy_reg(hw,
2894                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2895                 if (ret_val)
2896                         return ret_val;
2897
2898                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2899                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2900                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2901
2902                 ret_val = e1000_write_phy_reg(hw,
2903                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2904                 if (ret_val)
2905                         return ret_val;
2906
2907                 /* Options:
2908                  *   MDI/MDI-X = 0 (default)
2909                  *   0 - Auto for all speeds
2910                  *   1 - MDI mode
2911                  *   2 - MDI-X mode
2912                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2913                  */
2914                 ret_val = e1000_read_phy_reg(hw,
2915                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2916                 if (ret_val)
2917                         return ret_val;
2918
2919                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2920
2921                 switch (hw->mdix) {
2922                 case 1:
2923                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2924                         break;
2925                 case 2:
2926                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2927                         break;
2928                 case 0:
2929                 default:
2930                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2931                         break;
2932                 }
2933
2934                 /* Options:
2935                  *   disable_polarity_correction = 0 (default)
2936                  *       Automatic Correction for Reversed Cable Polarity
2937                  *   0 - Disabled
2938                  *   1 - Enabled
2939                  */
2940                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2941                 ret_val = e1000_write_phy_reg(hw,
2942                                 GG82563_PHY_SPEC_CTRL, phy_data);
2943
2944                 if (ret_val)
2945                         return ret_val;
2946
2947                 /* SW Reset the PHY so all changes take effect */
2948                 ret_val = e1000_phy_reset(hw);
2949                 if (ret_val) {
2950                         DEBUGOUT("Error Resetting the PHY\n");
2951                         return ret_val;
2952                 }
2953         } /* phy_reset_disable */
2954
2955         if (hw->mac_type == e1000_80003es2lan) {
2956                 /* Bypass RX and TX FIFO's */
2957                 ret_val = e1000_write_kmrn_reg(hw,
2958                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2959                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2960                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2961                 if (ret_val)
2962                         return ret_val;
2963
2964                 ret_val = e1000_read_phy_reg(hw,
2965                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2966                 if (ret_val)
2967                         return ret_val;
2968
2969                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2970                 ret_val = e1000_write_phy_reg(hw,
2971                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2972
2973                 if (ret_val)
2974                         return ret_val;
2975
2976                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2977                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2978                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2979
2980                 ret_val = e1000_read_phy_reg(hw,
2981                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2982                 if (ret_val)
2983                         return ret_val;
2984
2985         /* Do not init these registers when the HW is in IAMT mode, since the
2986          * firmware will have already initialized them.  We only initialize
2987          * them if the HW is not in IAMT mode.
2988          */
2989                 if (e1000_check_mng_mode(hw) == false) {
2990                         /* Enable Electrical Idle on the PHY */
2991                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2992                         ret_val = e1000_write_phy_reg(hw,
2993                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2994                         if (ret_val)
2995                                 return ret_val;
2996
2997                         ret_val = e1000_read_phy_reg(hw,
2998                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2999                         if (ret_val)
3000                                 return ret_val;
3001
3002                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3003                         ret_val = e1000_write_phy_reg(hw,
3004                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
3005
3006                         if (ret_val)
3007                                 return ret_val;
3008                 }
3009
3010                 /* Workaround: Disable padding in Kumeran interface in the MAC
3011                  * and in the PHY to avoid CRC errors.
3012                  */
3013                 ret_val = e1000_read_phy_reg(hw,
3014                                 GG82563_PHY_INBAND_CTRL, &phy_data);
3015                 if (ret_val)
3016                         return ret_val;
3017                 phy_data |= GG82563_ICR_DIS_PADDING;
3018                 ret_val = e1000_write_phy_reg(hw,
3019                                 GG82563_PHY_INBAND_CTRL, phy_data);
3020                 if (ret_val)
3021                         return ret_val;
3022         }
3023         return E1000_SUCCESS;
3024 }
3025
3026 /********************************************************************
3027 * Copper link setup for e1000_phy_m88 series.
3028 *
3029 * hw - Struct containing variables accessed by shared code
3030 *********************************************************************/
3031 static int32_t
3032 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
3033 {
3034         int32_t ret_val;
3035         uint16_t phy_data;
3036
3037         DEBUGFUNC();
3038
3039         if (hw->phy_reset_disable)
3040                 return E1000_SUCCESS;
3041
3042         /* Enable CRS on TX. This must be set for half-duplex operation. */
3043         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3044         if (ret_val)
3045                 return ret_val;
3046
3047         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3048
3049         /* Options:
3050          *   MDI/MDI-X = 0 (default)
3051          *   0 - Auto for all speeds
3052          *   1 - MDI mode
3053          *   2 - MDI-X mode
3054          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3055          */
3056         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3057
3058         switch (hw->mdix) {
3059         case 1:
3060                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3061                 break;
3062         case 2:
3063                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3064                 break;
3065         case 3:
3066                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3067                 break;
3068         case 0:
3069         default:
3070                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3071                 break;
3072         }
3073
3074         /* Options:
3075          *   disable_polarity_correction = 0 (default)
3076          *       Automatic Correction for Reversed Cable Polarity
3077          *   0 - Disabled
3078          *   1 - Enabled
3079          */
3080         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
3081         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3082         if (ret_val)
3083                 return ret_val;
3084
3085         if (hw->phy_revision < M88E1011_I_REV_4) {
3086                 /* Force TX_CLK in the Extended PHY Specific Control Register
3087                  * to 25MHz clock.
3088                  */
3089                 ret_val = e1000_read_phy_reg(hw,
3090                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3091                 if (ret_val)
3092                         return ret_val;
3093
3094                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3095
3096                 if ((hw->phy_revision == E1000_REVISION_2) &&
3097                         (hw->phy_id == M88E1111_I_PHY_ID)) {
3098                         /* Vidalia Phy, set the downshift counter to 5x */
3099                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3100                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3101                         ret_val = e1000_write_phy_reg(hw,
3102                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3103                         if (ret_val)
3104                                 return ret_val;
3105                 } else {
3106                         /* Configure Master and Slave downshift values */
3107                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3108                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3109                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3110                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3111                         ret_val = e1000_write_phy_reg(hw,
3112                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3113                         if (ret_val)
3114                                 return ret_val;
3115                 }
3116         }
3117
3118         /* SW Reset the PHY so all changes take effect */
3119         ret_val = e1000_phy_reset(hw);
3120         if (ret_val) {
3121                 DEBUGOUT("Error Resetting the PHY\n");
3122                 return ret_val;
3123         }
3124
3125         return E1000_SUCCESS;
3126 }
3127
3128 /********************************************************************
3129 * Setup auto-negotiation and flow control advertisements,
3130 * and then perform auto-negotiation.
3131 *
3132 * hw - Struct containing variables accessed by shared code
3133 *********************************************************************/
3134 static int32_t
3135 e1000_copper_link_autoneg(struct e1000_hw *hw)
3136 {
3137         int32_t ret_val;
3138         uint16_t phy_data;
3139
3140         DEBUGFUNC();
3141
3142         /* Perform some bounds checking on the hw->autoneg_advertised
3143          * parameter.  If this variable is zero, then set it to the default.
3144          */
3145         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3146
3147         /* If autoneg_advertised is zero, we assume it was not defaulted
3148          * by the calling code so we set to advertise full capability.
3149          */
3150         if (hw->autoneg_advertised == 0)
3151                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3152
3153         /* IFE phy only supports 10/100 */
3154         if (hw->phy_type == e1000_phy_ife)
3155                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3156
3157         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3158         ret_val = e1000_phy_setup_autoneg(hw);
3159         if (ret_val) {
3160                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3161                 return ret_val;
3162         }
3163         DEBUGOUT("Restarting Auto-Neg\n");
3164
3165         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
3166          * the Auto Neg Restart bit in the PHY control register.
3167          */
3168         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3169         if (ret_val)
3170                 return ret_val;
3171
3172         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3173         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3174         if (ret_val)
3175                 return ret_val;
3176
3177         /* Does the user want to wait for Auto-Neg to complete here, or
3178          * check at a later time (for example, callback routine).
3179          */
3180         /* If we do not wait for autonegtation to complete I
3181          * do not see a valid link status.
3182          * wait_autoneg_complete = 1 .
3183          */
3184         if (hw->wait_autoneg_complete) {
3185                 ret_val = e1000_wait_autoneg(hw);
3186                 if (ret_val) {
3187                         DEBUGOUT("Error while waiting for autoneg"
3188                                         "to complete\n");
3189                         return ret_val;
3190                 }
3191         }
3192
3193         hw->get_link_status = true;
3194
3195         return E1000_SUCCESS;
3196 }
3197
3198 /******************************************************************************
3199 * Config the MAC and the PHY after link is up.
3200 *   1) Set up the MAC to the current PHY speed/duplex
3201 *      if we are on 82543.  If we
3202 *      are on newer silicon, we only need to configure
3203 *      collision distance in the Transmit Control Register.
3204 *   2) Set up flow control on the MAC to that established with
3205 *      the link partner.
3206 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3207 *
3208 * hw - Struct containing variables accessed by shared code
3209 ******************************************************************************/
3210 static int32_t
3211 e1000_copper_link_postconfig(struct e1000_hw *hw)
3212 {
3213         int32_t ret_val;
3214         DEBUGFUNC();
3215
3216         if (hw->mac_type >= e1000_82544) {
3217                 e1000_config_collision_dist(hw);
3218         } else {
3219                 ret_val = e1000_config_mac_to_phy(hw);
3220                 if (ret_val) {
3221                         DEBUGOUT("Error configuring MAC to PHY settings\n");
3222                         return ret_val;
3223                 }
3224         }
3225         ret_val = e1000_config_fc_after_link_up(hw);
3226         if (ret_val) {
3227                 DEBUGOUT("Error Configuring Flow Control\n");
3228                 return ret_val;
3229         }
3230         return E1000_SUCCESS;
3231 }
3232
3233 /******************************************************************************
3234 * Detects which PHY is present and setup the speed and duplex
3235 *
3236 * hw - Struct containing variables accessed by shared code
3237 ******************************************************************************/
3238 static int
3239 e1000_setup_copper_link(struct e1000_hw *hw)
3240 {
3241         int32_t ret_val;
3242         uint16_t i;
3243         uint16_t phy_data;
3244         uint16_t reg_data;
3245
3246         DEBUGFUNC();
3247
3248         switch (hw->mac_type) {
3249         case e1000_80003es2lan:
3250         case e1000_ich8lan:
3251                 /* Set the mac to wait the maximum time between each
3252                  * iteration and increase the max iterations when
3253                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3254                 ret_val = e1000_write_kmrn_reg(hw,
3255                                 GG82563_REG(0x34, 4), 0xFFFF);
3256                 if (ret_val)
3257                         return ret_val;
3258                 ret_val = e1000_read_kmrn_reg(hw,
3259                                 GG82563_REG(0x34, 9), &reg_data);
3260                 if (ret_val)
3261                         return ret_val;
3262                 reg_data |= 0x3F;
3263                 ret_val = e1000_write_kmrn_reg(hw,
3264                                 GG82563_REG(0x34, 9), reg_data);
3265                 if (ret_val)
3266                         return ret_val;
3267         default:
3268                 break;
3269         }
3270
3271         /* Check if it is a valid PHY and set PHY mode if necessary. */
3272         ret_val = e1000_copper_link_preconfig(hw);
3273         if (ret_val)
3274                 return ret_val;
3275         switch (hw->mac_type) {
3276         case e1000_80003es2lan:
3277                 /* Kumeran registers are written-only */
3278                 reg_data =
3279                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3280                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3281                 ret_val = e1000_write_kmrn_reg(hw,
3282                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3283                 if (ret_val)
3284                         return ret_val;
3285                 break;
3286         default:
3287                 break;
3288         }
3289
3290         if (hw->phy_type == e1000_phy_igp ||
3291                 hw->phy_type == e1000_phy_igp_3 ||
3292                 hw->phy_type == e1000_phy_igp_2) {
3293                 ret_val = e1000_copper_link_igp_setup(hw);
3294                 if (ret_val)
3295                         return ret_val;
3296         } else if (hw->phy_type == e1000_phy_m88 ||
3297                 hw->phy_type == e1000_phy_igb) {
3298                 ret_val = e1000_copper_link_mgp_setup(hw);
3299                 if (ret_val)
3300                         return ret_val;
3301         } else if (hw->phy_type == e1000_phy_gg82563) {
3302                 ret_val = e1000_copper_link_ggp_setup(hw);
3303                 if (ret_val)
3304                         return ret_val;
3305         }
3306
3307         /* always auto */
3308         /* Setup autoneg and flow control advertisement
3309           * and perform autonegotiation */
3310         ret_val = e1000_copper_link_autoneg(hw);
3311         if (ret_val)
3312                 return ret_val;
3313
3314         /* Check link status. Wait up to 100 microseconds for link to become
3315          * valid.
3316          */
3317         for (i = 0; i < 10; i++) {
3318                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3319                 if (ret_val)
3320                         return ret_val;
3321                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3322                 if (ret_val)
3323                         return ret_val;
3324
3325                 if (phy_data & MII_SR_LINK_STATUS) {
3326                         /* Config the MAC and PHY after link is up */
3327                         ret_val = e1000_copper_link_postconfig(hw);
3328                         if (ret_val)
3329                                 return ret_val;
3330
3331                         DEBUGOUT("Valid link established!!!\n");
3332                         return E1000_SUCCESS;
3333                 }
3334                 udelay(10);
3335         }
3336
3337         DEBUGOUT("Unable to establish link!!!\n");
3338         return E1000_SUCCESS;
3339 }
3340
3341 /******************************************************************************
3342 * Configures PHY autoneg and flow control advertisement settings
3343 *
3344 * hw - Struct containing variables accessed by shared code
3345 ******************************************************************************/
3346 int32_t
3347 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3348 {
3349         int32_t ret_val;
3350         uint16_t mii_autoneg_adv_reg;
3351         uint16_t mii_1000t_ctrl_reg;
3352
3353         DEBUGFUNC();
3354
3355         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3356         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3357         if (ret_val)
3358                 return ret_val;
3359
3360         if (hw->phy_type != e1000_phy_ife) {
3361                 /* Read the MII 1000Base-T Control Register (Address 9). */
3362                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3363                                 &mii_1000t_ctrl_reg);
3364                 if (ret_val)
3365                         return ret_val;
3366         } else
3367                 mii_1000t_ctrl_reg = 0;
3368
3369         /* Need to parse both autoneg_advertised and fc and set up
3370          * the appropriate PHY registers.  First we will parse for
3371          * autoneg_advertised software override.  Since we can advertise
3372          * a plethora of combinations, we need to check each bit
3373          * individually.
3374          */
3375
3376         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3377          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3378          * the  1000Base-T Control Register (Address 9).
3379          */
3380         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3381         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3382
3383         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3384
3385         /* Do we want to advertise 10 Mb Half Duplex? */
3386         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3387                 DEBUGOUT("Advertise 10mb Half duplex\n");
3388                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3389         }
3390
3391         /* Do we want to advertise 10 Mb Full Duplex? */
3392         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3393                 DEBUGOUT("Advertise 10mb Full duplex\n");
3394                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3395         }
3396
3397         /* Do we want to advertise 100 Mb Half Duplex? */
3398         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3399                 DEBUGOUT("Advertise 100mb Half duplex\n");
3400                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3401         }
3402
3403         /* Do we want to advertise 100 Mb Full Duplex? */
3404         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3405                 DEBUGOUT("Advertise 100mb Full duplex\n");
3406                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3407         }
3408
3409         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3410         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3411                 DEBUGOUT
3412                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3413         }
3414
3415         /* Do we want to advertise 1000 Mb Full Duplex? */
3416         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3417                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3418                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3419         }
3420
3421         /* Check for a software override of the flow control settings, and
3422          * setup the PHY advertisement registers accordingly.  If
3423          * auto-negotiation is enabled, then software will have to set the
3424          * "PAUSE" bits to the correct value in the Auto-Negotiation
3425          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3426          *
3427          * The possible values of the "fc" parameter are:
3428          *      0:  Flow control is completely disabled
3429          *      1:  Rx flow control is enabled (we can receive pause frames
3430          *          but not send pause frames).
3431          *      2:  Tx flow control is enabled (we can send pause frames
3432          *          but we do not support receiving pause frames).
3433          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3434          *  other:  No software override.  The flow control configuration
3435          *          in the EEPROM is used.
3436          */
3437         switch (hw->fc) {
3438         case e1000_fc_none:     /* 0 */
3439                 /* Flow control (RX & TX) is completely disabled by a
3440                  * software over-ride.
3441                  */
3442                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3443                 break;
3444         case e1000_fc_rx_pause: /* 1 */
3445                 /* RX Flow control is enabled, and TX Flow control is
3446                  * disabled, by a software over-ride.
3447                  */
3448                 /* Since there really isn't a way to advertise that we are
3449                  * capable of RX Pause ONLY, we will advertise that we
3450                  * support both symmetric and asymmetric RX PAUSE.  Later
3451                  * (in e1000_config_fc_after_link_up) we will disable the
3452                  *hw's ability to send PAUSE frames.
3453                  */
3454                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3455                 break;
3456         case e1000_fc_tx_pause: /* 2 */
3457                 /* TX Flow control is enabled, and RX Flow control is
3458                  * disabled, by a software over-ride.
3459                  */
3460                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3461                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3462                 break;
3463         case e1000_fc_full:     /* 3 */
3464                 /* Flow control (both RX and TX) is enabled by a software
3465                  * over-ride.
3466                  */
3467                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3468                 break;
3469         default:
3470                 DEBUGOUT("Flow control param set incorrectly\n");
3471                 return -E1000_ERR_CONFIG;
3472         }
3473
3474         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3475         if (ret_val)
3476                 return ret_val;
3477
3478         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3479
3480         if (hw->phy_type != e1000_phy_ife) {
3481                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3482                                 mii_1000t_ctrl_reg);
3483                 if (ret_val)
3484                         return ret_val;
3485         }
3486
3487         return E1000_SUCCESS;
3488 }
3489
3490 /******************************************************************************
3491 * Sets the collision distance in the Transmit Control register
3492 *
3493 * hw - Struct containing variables accessed by shared code
3494 *
3495 * Link should have been established previously. Reads the speed and duplex
3496 * information from the Device Status register.
3497 ******************************************************************************/
3498 static void
3499 e1000_config_collision_dist(struct e1000_hw *hw)
3500 {
3501         uint32_t tctl, coll_dist;
3502
3503         DEBUGFUNC();
3504
3505         if (hw->mac_type < e1000_82543)
3506                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3507         else
3508                 coll_dist = E1000_COLLISION_DISTANCE;
3509
3510         tctl = E1000_READ_REG(hw, TCTL);
3511
3512         tctl &= ~E1000_TCTL_COLD;
3513         tctl |= coll_dist << E1000_COLD_SHIFT;
3514
3515         E1000_WRITE_REG(hw, TCTL, tctl);
3516         E1000_WRITE_FLUSH(hw);
3517 }
3518
3519 /******************************************************************************
3520 * Sets MAC speed and duplex settings to reflect the those in the PHY
3521 *
3522 * hw - Struct containing variables accessed by shared code
3523 * mii_reg - data to write to the MII control register
3524 *
3525 * The contents of the PHY register containing the needed information need to
3526 * be passed in.
3527 ******************************************************************************/
3528 static int
3529 e1000_config_mac_to_phy(struct e1000_hw *hw)
3530 {
3531         uint32_t ctrl;
3532         uint16_t phy_data;
3533
3534         DEBUGFUNC();
3535
3536         /* Read the Device Control Register and set the bits to Force Speed
3537          * and Duplex.
3538          */
3539         ctrl = E1000_READ_REG(hw, CTRL);
3540         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3541         ctrl &= ~(E1000_CTRL_ILOS);
3542         ctrl |= (E1000_CTRL_SPD_SEL);
3543
3544         /* Set up duplex in the Device Control and Transmit Control
3545          * registers depending on negotiated values.
3546          */
3547         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3548                 DEBUGOUT("PHY Read Error\n");
3549                 return -E1000_ERR_PHY;
3550         }
3551         if (phy_data & M88E1000_PSSR_DPLX)
3552                 ctrl |= E1000_CTRL_FD;
3553         else
3554                 ctrl &= ~E1000_CTRL_FD;
3555
3556         e1000_config_collision_dist(hw);
3557
3558         /* Set up speed in the Device Control register depending on
3559          * negotiated values.
3560          */
3561         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3562                 ctrl |= E1000_CTRL_SPD_1000;
3563         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3564                 ctrl |= E1000_CTRL_SPD_100;
3565         /* Write the configured values back to the Device Control Reg. */
3566         E1000_WRITE_REG(hw, CTRL, ctrl);
3567         return 0;
3568 }
3569
3570 /******************************************************************************
3571  * Forces the MAC's flow control settings.
3572  *
3573  * hw - Struct containing variables accessed by shared code
3574  *
3575  * Sets the TFCE and RFCE bits in the device control register to reflect
3576  * the adapter settings. TFCE and RFCE need to be explicitly set by
3577  * software when a Copper PHY is used because autonegotiation is managed
3578  * by the PHY rather than the MAC. Software must also configure these
3579  * bits when link is forced on a fiber connection.
3580  *****************************************************************************/
3581 static int
3582 e1000_force_mac_fc(struct e1000_hw *hw)
3583 {
3584         uint32_t ctrl;
3585
3586         DEBUGFUNC();
3587
3588         /* Get the current configuration of the Device Control Register */
3589         ctrl = E1000_READ_REG(hw, CTRL);
3590
3591         /* Because we didn't get link via the internal auto-negotiation
3592          * mechanism (we either forced link or we got link via PHY
3593          * auto-neg), we have to manually enable/disable transmit an
3594          * receive flow control.
3595          *
3596          * The "Case" statement below enables/disable flow control
3597          * according to the "hw->fc" parameter.
3598          *
3599          * The possible values of the "fc" parameter are:
3600          *      0:  Flow control is completely disabled
3601          *      1:  Rx flow control is enabled (we can receive pause
3602          *          frames but not send pause frames).
3603          *      2:  Tx flow control is enabled (we can send pause frames
3604          *          frames but we do not receive pause frames).
3605          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3606          *  other:  No other values should be possible at this point.
3607          */
3608
3609         switch (hw->fc) {
3610         case e1000_fc_none:
3611                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3612                 break;
3613         case e1000_fc_rx_pause:
3614                 ctrl &= (~E1000_CTRL_TFCE);
3615                 ctrl |= E1000_CTRL_RFCE;
3616                 break;
3617         case e1000_fc_tx_pause:
3618                 ctrl &= (~E1000_CTRL_RFCE);
3619                 ctrl |= E1000_CTRL_TFCE;
3620                 break;
3621         case e1000_fc_full:
3622                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3623                 break;
3624         default:
3625                 DEBUGOUT("Flow control param set incorrectly\n");
3626                 return -E1000_ERR_CONFIG;
3627         }
3628
3629         /* Disable TX Flow Control for 82542 (rev 2.0) */
3630         if (hw->mac_type == e1000_82542_rev2_0)
3631                 ctrl &= (~E1000_CTRL_TFCE);
3632
3633         E1000_WRITE_REG(hw, CTRL, ctrl);
3634         return 0;
3635 }
3636
3637 /******************************************************************************
3638  * Configures flow control settings after link is established
3639  *
3640  * hw - Struct containing variables accessed by shared code
3641  *
3642  * Should be called immediately after a valid link has been established.
3643  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3644  * and autonegotiation is enabled, the MAC flow control settings will be set
3645  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3646  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3647  *****************************************************************************/
3648 static int32_t
3649 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3650 {
3651         int32_t ret_val;
3652         uint16_t mii_status_reg;
3653         uint16_t mii_nway_adv_reg;
3654         uint16_t mii_nway_lp_ability_reg;
3655         uint16_t speed;
3656         uint16_t duplex;
3657
3658         DEBUGFUNC();
3659
3660         /* Check for the case where we have fiber media and auto-neg failed
3661          * so we had to force link.  In this case, we need to force the
3662          * configuration of the MAC to match the "fc" parameter.
3663          */
3664         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3665                 || ((hw->media_type == e1000_media_type_internal_serdes)
3666                 && (hw->autoneg_failed))
3667                 || ((hw->media_type == e1000_media_type_copper)
3668                 && (!hw->autoneg))) {
3669                 ret_val = e1000_force_mac_fc(hw);
3670                 if (ret_val < 0) {
3671                         DEBUGOUT("Error forcing flow control settings\n");
3672                         return ret_val;
3673                 }
3674         }
3675
3676         /* Check for the case where we have copper media and auto-neg is
3677          * enabled.  In this case, we need to check and see if Auto-Neg
3678          * has completed, and if so, how the PHY and link partner has
3679          * flow control configured.
3680          */
3681         if (hw->media_type == e1000_media_type_copper) {
3682                 /* Read the MII Status Register and check to see if AutoNeg
3683                  * has completed.  We read this twice because this reg has
3684                  * some "sticky" (latched) bits.
3685                  */
3686                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3687                         DEBUGOUT("PHY Read Error\n");
3688                         return -E1000_ERR_PHY;
3689                 }
3690                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3691                         DEBUGOUT("PHY Read Error\n");
3692                         return -E1000_ERR_PHY;
3693                 }
3694
3695                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3696                         /* The AutoNeg process has completed, so we now need to
3697                          * read both the Auto Negotiation Advertisement Register
3698                          * (Address 4) and the Auto_Negotiation Base Page Ability
3699                          * Register (Address 5) to determine how flow control was
3700                          * negotiated.
3701                          */
3702                         if (e1000_read_phy_reg
3703                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3704                                 DEBUGOUT("PHY Read Error\n");
3705                                 return -E1000_ERR_PHY;
3706                         }
3707                         if (e1000_read_phy_reg
3708                             (hw, PHY_LP_ABILITY,
3709                              &mii_nway_lp_ability_reg) < 0) {
3710                                 DEBUGOUT("PHY Read Error\n");
3711                                 return -E1000_ERR_PHY;
3712                         }
3713
3714                         /* Two bits in the Auto Negotiation Advertisement Register
3715                          * (Address 4) and two bits in the Auto Negotiation Base
3716                          * Page Ability Register (Address 5) determine flow control
3717                          * for both the PHY and the link partner.  The following
3718                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3719                          * 1999, describes these PAUSE resolution bits and how flow
3720                          * control is determined based upon these settings.
3721                          * NOTE:  DC = Don't Care
3722                          *
3723                          *   LOCAL DEVICE  |   LINK PARTNER
3724                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3725                          *-------|---------|-------|---------|--------------------
3726                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3727                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3728                          *   0   |    1    |   1   |    0    | e1000_fc_none
3729                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3730                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3731                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3732                          *   1   |    1    |   0   |    0    | e1000_fc_none
3733                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3734                          *
3735                          */
3736                         /* Are both PAUSE bits set to 1?  If so, this implies
3737                          * Symmetric Flow Control is enabled at both ends.  The
3738                          * ASM_DIR bits are irrelevant per the spec.
3739                          *
3740                          * For Symmetric Flow Control:
3741                          *
3742                          *   LOCAL DEVICE  |   LINK PARTNER
3743                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3744                          *-------|---------|-------|---------|--------------------
3745                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3746                          *
3747                          */
3748                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3749                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3750                                 /* Now we need to check if the user selected RX ONLY
3751                                  * of pause frames.  In this case, we had to advertise
3752                                  * FULL flow control because we could not advertise RX
3753                                  * ONLY. Hence, we must now check to see if we need to
3754                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3755                                  */
3756                                 if (hw->original_fc == e1000_fc_full) {
3757                                         hw->fc = e1000_fc_full;
3758                                         DEBUGOUT("Flow Control = FULL.\r\n");
3759                                 } else {
3760                                         hw->fc = e1000_fc_rx_pause;
3761                                         DEBUGOUT
3762                                             ("Flow Control = RX PAUSE frames only.\r\n");
3763                                 }
3764                         }
3765                         /* For receiving PAUSE frames ONLY.
3766                          *
3767                          *   LOCAL DEVICE  |   LINK PARTNER
3768                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3769                          *-------|---------|-------|---------|--------------------
3770                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3771                          *
3772                          */
3773                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3774                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3775                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3776                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3777                         {
3778                                 hw->fc = e1000_fc_tx_pause;
3779                                 DEBUGOUT
3780                                     ("Flow Control = TX PAUSE frames only.\r\n");
3781                         }
3782                         /* For transmitting PAUSE frames ONLY.
3783                          *
3784                          *   LOCAL DEVICE  |   LINK PARTNER
3785                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3786                          *-------|---------|-------|---------|--------------------
3787                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3788                          *
3789                          */
3790                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3791                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3792                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3793                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3794                         {
3795                                 hw->fc = e1000_fc_rx_pause;
3796                                 DEBUGOUT
3797                                     ("Flow Control = RX PAUSE frames only.\r\n");
3798                         }
3799                         /* Per the IEEE spec, at this point flow control should be
3800                          * disabled.  However, we want to consider that we could
3801                          * be connected to a legacy switch that doesn't advertise
3802                          * desired flow control, but can be forced on the link
3803                          * partner.  So if we advertised no flow control, that is
3804                          * what we will resolve to.  If we advertised some kind of
3805                          * receive capability (Rx Pause Only or Full Flow Control)
3806                          * and the link partner advertised none, we will configure
3807                          * ourselves to enable Rx Flow Control only.  We can do
3808                          * this safely for two reasons:  If the link partner really
3809                          * didn't want flow control enabled, and we enable Rx, no
3810                          * harm done since we won't be receiving any PAUSE frames
3811                          * anyway.  If the intent on the link partner was to have
3812                          * flow control enabled, then by us enabling RX only, we
3813                          * can at least receive pause frames and process them.
3814                          * This is a good idea because in most cases, since we are
3815                          * predominantly a server NIC, more times than not we will
3816                          * be asked to delay transmission of packets than asking
3817                          * our link partner to pause transmission of frames.
3818                          */
3819                         else if (hw->original_fc == e1000_fc_none ||
3820                                  hw->original_fc == e1000_fc_tx_pause) {
3821                                 hw->fc = e1000_fc_none;
3822                                 DEBUGOUT("Flow Control = NONE.\r\n");
3823                         } else {
3824                                 hw->fc = e1000_fc_rx_pause;
3825                                 DEBUGOUT
3826                                     ("Flow Control = RX PAUSE frames only.\r\n");
3827                         }
3828
3829                         /* Now we need to do one last check...  If we auto-
3830                          * negotiated to HALF DUPLEX, flow control should not be
3831                          * enabled per IEEE 802.3 spec.
3832                          */
3833                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3834
3835                         if (duplex == HALF_DUPLEX)
3836                                 hw->fc = e1000_fc_none;
3837
3838                         /* Now we call a subroutine to actually force the MAC
3839                          * controller to use the correct flow control settings.
3840                          */
3841                         ret_val = e1000_force_mac_fc(hw);
3842                         if (ret_val < 0) {
3843                                 DEBUGOUT
3844                                     ("Error forcing flow control settings\n");
3845                                 return ret_val;
3846                         }
3847                 } else {
3848                         DEBUGOUT
3849                             ("Copper PHY and Auto Neg has not completed.\r\n");
3850                 }
3851         }
3852         return E1000_SUCCESS;
3853 }
3854
3855 /******************************************************************************
3856  * Checks to see if the link status of the hardware has changed.
3857  *
3858  * hw - Struct containing variables accessed by shared code
3859  *
3860  * Called by any function that needs to check the link status of the adapter.
3861  *****************************************************************************/
3862 static int
3863 e1000_check_for_link(struct e1000_hw *hw)
3864 {
3865         uint32_t rxcw;
3866         uint32_t ctrl;
3867         uint32_t status;
3868         uint32_t rctl;
3869         uint32_t signal;
3870         int32_t ret_val;
3871         uint16_t phy_data;
3872         uint16_t lp_capability;
3873
3874         DEBUGFUNC();
3875
3876         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3877          * set when the optics detect a signal. On older adapters, it will be
3878          * cleared when there is a signal
3879          */
3880         ctrl = E1000_READ_REG(hw, CTRL);
3881         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3882                 signal = E1000_CTRL_SWDPIN1;
3883         else
3884                 signal = 0;
3885
3886         status = E1000_READ_REG(hw, STATUS);
3887         rxcw = E1000_READ_REG(hw, RXCW);
3888         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3889
3890         /* If we have a copper PHY then we only want to go out to the PHY
3891          * registers to see if Auto-Neg has completed and/or if our link
3892          * status has changed.  The get_link_status flag will be set if we
3893          * receive a Link Status Change interrupt or we have Rx Sequence
3894          * Errors.
3895          */
3896         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3897                 /* First we want to see if the MII Status Register reports
3898                  * link.  If so, then we want to get the current speed/duplex
3899                  * of the PHY.
3900                  * Read the register twice since the link bit is sticky.
3901                  */
3902                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3903                         DEBUGOUT("PHY Read Error\n");
3904                         return -E1000_ERR_PHY;
3905                 }
3906                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3907                         DEBUGOUT("PHY Read Error\n");
3908                         return -E1000_ERR_PHY;
3909                 }
3910
3911                 if (phy_data & MII_SR_LINK_STATUS) {
3912                         hw->get_link_status = false;
3913                 } else {
3914                         /* No link detected */
3915                         return -E1000_ERR_NOLINK;
3916                 }
3917
3918                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3919                  * have Si on board that is 82544 or newer, Auto
3920                  * Speed Detection takes care of MAC speed/duplex
3921                  * configuration.  So we only need to configure Collision
3922                  * Distance in the MAC.  Otherwise, we need to force
3923                  * speed/duplex on the MAC to the current PHY speed/duplex
3924                  * settings.
3925                  */
3926                 if (hw->mac_type >= e1000_82544)
3927                         e1000_config_collision_dist(hw);
3928                 else {
3929                         ret_val = e1000_config_mac_to_phy(hw);
3930                         if (ret_val < 0) {
3931                                 DEBUGOUT
3932                                     ("Error configuring MAC to PHY settings\n");
3933                                 return ret_val;
3934                         }
3935                 }
3936
3937                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3938                  * need to restore the desired flow control settings because we may
3939                  * have had to re-autoneg with a different link partner.
3940                  */
3941                 ret_val = e1000_config_fc_after_link_up(hw);
3942                 if (ret_val < 0) {
3943                         DEBUGOUT("Error configuring flow control\n");
3944                         return ret_val;
3945                 }
3946
3947                 /* At this point we know that we are on copper and we have
3948                  * auto-negotiated link.  These are conditions for checking the link
3949                  * parter capability register.  We use the link partner capability to
3950                  * determine if TBI Compatibility needs to be turned on or off.  If
3951                  * the link partner advertises any speed in addition to Gigabit, then
3952                  * we assume that they are GMII-based, and TBI compatibility is not
3953                  * needed. If no other speeds are advertised, we assume the link
3954                  * partner is TBI-based, and we turn on TBI Compatibility.
3955                  */
3956                 if (hw->tbi_compatibility_en) {
3957                         if (e1000_read_phy_reg
3958                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3959                                 DEBUGOUT("PHY Read Error\n");
3960                                 return -E1000_ERR_PHY;
3961                         }
3962                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3963                                              NWAY_LPAR_10T_FD_CAPS |
3964                                              NWAY_LPAR_100TX_HD_CAPS |
3965                                              NWAY_LPAR_100TX_FD_CAPS |
3966                                              NWAY_LPAR_100T4_CAPS)) {
3967                                 /* If our link partner advertises anything in addition to
3968                                  * gigabit, we do not need to enable TBI compatibility.
3969                                  */
3970                                 if (hw->tbi_compatibility_on) {
3971                                         /* If we previously were in the mode, turn it off. */
3972                                         rctl = E1000_READ_REG(hw, RCTL);
3973                                         rctl &= ~E1000_RCTL_SBP;
3974                                         E1000_WRITE_REG(hw, RCTL, rctl);
3975                                         hw->tbi_compatibility_on = false;
3976                                 }
3977                         } else {
3978                                 /* If TBI compatibility is was previously off, turn it on. For
3979                                  * compatibility with a TBI link partner, we will store bad
3980                                  * packets. Some frames have an additional byte on the end and
3981                                  * will look like CRC errors to to the hardware.
3982                                  */
3983                                 if (!hw->tbi_compatibility_on) {
3984                                         hw->tbi_compatibility_on = true;
3985                                         rctl = E1000_READ_REG(hw, RCTL);
3986                                         rctl |= E1000_RCTL_SBP;
3987                                         E1000_WRITE_REG(hw, RCTL, rctl);
3988                                 }
3989                         }
3990                 }
3991         }
3992         /* If we don't have link (auto-negotiation failed or link partner cannot
3993          * auto-negotiate), the cable is plugged in (we have signal), and our
3994          * link partner is not trying to auto-negotiate with us (we are receiving
3995          * idles or data), we need to force link up. We also need to give
3996          * auto-negotiation time to complete, in case the cable was just plugged
3997          * in. The autoneg_failed flag does this.
3998          */
3999         else if ((hw->media_type == e1000_media_type_fiber) &&
4000                  (!(status & E1000_STATUS_LU)) &&
4001                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
4002                  (!(rxcw & E1000_RXCW_C))) {
4003                 if (hw->autoneg_failed == 0) {
4004                         hw->autoneg_failed = 1;
4005                         return 0;
4006                 }
4007                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
4008
4009                 /* Disable auto-negotiation in the TXCW register */
4010                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
4011
4012                 /* Force link-up and also force full-duplex. */
4013                 ctrl = E1000_READ_REG(hw, CTRL);
4014                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4015                 E1000_WRITE_REG(hw, CTRL, ctrl);
4016
4017                 /* Configure Flow Control after forcing link up. */
4018                 ret_val = e1000_config_fc_after_link_up(hw);
4019                 if (ret_val < 0) {
4020                         DEBUGOUT("Error configuring flow control\n");
4021                         return ret_val;
4022                 }
4023         }
4024         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
4025          * auto-negotiation in the TXCW register and disable forced link in the
4026          * Device Control register in an attempt to auto-negotiate with our link
4027          * partner.
4028          */
4029         else if ((hw->media_type == e1000_media_type_fiber) &&
4030                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4031                 DEBUGOUT
4032                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
4033                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
4034                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4035         }
4036         return 0;
4037 }
4038
4039 /******************************************************************************
4040 * Configure the MAC-to-PHY interface for 10/100Mbps
4041 *
4042 * hw - Struct containing variables accessed by shared code
4043 ******************************************************************************/
4044 static int32_t
4045 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
4046 {
4047         int32_t ret_val = E1000_SUCCESS;
4048         uint32_t tipg;
4049         uint16_t reg_data;
4050
4051         DEBUGFUNC();
4052
4053         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4054         ret_val = e1000_write_kmrn_reg(hw,
4055                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4056         if (ret_val)
4057                 return ret_val;
4058
4059         /* Configure Transmit Inter-Packet Gap */
4060         tipg = E1000_READ_REG(hw, TIPG);
4061         tipg &= ~E1000_TIPG_IPGT_MASK;
4062         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4063         E1000_WRITE_REG(hw, TIPG, tipg);
4064
4065         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4066
4067         if (ret_val)
4068                 return ret_val;
4069
4070         if (duplex == HALF_DUPLEX)
4071                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4072         else
4073                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4074
4075         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4076
4077         return ret_val;
4078 }
4079
4080 static int32_t
4081 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4082 {
4083         int32_t ret_val = E1000_SUCCESS;
4084         uint16_t reg_data;
4085         uint32_t tipg;
4086
4087         DEBUGFUNC();
4088
4089         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4090         ret_val = e1000_write_kmrn_reg(hw,
4091                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4092         if (ret_val)
4093                 return ret_val;
4094
4095         /* Configure Transmit Inter-Packet Gap */
4096         tipg = E1000_READ_REG(hw, TIPG);
4097         tipg &= ~E1000_TIPG_IPGT_MASK;
4098         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4099         E1000_WRITE_REG(hw, TIPG, tipg);
4100
4101         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4102
4103         if (ret_val)
4104                 return ret_val;
4105
4106         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4107         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4108
4109         return ret_val;
4110 }
4111
4112 /******************************************************************************
4113  * Detects the current speed and duplex settings of the hardware.
4114  *
4115  * hw - Struct containing variables accessed by shared code
4116  * speed - Speed of the connection
4117  * duplex - Duplex setting of the connection
4118  *****************************************************************************/
4119 static int
4120 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4121                 uint16_t *duplex)
4122 {
4123         uint32_t status;
4124         int32_t ret_val;
4125         uint16_t phy_data;
4126
4127         DEBUGFUNC();
4128
4129         if (hw->mac_type >= e1000_82543) {
4130                 status = E1000_READ_REG(hw, STATUS);
4131                 if (status & E1000_STATUS_SPEED_1000) {
4132                         *speed = SPEED_1000;
4133                         DEBUGOUT("1000 Mbs, ");
4134                 } else if (status & E1000_STATUS_SPEED_100) {
4135                         *speed = SPEED_100;
4136                         DEBUGOUT("100 Mbs, ");
4137                 } else {
4138                         *speed = SPEED_10;
4139                         DEBUGOUT("10 Mbs, ");
4140                 }
4141
4142                 if (status & E1000_STATUS_FD) {
4143                         *duplex = FULL_DUPLEX;
4144                         DEBUGOUT("Full Duplex\r\n");
4145                 } else {
4146                         *duplex = HALF_DUPLEX;
4147                         DEBUGOUT(" Half Duplex\r\n");
4148                 }
4149         } else {
4150                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4151                 *speed = SPEED_1000;
4152                 *duplex = FULL_DUPLEX;
4153         }
4154
4155         /* IGP01 PHY may advertise full duplex operation after speed downgrade
4156          * even if it is operating at half duplex.  Here we set the duplex
4157          * settings to match the duplex in the link partner's capabilities.
4158          */
4159         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4160                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4161                 if (ret_val)
4162                         return ret_val;
4163
4164                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4165                         *duplex = HALF_DUPLEX;
4166                 else {
4167                         ret_val = e1000_read_phy_reg(hw,
4168                                         PHY_LP_ABILITY, &phy_data);
4169                         if (ret_val)
4170                                 return ret_val;
4171                         if ((*speed == SPEED_100 &&
4172                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4173                                 || (*speed == SPEED_10
4174                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4175                                 *duplex = HALF_DUPLEX;
4176                 }
4177         }
4178
4179         if ((hw->mac_type == e1000_80003es2lan) &&
4180                 (hw->media_type == e1000_media_type_copper)) {
4181                 if (*speed == SPEED_1000)
4182                         ret_val = e1000_configure_kmrn_for_1000(hw);
4183                 else
4184                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4185                 if (ret_val)
4186                         return ret_val;
4187         }
4188         return E1000_SUCCESS;
4189 }
4190
4191 /******************************************************************************
4192 * Blocks until autoneg completes or times out (~4.5 seconds)
4193 *
4194 * hw - Struct containing variables accessed by shared code
4195 ******************************************************************************/
4196 static int
4197 e1000_wait_autoneg(struct e1000_hw *hw)
4198 {
4199         uint16_t i;
4200         uint16_t phy_data;
4201
4202         DEBUGFUNC();
4203         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4204
4205         /* We will wait for autoneg to complete or timeout to expire. */
4206         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4207                 /* Read the MII Status Register and wait for Auto-Neg
4208                  * Complete bit to be set.
4209                  */
4210                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4211                         DEBUGOUT("PHY Read Error\n");
4212                         return -E1000_ERR_PHY;
4213                 }
4214                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4215                         DEBUGOUT("PHY Read Error\n");
4216                         return -E1000_ERR_PHY;
4217                 }
4218                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4219                         DEBUGOUT("Auto-Neg complete.\n");
4220                         return 0;
4221                 }
4222                 mdelay(100);
4223         }
4224         DEBUGOUT("Auto-Neg timedout.\n");
4225         return -E1000_ERR_TIMEOUT;
4226 }
4227
4228 /******************************************************************************
4229 * Raises the Management Data Clock
4230 *
4231 * hw - Struct containing variables accessed by shared code
4232 * ctrl - Device control register's current value
4233 ******************************************************************************/
4234 static void
4235 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4236 {
4237         /* Raise the clock input to the Management Data Clock (by setting the MDC
4238          * bit), and then delay 2 microseconds.
4239          */
4240         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4241         E1000_WRITE_FLUSH(hw);
4242         udelay(2);
4243 }
4244
4245 /******************************************************************************
4246 * Lowers the Management Data Clock
4247 *
4248 * hw - Struct containing variables accessed by shared code
4249 * ctrl - Device control register's current value
4250 ******************************************************************************/
4251 static void
4252 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4253 {
4254         /* Lower the clock input to the Management Data Clock (by clearing the MDC
4255          * bit), and then delay 2 microseconds.
4256          */
4257         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4258         E1000_WRITE_FLUSH(hw);
4259         udelay(2);
4260 }
4261
4262 /******************************************************************************
4263 * Shifts data bits out to the PHY
4264 *
4265 * hw - Struct containing variables accessed by shared code
4266 * data - Data to send out to the PHY
4267 * count - Number of bits to shift out
4268 *
4269 * Bits are shifted out in MSB to LSB order.
4270 ******************************************************************************/
4271 static void
4272 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4273 {
4274         uint32_t ctrl;
4275         uint32_t mask;
4276
4277         /* We need to shift "count" number of bits out to the PHY. So, the value
4278          * in the "data" parameter will be shifted out to the PHY one bit at a
4279          * time. In order to do this, "data" must be broken down into bits.
4280          */
4281         mask = 0x01;
4282         mask <<= (count - 1);
4283
4284         ctrl = E1000_READ_REG(hw, CTRL);
4285
4286         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4287         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4288
4289         while (mask) {
4290                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4291                  * then raising and lowering the Management Data Clock. A "0" is
4292                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4293                  * raising and lowering the clock.
4294                  */
4295                 if (data & mask)
4296                         ctrl |= E1000_CTRL_MDIO;
4297                 else
4298                         ctrl &= ~E1000_CTRL_MDIO;
4299
4300                 E1000_WRITE_REG(hw, CTRL, ctrl);
4301                 E1000_WRITE_FLUSH(hw);
4302
4303                 udelay(2);
4304
4305                 e1000_raise_mdi_clk(hw, &ctrl);
4306                 e1000_lower_mdi_clk(hw, &ctrl);
4307
4308                 mask = mask >> 1;
4309         }
4310 }
4311
4312 /******************************************************************************
4313 * Shifts data bits in from the PHY
4314 *
4315 * hw - Struct containing variables accessed by shared code
4316 *
4317 * Bits are shifted in in MSB to LSB order.
4318 ******************************************************************************/
4319 static uint16_t
4320 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4321 {
4322         uint32_t ctrl;
4323         uint16_t data = 0;
4324         uint8_t i;
4325
4326         /* In order to read a register from the PHY, we need to shift in a total
4327          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4328          * to avoid contention on the MDIO pin when a read operation is performed.
4329          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4330          * by raising the input to the Management Data Clock (setting the MDC bit),
4331          * and then reading the value of the MDIO bit.
4332          */
4333         ctrl = E1000_READ_REG(hw, CTRL);
4334
4335         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4336         ctrl &= ~E1000_CTRL_MDIO_DIR;
4337         ctrl &= ~E1000_CTRL_MDIO;
4338
4339         E1000_WRITE_REG(hw, CTRL, ctrl);
4340         E1000_WRITE_FLUSH(hw);
4341
4342         /* Raise and Lower the clock before reading in the data. This accounts for
4343          * the turnaround bits. The first clock occurred when we clocked out the
4344          * last bit of the Register Address.
4345          */
4346         e1000_raise_mdi_clk(hw, &ctrl);
4347         e1000_lower_mdi_clk(hw, &ctrl);
4348
4349         for (data = 0, i = 0; i < 16; i++) {
4350                 data = data << 1;
4351                 e1000_raise_mdi_clk(hw, &ctrl);
4352                 ctrl = E1000_READ_REG(hw, CTRL);
4353                 /* Check to see if we shifted in a "1". */
4354                 if (ctrl & E1000_CTRL_MDIO)
4355                         data |= 1;
4356                 e1000_lower_mdi_clk(hw, &ctrl);
4357         }
4358
4359         e1000_raise_mdi_clk(hw, &ctrl);
4360         e1000_lower_mdi_clk(hw, &ctrl);
4361
4362         return data;
4363 }
4364
4365 /*****************************************************************************
4366 * Reads the value from a PHY register
4367 *
4368 * hw - Struct containing variables accessed by shared code
4369 * reg_addr - address of the PHY register to read
4370 ******************************************************************************/
4371 static int
4372 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4373 {
4374         uint32_t i;
4375         uint32_t mdic = 0;
4376         const uint32_t phy_addr = 1;
4377
4378         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4379                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4380                 return -E1000_ERR_PARAM;
4381         }
4382
4383         if (hw->mac_type > e1000_82543) {
4384                 /* Set up Op-code, Phy Address, and register address in the MDI
4385                  * Control register.  The MAC will take care of interfacing with the
4386                  * PHY to retrieve the desired data.
4387                  */
4388                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4389                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4390                         (E1000_MDIC_OP_READ));
4391
4392                 E1000_WRITE_REG(hw, MDIC, mdic);
4393
4394                 /* Poll the ready bit to see if the MDI read completed */
4395                 for (i = 0; i < 64; i++) {
4396                         udelay(10);
4397                         mdic = E1000_READ_REG(hw, MDIC);
4398                         if (mdic & E1000_MDIC_READY)
4399                                 break;
4400                 }
4401                 if (!(mdic & E1000_MDIC_READY)) {
4402                         DEBUGOUT("MDI Read did not complete\n");
4403                         return -E1000_ERR_PHY;
4404                 }
4405                 if (mdic & E1000_MDIC_ERROR) {
4406                         DEBUGOUT("MDI Error\n");
4407                         return -E1000_ERR_PHY;
4408                 }
4409                 *phy_data = (uint16_t) mdic;
4410         } else {
4411                 /* We must first send a preamble through the MDIO pin to signal the
4412                  * beginning of an MII instruction.  This is done by sending 32
4413                  * consecutive "1" bits.
4414                  */
4415                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4416
4417                 /* Now combine the next few fields that are required for a read
4418                  * operation.  We use this method instead of calling the
4419                  * e1000_shift_out_mdi_bits routine five different times. The format of
4420                  * a MII read instruction consists of a shift out of 14 bits and is
4421                  * defined as follows:
4422                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4423                  * followed by a shift in of 18 bits.  This first two bits shifted in
4424                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4425                  * READ operation is performed.  These two bits are thrown away
4426                  * followed by a shift in of 16 bits which contains the desired data.
4427                  */
4428                 mdic = ((reg_addr) | (phy_addr << 5) |
4429                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4430
4431                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4432
4433                 /* Now that we've shifted out the read command to the MII, we need to
4434                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4435                  * register address.
4436                  */
4437                 *phy_data = e1000_shift_in_mdi_bits(hw);
4438         }
4439         return 0;
4440 }
4441
4442 /******************************************************************************
4443 * Writes a value to a PHY register
4444 *
4445 * hw - Struct containing variables accessed by shared code
4446 * reg_addr - address of the PHY register to write
4447 * data - data to write to the PHY
4448 ******************************************************************************/
4449 static int
4450 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4451 {
4452         uint32_t i;
4453         uint32_t mdic = 0;
4454         const uint32_t phy_addr = 1;
4455
4456         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4457                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4458                 return -E1000_ERR_PARAM;
4459         }
4460
4461         if (hw->mac_type > e1000_82543) {
4462                 /* Set up Op-code, Phy Address, register address, and data intended
4463                  * for the PHY register in the MDI Control register.  The MAC will take
4464                  * care of interfacing with the PHY to send the desired data.
4465                  */
4466                 mdic = (((uint32_t) phy_data) |
4467                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4468                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4469                         (E1000_MDIC_OP_WRITE));
4470
4471                 E1000_WRITE_REG(hw, MDIC, mdic);
4472
4473                 /* Poll the ready bit to see if the MDI read completed */
4474                 for (i = 0; i < 64; i++) {
4475                         udelay(10);
4476                         mdic = E1000_READ_REG(hw, MDIC);
4477                         if (mdic & E1000_MDIC_READY)
4478                                 break;
4479                 }
4480                 if (!(mdic & E1000_MDIC_READY)) {
4481                         DEBUGOUT("MDI Write did not complete\n");
4482                         return -E1000_ERR_PHY;
4483                 }
4484         } else {
4485                 /* We'll need to use the SW defined pins to shift the write command
4486                  * out to the PHY. We first send a preamble to the PHY to signal the
4487                  * beginning of the MII instruction.  This is done by sending 32
4488                  * consecutive "1" bits.
4489                  */
4490                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4491
4492                 /* Now combine the remaining required fields that will indicate a
4493                  * write operation. We use this method instead of calling the
4494                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4495                  * format of a MII write instruction is as follows:
4496                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4497                  */
4498                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4499                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4500                 mdic <<= 16;
4501                 mdic |= (uint32_t) phy_data;
4502
4503                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4504         }
4505         return 0;
4506 }
4507
4508 /******************************************************************************
4509  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4510  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4511  * the caller to figure out how to deal with it.
4512  *
4513  * hw - Struct containing variables accessed by shared code
4514  *
4515  * returns: - E1000_BLK_PHY_RESET
4516  *            E1000_SUCCESS
4517  *
4518  *****************************************************************************/
4519 int32_t
4520 e1000_check_phy_reset_block(struct e1000_hw *hw)
4521 {
4522         uint32_t manc = 0;
4523         uint32_t fwsm = 0;
4524
4525         if (hw->mac_type == e1000_ich8lan) {
4526                 fwsm = E1000_READ_REG(hw, FWSM);
4527                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4528                                                 : E1000_BLK_PHY_RESET;
4529         }
4530
4531         if (hw->mac_type > e1000_82547_rev_2)
4532                 manc = E1000_READ_REG(hw, MANC);
4533         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4534                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4535 }
4536
4537 /***************************************************************************
4538  * Checks if the PHY configuration is done
4539  *
4540  * hw: Struct containing variables accessed by shared code
4541  *
4542  * returns: - E1000_ERR_RESET if fail to reset MAC
4543  *            E1000_SUCCESS at any other case.
4544  *
4545  ***************************************************************************/
4546 static int32_t
4547 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4548 {
4549         int32_t timeout = PHY_CFG_TIMEOUT;
4550         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4551
4552         DEBUGFUNC();
4553
4554         switch (hw->mac_type) {
4555         default:
4556                 mdelay(10);
4557                 break;
4558
4559         case e1000_80003es2lan:
4560                 /* Separate *_CFG_DONE_* bit for each port */
4561                 if (e1000_is_second_port(hw))
4562                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4563                 /* Fall Through */
4564
4565         case e1000_82571:
4566         case e1000_82572:
4567         case e1000_igb:
4568                 while (timeout) {
4569                         if (hw->mac_type == e1000_igb) {
4570                                 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4571                                         break;
4572                         } else {
4573                                 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4574                                         break;
4575                         }
4576                         mdelay(1);
4577                         timeout--;
4578                 }
4579                 if (!timeout) {
4580                         DEBUGOUT("MNG configuration cycle has not "
4581                                         "completed.\n");
4582                         return -E1000_ERR_RESET;
4583                 }
4584                 break;
4585         }
4586
4587         return E1000_SUCCESS;
4588 }
4589
4590 /******************************************************************************
4591 * Returns the PHY to the power-on reset state
4592 *
4593 * hw - Struct containing variables accessed by shared code
4594 ******************************************************************************/
4595 int32_t
4596 e1000_phy_hw_reset(struct e1000_hw *hw)
4597 {
4598         uint16_t swfw = E1000_SWFW_PHY0_SM;
4599         uint32_t ctrl, ctrl_ext;
4600         uint32_t led_ctrl;
4601         int32_t ret_val;
4602
4603         DEBUGFUNC();
4604
4605         /* In the case of the phy reset being blocked, it's not an error, we
4606          * simply return success without performing the reset. */
4607         ret_val = e1000_check_phy_reset_block(hw);
4608         if (ret_val)
4609                 return E1000_SUCCESS;
4610
4611         DEBUGOUT("Resetting Phy...\n");
4612
4613         if (hw->mac_type > e1000_82543) {
4614                 if (e1000_is_second_port(hw))
4615                         swfw = E1000_SWFW_PHY1_SM;
4616
4617                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4618                         DEBUGOUT("Unable to acquire swfw sync\n");
4619                         return -E1000_ERR_SWFW_SYNC;
4620                 }
4621
4622                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4623                  * bit. Then, take it out of reset.
4624                  */
4625                 ctrl = E1000_READ_REG(hw, CTRL);
4626                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4627                 E1000_WRITE_FLUSH(hw);
4628
4629                 if (hw->mac_type < e1000_82571)
4630                         udelay(10);
4631                 else
4632                         udelay(100);
4633
4634                 E1000_WRITE_REG(hw, CTRL, ctrl);
4635                 E1000_WRITE_FLUSH(hw);
4636
4637                 if (hw->mac_type >= e1000_82571)
4638                         mdelay(10);
4639
4640         } else {
4641                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4642                  * bit to put the PHY into reset. Then, take it out of reset.
4643                  */
4644                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4645                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4646                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4647                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4648                 E1000_WRITE_FLUSH(hw);
4649                 mdelay(10);
4650                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4651                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4652                 E1000_WRITE_FLUSH(hw);
4653         }
4654         udelay(150);
4655
4656         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4657                 /* Configure activity LED after PHY reset */
4658                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4659                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4660                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4661                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4662         }
4663
4664         e1000_swfw_sync_release(hw, swfw);
4665
4666         /* Wait for FW to finish PHY configuration. */
4667         ret_val = e1000_get_phy_cfg_done(hw);
4668         if (ret_val != E1000_SUCCESS)
4669                 return ret_val;
4670
4671         return ret_val;
4672 }
4673
4674 /******************************************************************************
4675  * IGP phy init script - initializes the GbE PHY
4676  *
4677  * hw - Struct containing variables accessed by shared code
4678  *****************************************************************************/
4679 static void
4680 e1000_phy_init_script(struct e1000_hw *hw)
4681 {
4682         uint32_t ret_val;
4683         uint16_t phy_saved_data;
4684         DEBUGFUNC();
4685
4686         if (hw->phy_init_script) {
4687                 mdelay(20);
4688
4689                 /* Save off the current value of register 0x2F5B to be
4690                  * restored at the end of this routine. */
4691                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4692
4693                 /* Disabled the PHY transmitter */
4694                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4695
4696                 mdelay(20);
4697
4698                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4699
4700                 mdelay(5);
4701
4702                 switch (hw->mac_type) {
4703                 case e1000_82541:
4704                 case e1000_82547:
4705                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4706
4707                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4708
4709                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4710
4711                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4712
4713                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4714
4715                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4716
4717                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4718
4719                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4720
4721                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4722                         break;
4723
4724                 case e1000_82541_rev_2:
4725                 case e1000_82547_rev_2:
4726                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4727                         break;
4728                 default:
4729                         break;
4730                 }
4731
4732                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4733
4734                 mdelay(20);
4735
4736                 /* Now enable the transmitter */
4737                 if (!ret_val)
4738                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4739
4740                 if (hw->mac_type == e1000_82547) {
4741                         uint16_t fused, fine, coarse;
4742
4743                         /* Move to analog registers page */
4744                         e1000_read_phy_reg(hw,
4745                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4746
4747                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4748                                 e1000_read_phy_reg(hw,
4749                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4750
4751                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4752                                 coarse = fused
4753                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4754
4755                                 if (coarse >
4756                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4757                                         coarse -=
4758                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4759                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4760                                 } else if (coarse
4761                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4762                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4763
4764                                 fused = (fused
4765                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4766                                         (fine
4767                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4768                                         (coarse
4769                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4770
4771                                 e1000_write_phy_reg(hw,
4772                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4773                                 e1000_write_phy_reg(hw,
4774                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4775                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4776                         }
4777                 }
4778         }
4779 }
4780
4781 /******************************************************************************
4782 * Resets the PHY
4783 *
4784 * hw - Struct containing variables accessed by shared code
4785 *
4786 * Sets bit 15 of the MII Control register
4787 ******************************************************************************/
4788 int32_t
4789 e1000_phy_reset(struct e1000_hw *hw)
4790 {
4791         int32_t ret_val;
4792         uint16_t phy_data;
4793
4794         DEBUGFUNC();
4795
4796         /* In the case of the phy reset being blocked, it's not an error, we
4797          * simply return success without performing the reset. */
4798         ret_val = e1000_check_phy_reset_block(hw);
4799         if (ret_val)
4800                 return E1000_SUCCESS;
4801
4802         switch (hw->phy_type) {
4803         case e1000_phy_igp:
4804         case e1000_phy_igp_2:
4805         case e1000_phy_igp_3:
4806         case e1000_phy_ife:
4807         case e1000_phy_igb:
4808                 ret_val = e1000_phy_hw_reset(hw);
4809                 if (ret_val)
4810                         return ret_val;
4811                 break;
4812         default:
4813                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4814                 if (ret_val)
4815                         return ret_val;
4816
4817                 phy_data |= MII_CR_RESET;
4818                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4819                 if (ret_val)
4820                         return ret_val;
4821
4822                 udelay(1);
4823                 break;
4824         }
4825
4826         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4827                 e1000_phy_init_script(hw);
4828
4829         return E1000_SUCCESS;
4830 }
4831
4832 static int e1000_set_phy_type (struct e1000_hw *hw)
4833 {
4834         DEBUGFUNC ();
4835
4836         if (hw->mac_type == e1000_undefined)
4837                 return -E1000_ERR_PHY_TYPE;
4838
4839         switch (hw->phy_id) {
4840         case M88E1000_E_PHY_ID:
4841         case M88E1000_I_PHY_ID:
4842         case M88E1011_I_PHY_ID:
4843         case M88E1111_I_PHY_ID:
4844                 hw->phy_type = e1000_phy_m88;
4845                 break;
4846         case IGP01E1000_I_PHY_ID:
4847                 if (hw->mac_type == e1000_82541 ||
4848                         hw->mac_type == e1000_82541_rev_2 ||
4849                         hw->mac_type == e1000_82547 ||
4850                         hw->mac_type == e1000_82547_rev_2) {
4851                         hw->phy_type = e1000_phy_igp;
4852                         break;
4853                 }
4854         case IGP03E1000_E_PHY_ID:
4855                 hw->phy_type = e1000_phy_igp_3;
4856                 break;
4857         case IFE_E_PHY_ID:
4858         case IFE_PLUS_E_PHY_ID:
4859         case IFE_C_E_PHY_ID:
4860                 hw->phy_type = e1000_phy_ife;
4861                 break;
4862         case GG82563_E_PHY_ID:
4863                 if (hw->mac_type == e1000_80003es2lan) {
4864                         hw->phy_type = e1000_phy_gg82563;
4865                         break;
4866                 }
4867         case BME1000_E_PHY_ID:
4868                 hw->phy_type = e1000_phy_bm;
4869                 break;
4870         case I210_I_PHY_ID:
4871                 hw->phy_type = e1000_phy_igb;
4872                 break;
4873                 /* Fall Through */
4874         default:
4875                 /* Should never have loaded on this device */
4876                 hw->phy_type = e1000_phy_undefined;
4877                 return -E1000_ERR_PHY_TYPE;
4878         }
4879
4880         return E1000_SUCCESS;
4881 }
4882
4883 /******************************************************************************
4884 * Probes the expected PHY address for known PHY IDs
4885 *
4886 * hw - Struct containing variables accessed by shared code
4887 ******************************************************************************/
4888 static int32_t
4889 e1000_detect_gig_phy(struct e1000_hw *hw)
4890 {
4891         int32_t phy_init_status, ret_val;
4892         uint16_t phy_id_high, phy_id_low;
4893         bool match = false;
4894
4895         DEBUGFUNC();
4896
4897         /* The 82571 firmware may still be configuring the PHY.  In this
4898          * case, we cannot access the PHY until the configuration is done.  So
4899          * we explicitly set the PHY values. */
4900         if (hw->mac_type == e1000_82571 ||
4901                 hw->mac_type == e1000_82572) {
4902                 hw->phy_id = IGP01E1000_I_PHY_ID;
4903                 hw->phy_type = e1000_phy_igp_2;
4904                 return E1000_SUCCESS;
4905         }
4906
4907         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4908          * work- around that forces PHY page 0 to be set or the reads fail.
4909          * The rest of the code in this routine uses e1000_read_phy_reg to
4910          * read the PHY ID.  So for ESB-2 we need to have this set so our
4911          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4912          * the routines below will figure this out as well. */
4913         if (hw->mac_type == e1000_80003es2lan)
4914                 hw->phy_type = e1000_phy_gg82563;
4915
4916         /* Read the PHY ID Registers to identify which PHY is onboard. */
4917         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4918         if (ret_val)
4919                 return ret_val;
4920
4921         hw->phy_id = (uint32_t) (phy_id_high << 16);
4922         udelay(20);
4923         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4924         if (ret_val)
4925                 return ret_val;
4926
4927         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4928         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4929
4930         switch (hw->mac_type) {
4931         case e1000_82543:
4932                 if (hw->phy_id == M88E1000_E_PHY_ID)
4933                         match = true;
4934                 break;
4935         case e1000_82544:
4936                 if (hw->phy_id == M88E1000_I_PHY_ID)
4937                         match = true;
4938                 break;
4939         case e1000_82540:
4940         case e1000_82545:
4941         case e1000_82545_rev_3:
4942         case e1000_82546:
4943         case e1000_82546_rev_3:
4944                 if (hw->phy_id == M88E1011_I_PHY_ID)
4945                         match = true;
4946                 break;
4947         case e1000_82541:
4948         case e1000_82541_rev_2:
4949         case e1000_82547:
4950         case e1000_82547_rev_2:
4951                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4952                         match = true;
4953
4954                 break;
4955         case e1000_82573:
4956                 if (hw->phy_id == M88E1111_I_PHY_ID)
4957                         match = true;
4958                 break;
4959         case e1000_82574:
4960                 if (hw->phy_id == BME1000_E_PHY_ID)
4961                         match = true;
4962                 break;
4963         case e1000_80003es2lan:
4964                 if (hw->phy_id == GG82563_E_PHY_ID)
4965                         match = true;
4966                 break;
4967         case e1000_ich8lan:
4968                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4969                         match = true;
4970                 if (hw->phy_id == IFE_E_PHY_ID)
4971                         match = true;
4972                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4973                         match = true;
4974                 if (hw->phy_id == IFE_C_E_PHY_ID)
4975                         match = true;
4976                 break;
4977         case e1000_igb:
4978                 if (hw->phy_id == I210_I_PHY_ID)
4979                         match = true;
4980                 break;
4981         default:
4982                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4983                 return -E1000_ERR_CONFIG;
4984         }
4985
4986         phy_init_status = e1000_set_phy_type(hw);
4987
4988         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4989                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4990                 return 0;
4991         }
4992         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4993         return -E1000_ERR_PHY;
4994 }
4995
4996 /*****************************************************************************
4997  * Set media type and TBI compatibility.
4998  *
4999  * hw - Struct containing variables accessed by shared code
5000  * **************************************************************************/
5001 void
5002 e1000_set_media_type(struct e1000_hw *hw)
5003 {
5004         uint32_t status;
5005
5006         DEBUGFUNC();
5007
5008         if (hw->mac_type != e1000_82543) {
5009                 /* tbi_compatibility is only valid on 82543 */
5010                 hw->tbi_compatibility_en = false;
5011         }
5012
5013         switch (hw->device_id) {
5014         case E1000_DEV_ID_82545GM_SERDES:
5015         case E1000_DEV_ID_82546GB_SERDES:
5016         case E1000_DEV_ID_82571EB_SERDES:
5017         case E1000_DEV_ID_82571EB_SERDES_DUAL:
5018         case E1000_DEV_ID_82571EB_SERDES_QUAD:
5019         case E1000_DEV_ID_82572EI_SERDES:
5020         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
5021                 hw->media_type = e1000_media_type_internal_serdes;
5022                 break;
5023         default:
5024                 switch (hw->mac_type) {
5025                 case e1000_82542_rev2_0:
5026                 case e1000_82542_rev2_1:
5027                         hw->media_type = e1000_media_type_fiber;
5028                         break;
5029                 case e1000_ich8lan:
5030                 case e1000_82573:
5031                 case e1000_82574:
5032                 case e1000_igb:
5033                         /* The STATUS_TBIMODE bit is reserved or reused
5034                          * for the this device.
5035                          */
5036                         hw->media_type = e1000_media_type_copper;
5037                         break;
5038                 default:
5039                         status = E1000_READ_REG(hw, STATUS);
5040                         if (status & E1000_STATUS_TBIMODE) {
5041                                 hw->media_type = e1000_media_type_fiber;
5042                                 /* tbi_compatibility not valid on fiber */
5043                                 hw->tbi_compatibility_en = false;
5044                         } else {
5045                                 hw->media_type = e1000_media_type_copper;
5046                         }
5047                         break;
5048                 }
5049         }
5050 }
5051
5052 /**
5053  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5054  *
5055  * e1000_sw_init initializes the Adapter private data structure.
5056  * Fields are initialized based on PCI device information and
5057  * OS network device settings (MTU size).
5058  **/
5059
5060 static int
5061 e1000_sw_init(struct e1000_hw *hw)
5062 {
5063         int result;
5064
5065         /* PCI config space info */
5066 #ifdef CONFIG_DM_ETH
5067         dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5068         dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5069         dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5070                              &hw->subsystem_vendor_id);
5071         dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5072
5073         dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5074         dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5075 #else
5076         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5077         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5078         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5079                              &hw->subsystem_vendor_id);
5080         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5081
5082         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5083         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5084 #endif
5085
5086         /* identify the MAC */
5087         result = e1000_set_mac_type(hw);
5088         if (result) {
5089                 E1000_ERR(hw, "Unknown MAC Type\n");
5090                 return result;
5091         }
5092
5093         switch (hw->mac_type) {
5094         default:
5095                 break;
5096         case e1000_82541:
5097         case e1000_82547:
5098         case e1000_82541_rev_2:
5099         case e1000_82547_rev_2:
5100                 hw->phy_init_script = 1;
5101                 break;
5102         }
5103
5104         /* flow control settings */
5105         hw->fc_high_water = E1000_FC_HIGH_THRESH;
5106         hw->fc_low_water = E1000_FC_LOW_THRESH;
5107         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5108         hw->fc_send_xon = 1;
5109
5110         /* Media type - copper or fiber */
5111         hw->tbi_compatibility_en = true;
5112         e1000_set_media_type(hw);
5113
5114         if (hw->mac_type >= e1000_82543) {
5115                 uint32_t status = E1000_READ_REG(hw, STATUS);
5116
5117                 if (status & E1000_STATUS_TBIMODE) {
5118                         DEBUGOUT("fiber interface\n");
5119                         hw->media_type = e1000_media_type_fiber;
5120                 } else {
5121                         DEBUGOUT("copper interface\n");
5122                         hw->media_type = e1000_media_type_copper;
5123                 }
5124         } else {
5125                 hw->media_type = e1000_media_type_fiber;
5126         }
5127
5128         hw->wait_autoneg_complete = true;
5129         if (hw->mac_type < e1000_82543)
5130                 hw->report_tx_early = 0;
5131         else
5132                 hw->report_tx_early = 1;
5133
5134         return E1000_SUCCESS;
5135 }
5136
5137 void
5138 fill_rx(struct e1000_hw *hw)
5139 {
5140         struct e1000_rx_desc *rd;
5141         unsigned long flush_start, flush_end;
5142
5143         rx_last = rx_tail;
5144         rd = rx_base + rx_tail;
5145         rx_tail = (rx_tail + 1) % 8;
5146         memset(rd, 0, 16);
5147         rd->buffer_addr = cpu_to_le64((unsigned long)packet);
5148
5149         /*
5150          * Make sure there are no stale data in WB over this area, which
5151          * might get written into the memory while the e1000 also writes
5152          * into the same memory area.
5153          */
5154         invalidate_dcache_range((unsigned long)packet,
5155                                 (unsigned long)packet + 4096);
5156         /* Dump the DMA descriptor into RAM. */
5157         flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5158         flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5159         flush_dcache_range(flush_start, flush_end);
5160
5161         E1000_WRITE_REG(hw, RDT, rx_tail);
5162 }
5163
5164 /**
5165  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5166  * @adapter: board private structure
5167  *
5168  * Configure the Tx unit of the MAC after a reset.
5169  **/
5170
5171 static void
5172 e1000_configure_tx(struct e1000_hw *hw)
5173 {
5174         unsigned long tctl;
5175         unsigned long tipg, tarc;
5176         uint32_t ipgr1, ipgr2;
5177
5178         E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
5179         E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
5180
5181         E1000_WRITE_REG(hw, TDLEN, 128);
5182
5183         /* Setup the HW Tx Head and Tail descriptor pointers */
5184         E1000_WRITE_REG(hw, TDH, 0);
5185         E1000_WRITE_REG(hw, TDT, 0);
5186         tx_tail = 0;
5187
5188         /* Set the default values for the Tx Inter Packet Gap timer */
5189         if (hw->mac_type <= e1000_82547_rev_2 &&
5190             (hw->media_type == e1000_media_type_fiber ||
5191              hw->media_type == e1000_media_type_internal_serdes))
5192                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5193         else
5194                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5195
5196         /* Set the default values for the Tx Inter Packet Gap timer */
5197         switch (hw->mac_type) {
5198         case e1000_82542_rev2_0:
5199         case e1000_82542_rev2_1:
5200                 tipg = DEFAULT_82542_TIPG_IPGT;
5201                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5202                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5203                 break;
5204         case e1000_80003es2lan:
5205                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5206                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5207                 break;
5208         default:
5209                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5210                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5211                 break;
5212         }
5213         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5214         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5215         E1000_WRITE_REG(hw, TIPG, tipg);
5216         /* Program the Transmit Control Register */
5217         tctl = E1000_READ_REG(hw, TCTL);
5218         tctl &= ~E1000_TCTL_CT;
5219         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5220             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5221
5222         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5223                 tarc = E1000_READ_REG(hw, TARC0);
5224                 /* set the speed mode bit, we'll clear it if we're not at
5225                  * gigabit link later */
5226                 /* git bit can be set to 1*/
5227         } else if (hw->mac_type == e1000_80003es2lan) {
5228                 tarc = E1000_READ_REG(hw, TARC0);
5229                 tarc |= 1;
5230                 E1000_WRITE_REG(hw, TARC0, tarc);
5231                 tarc = E1000_READ_REG(hw, TARC1);
5232                 tarc |= 1;
5233                 E1000_WRITE_REG(hw, TARC1, tarc);
5234         }
5235
5236
5237         e1000_config_collision_dist(hw);
5238         /* Setup Transmit Descriptor Settings for eop descriptor */
5239         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5240
5241         /* Need to set up RS bit */
5242         if (hw->mac_type < e1000_82543)
5243                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5244         else
5245                 hw->txd_cmd |= E1000_TXD_CMD_RS;
5246
5247
5248         if (hw->mac_type == e1000_igb) {
5249                 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5250
5251                 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5252                 reg_txdctl |= 1 << 25;
5253                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5254                 mdelay(20);
5255         }
5256
5257
5258
5259         E1000_WRITE_REG(hw, TCTL, tctl);
5260
5261
5262 }
5263
5264 /**
5265  * e1000_setup_rctl - configure the receive control register
5266  * @adapter: Board private structure
5267  **/
5268 static void
5269 e1000_setup_rctl(struct e1000_hw *hw)
5270 {
5271         uint32_t rctl;
5272
5273         rctl = E1000_READ_REG(hw, RCTL);
5274
5275         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5276
5277         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5278                 | E1000_RCTL_RDMTS_HALF;        /* |
5279                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5280
5281         if (hw->tbi_compatibility_on == 1)
5282                 rctl |= E1000_RCTL_SBP;
5283         else
5284                 rctl &= ~E1000_RCTL_SBP;
5285
5286         rctl &= ~(E1000_RCTL_SZ_4096);
5287                 rctl |= E1000_RCTL_SZ_2048;
5288                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5289         E1000_WRITE_REG(hw, RCTL, rctl);
5290 }
5291
5292 /**
5293  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5294  * @adapter: board private structure
5295  *
5296  * Configure the Rx unit of the MAC after a reset.
5297  **/
5298 static void
5299 e1000_configure_rx(struct e1000_hw *hw)
5300 {
5301         unsigned long rctl, ctrl_ext;
5302         rx_tail = 0;
5303
5304         /* make sure receives are disabled while setting up the descriptors */
5305         rctl = E1000_READ_REG(hw, RCTL);
5306         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5307         if (hw->mac_type >= e1000_82540) {
5308                 /* Set the interrupt throttling rate.  Value is calculated
5309                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5310 #define MAX_INTS_PER_SEC        8000
5311 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
5312                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5313         }
5314
5315         if (hw->mac_type >= e1000_82571) {
5316                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5317                 /* Reset delay timers after every interrupt */
5318                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5319                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5320                 E1000_WRITE_FLUSH(hw);
5321         }
5322         /* Setup the Base and Length of the Rx Descriptor Ring */
5323         E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5324         E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
5325
5326         E1000_WRITE_REG(hw, RDLEN, 128);
5327
5328         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5329         E1000_WRITE_REG(hw, RDH, 0);
5330         E1000_WRITE_REG(hw, RDT, 0);
5331         /* Enable Receives */
5332
5333         if (hw->mac_type == e1000_igb) {
5334
5335                 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5336                 reg_rxdctl |= 1 << 25;
5337                 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5338                 mdelay(20);
5339         }
5340
5341         E1000_WRITE_REG(hw, RCTL, rctl);
5342
5343         fill_rx(hw);
5344 }
5345
5346 /**************************************************************************
5347 POLL - Wait for a frame
5348 ***************************************************************************/
5349 static int
5350 _e1000_poll(struct e1000_hw *hw)
5351 {
5352         struct e1000_rx_desc *rd;
5353         unsigned long inval_start, inval_end;
5354         uint32_t len;
5355
5356         /* return true if there's an ethernet packet ready to read */
5357         rd = rx_base + rx_last;
5358
5359         /* Re-load the descriptor from RAM. */
5360         inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5361         inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5362         invalidate_dcache_range(inval_start, inval_end);
5363
5364         if (!(rd->status & E1000_RXD_STAT_DD))
5365                 return 0;
5366         /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5367         /* Packet received, make sure the data are re-loaded from RAM. */
5368         len = le16_to_cpu(rd->length);
5369         invalidate_dcache_range((unsigned long)packet,
5370                                 (unsigned long)packet +
5371                                 roundup(len, ARCH_DMA_MINALIGN));
5372         return len;
5373 }
5374
5375 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5376 {
5377         void *nv_packet = (void *)txpacket;
5378         struct e1000_tx_desc *txp;
5379         int i = 0;
5380         unsigned long flush_start, flush_end;
5381
5382         txp = tx_base + tx_tail;
5383         tx_tail = (tx_tail + 1) % 8;
5384
5385         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5386         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5387         txp->upper.data = 0;
5388
5389         /* Dump the packet into RAM so e1000 can pick them. */
5390         flush_dcache_range((unsigned long)nv_packet,
5391                            (unsigned long)nv_packet +
5392                            roundup(length, ARCH_DMA_MINALIGN));
5393         /* Dump the descriptor into RAM as well. */
5394         flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5395         flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5396         flush_dcache_range(flush_start, flush_end);
5397
5398         E1000_WRITE_REG(hw, TDT, tx_tail);
5399
5400         E1000_WRITE_FLUSH(hw);
5401         while (1) {
5402                 invalidate_dcache_range(flush_start, flush_end);
5403                 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5404                         break;
5405                 if (i++ > TOUT_LOOP) {
5406                         DEBUGOUT("e1000: tx timeout\n");
5407                         return 0;
5408                 }
5409                 udelay(10);     /* give the nic a chance to write to the register */
5410         }
5411         return 1;
5412 }
5413
5414 static void
5415 _e1000_disable(struct e1000_hw *hw)
5416 {
5417         /* Turn off the ethernet interface */
5418         E1000_WRITE_REG(hw, RCTL, 0);
5419         E1000_WRITE_REG(hw, TCTL, 0);
5420
5421         /* Clear the transmit ring */
5422         E1000_WRITE_REG(hw, TDH, 0);
5423         E1000_WRITE_REG(hw, TDT, 0);
5424
5425         /* Clear the receive ring */
5426         E1000_WRITE_REG(hw, RDH, 0);
5427         E1000_WRITE_REG(hw, RDT, 0);
5428
5429         mdelay(10);
5430 }
5431
5432 /*reset function*/
5433 static inline int
5434 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5435 {
5436         e1000_reset_hw(hw);
5437         if (hw->mac_type >= e1000_82544)
5438                 E1000_WRITE_REG(hw, WUC, 0);
5439
5440         return e1000_init_hw(hw, enetaddr);
5441 }
5442
5443 static int
5444 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5445 {
5446         int ret_val = 0;
5447
5448         ret_val = e1000_reset(hw, enetaddr);
5449         if (ret_val < 0) {
5450                 if ((ret_val == -E1000_ERR_NOLINK) ||
5451                     (ret_val == -E1000_ERR_TIMEOUT)) {
5452                         E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5453                 } else {
5454                         E1000_ERR(hw, "Hardware Initialization Failed\n");
5455                 }
5456                 return ret_val;
5457         }
5458         e1000_configure_tx(hw);
5459         e1000_setup_rctl(hw);
5460         e1000_configure_rx(hw);
5461         return 0;
5462 }
5463
5464 /******************************************************************************
5465  * Gets the current PCI bus type of hardware
5466  *
5467  * hw - Struct containing variables accessed by shared code
5468  *****************************************************************************/
5469 void e1000_get_bus_type(struct e1000_hw *hw)
5470 {
5471         uint32_t status;
5472
5473         switch (hw->mac_type) {
5474         case e1000_82542_rev2_0:
5475         case e1000_82542_rev2_1:
5476                 hw->bus_type = e1000_bus_type_pci;
5477                 break;
5478         case e1000_82571:
5479         case e1000_82572:
5480         case e1000_82573:
5481         case e1000_82574:
5482         case e1000_80003es2lan:
5483         case e1000_ich8lan:
5484         case e1000_igb:
5485                 hw->bus_type = e1000_bus_type_pci_express;
5486                 break;
5487         default:
5488                 status = E1000_READ_REG(hw, STATUS);
5489                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5490                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5491                 break;
5492         }
5493 }
5494
5495 #ifndef CONFIG_DM_ETH
5496 /* A list of all registered e1000 devices */
5497 static LIST_HEAD(e1000_hw_list);
5498 #endif
5499
5500 #ifdef CONFIG_DM_ETH
5501 static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5502                           struct udevice *devno, unsigned char enetaddr[6])
5503 #else
5504 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5505                           unsigned char enetaddr[6])
5506 #endif
5507 {
5508         u32 val;
5509
5510         /* Assign the passed-in values */
5511 #ifdef CONFIG_DM_ETH
5512         hw->pdev = devno;
5513 #else
5514         hw->pdev = devno;
5515 #endif
5516         hw->cardnum = cardnum;
5517
5518         /* Print a debug message with the IO base address */
5519 #ifdef CONFIG_DM_ETH
5520         dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5521 #else
5522         pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5523 #endif
5524         E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5525
5526         /* Try to enable I/O accesses and bus-mastering */
5527         val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5528 #ifdef CONFIG_DM_ETH
5529         dm_pci_write_config32(devno, PCI_COMMAND, val);
5530 #else
5531         pci_write_config_dword(devno, PCI_COMMAND, val);
5532 #endif
5533
5534         /* Make sure it worked */
5535 #ifdef CONFIG_DM_ETH
5536         dm_pci_read_config32(devno, PCI_COMMAND, &val);
5537 #else
5538         pci_read_config_dword(devno, PCI_COMMAND, &val);
5539 #endif
5540         if (!(val & PCI_COMMAND_MEMORY)) {
5541                 E1000_ERR(hw, "Can't enable I/O memory\n");
5542                 return -ENOSPC;
5543         }
5544         if (!(val & PCI_COMMAND_MASTER)) {
5545                 E1000_ERR(hw, "Can't enable bus-mastering\n");
5546                 return -EPERM;
5547         }
5548
5549         /* Are these variables needed? */
5550         hw->fc = e1000_fc_default;
5551         hw->original_fc = e1000_fc_default;
5552         hw->autoneg_failed = 0;
5553         hw->autoneg = 1;
5554         hw->get_link_status = true;
5555 #ifndef CONFIG_E1000_NO_NVM
5556         hw->eeprom_semaphore_present = true;
5557 #endif
5558 #ifdef CONFIG_DM_ETH
5559         hw->hw_addr = dm_pci_map_bar(devno,     PCI_BASE_ADDRESS_0,
5560                                                 PCI_REGION_MEM);
5561 #else
5562         hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5563                                                 PCI_REGION_MEM);
5564 #endif
5565         hw->mac_type = e1000_undefined;
5566
5567         /* MAC and Phy settings */
5568         if (e1000_sw_init(hw) < 0) {
5569                 E1000_ERR(hw, "Software init failed\n");
5570                 return -EIO;
5571         }
5572         if (e1000_check_phy_reset_block(hw))
5573                 E1000_ERR(hw, "PHY Reset is blocked!\n");
5574
5575         /* Basic init was OK, reset the hardware and allow SPI access */
5576         e1000_reset_hw(hw);
5577
5578 #ifndef CONFIG_E1000_NO_NVM
5579         /* Validate the EEPROM and get chipset information */
5580         if (e1000_init_eeprom_params(hw)) {
5581                 E1000_ERR(hw, "EEPROM is invalid!\n");
5582                 return -EINVAL;
5583         }
5584         if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5585             e1000_validate_eeprom_checksum(hw))
5586                 return -ENXIO;
5587         e1000_read_mac_addr(hw, enetaddr);
5588 #endif
5589         e1000_get_bus_type(hw);
5590
5591 #ifndef CONFIG_E1000_NO_NVM
5592         printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5593                enetaddr[0], enetaddr[1], enetaddr[2],
5594                enetaddr[3], enetaddr[4], enetaddr[5]);
5595 #else
5596         memset(enetaddr, 0, 6);
5597         printf("e1000: no NVM\n");
5598 #endif
5599
5600         return 0;
5601 }
5602
5603 /* Put the name of a device in a string */
5604 static void e1000_name(char *str, int cardnum)
5605 {
5606         sprintf(str, "e1000#%u", cardnum);
5607 }
5608
5609 #ifndef CONFIG_DM_ETH
5610 /**************************************************************************
5611 TRANSMIT - Transmit a frame
5612 ***************************************************************************/
5613 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5614 {
5615         struct e1000_hw *hw = nic->priv;
5616
5617         return _e1000_transmit(hw, txpacket, length);
5618 }
5619
5620 /**************************************************************************
5621 DISABLE - Turn off ethernet interface
5622 ***************************************************************************/
5623 static void
5624 e1000_disable(struct eth_device *nic)
5625 {
5626         struct e1000_hw *hw = nic->priv;
5627
5628         _e1000_disable(hw);
5629 }
5630
5631 /**************************************************************************
5632 INIT - set up ethernet interface(s)
5633 ***************************************************************************/
5634 static int
5635 e1000_init(struct eth_device *nic, bd_t *bis)
5636 {
5637         struct e1000_hw *hw = nic->priv;
5638
5639         return _e1000_init(hw, nic->enetaddr);
5640 }
5641
5642 static int
5643 e1000_poll(struct eth_device *nic)
5644 {
5645         struct e1000_hw *hw = nic->priv;
5646         int len;
5647
5648         len = _e1000_poll(hw);
5649         if (len) {
5650                 net_process_received_packet((uchar *)packet, len);
5651                 fill_rx(hw);
5652         }
5653
5654         return len ? 1 : 0;
5655 }
5656
5657 static int e1000_write_hwaddr(struct eth_device *dev)
5658 {
5659 #ifndef CONFIG_E1000_NO_NVM
5660         unsigned char *mac = dev->enetaddr;
5661         unsigned char current_mac[6];
5662         struct e1000_hw *hw = dev->priv;
5663         uint16_t data[3];
5664         int ret_val, i;
5665
5666         DEBUGOUT("%s: mac=%pM\n", __func__, mac);
5667
5668         memset(current_mac, 0, 6);
5669
5670         /* Read from EEPROM, not from registers, to make sure
5671          * the address is persistently configured
5672          */
5673         ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5674         DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
5675
5676         /* Only write to EEPROM if the given address is different or
5677          * reading the current address failed
5678          */
5679         if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5680                 return 0;
5681
5682         for (i = 0; i < 3; ++i)
5683                 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
5684
5685         ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5686
5687         if (!ret_val)
5688                 ret_val = e1000_update_eeprom_checksum_i210(hw);
5689
5690         return ret_val;
5691 #else
5692         return 0;
5693 #endif
5694 }
5695
5696 /**************************************************************************
5697 PROBE - Look for an adapter, this routine's visible to the outside
5698 You should omit the last argument struct pci_device * for a non-PCI NIC
5699 ***************************************************************************/
5700 int
5701 e1000_initialize(bd_t * bis)
5702 {
5703         unsigned int i;
5704         pci_dev_t devno;
5705         int ret;
5706
5707         DEBUGFUNC();
5708
5709         /* Find and probe all the matching PCI devices */
5710         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5711                 /*
5712                  * These will never get freed due to errors, this allows us to
5713                  * perform SPI EEPROM programming from U-Boot, for example.
5714                  */
5715                 struct eth_device *nic = malloc(sizeof(*nic));
5716                 struct e1000_hw *hw = malloc(sizeof(*hw));
5717                 if (!nic || !hw) {
5718                         printf("e1000#%u: Out of Memory!\n", i);
5719                         free(nic);
5720                         free(hw);
5721                         continue;
5722                 }
5723
5724                 /* Make sure all of the fields are initially zeroed */
5725                 memset(nic, 0, sizeof(*nic));
5726                 memset(hw, 0, sizeof(*hw));
5727                 nic->priv = hw;
5728
5729                 /* Generate a card name */
5730                 e1000_name(nic->name, i);
5731                 hw->name = nic->name;
5732
5733                 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5734                 if (ret)
5735                         continue;
5736                 list_add_tail(&hw->list_node, &e1000_hw_list);
5737
5738                 hw->nic = nic;
5739
5740                 /* Set up the function pointers and register the device */
5741                 nic->init = e1000_init;
5742                 nic->recv = e1000_poll;
5743                 nic->send = e1000_transmit;
5744                 nic->halt = e1000_disable;
5745                 nic->write_hwaddr = e1000_write_hwaddr;
5746                 eth_register(nic);
5747         }
5748
5749         return i;
5750 }
5751
5752 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5753 {
5754         struct e1000_hw *hw;
5755
5756         list_for_each_entry(hw, &e1000_hw_list, list_node)
5757                 if (hw->cardnum == cardnum)
5758                         return hw;
5759
5760         return NULL;
5761 }
5762 #endif /* !CONFIG_DM_ETH */
5763
5764 #ifdef CONFIG_CMD_E1000
5765 static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
5766                     char *const argv[])
5767 {
5768         unsigned char *mac = NULL;
5769 #ifdef CONFIG_DM_ETH
5770         struct eth_pdata *plat;
5771         struct udevice *dev;
5772         char name[30];
5773         int ret;
5774 #endif
5775 #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
5776         struct e1000_hw *hw;
5777 #endif
5778         int cardnum;
5779
5780         if (argc < 3) {
5781                 cmd_usage(cmdtp);
5782                 return 1;
5783         }
5784
5785         /* Make sure we can find the requested e1000 card */
5786         cardnum = simple_strtoul(argv[1], NULL, 10);
5787 #ifdef CONFIG_DM_ETH
5788         e1000_name(name, cardnum);
5789         ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5790         if (!ret) {
5791                 plat = dev_get_platdata(dev);
5792                 mac = plat->enetaddr;
5793         }
5794 #else
5795         hw = e1000_find_card(cardnum);
5796         if (hw)
5797                 mac = hw->nic->enetaddr;
5798 #endif
5799         if (!mac) {
5800                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5801                 return 1;
5802         }
5803
5804         if (!strcmp(argv[2], "print-mac-address")) {
5805                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5806                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5807                 return 0;
5808         }
5809
5810 #ifdef CONFIG_E1000_SPI
5811 #ifdef CONFIG_DM_ETH
5812         hw = dev_get_priv(dev);
5813 #endif
5814         /* Handle the "SPI" subcommand */
5815         if (!strcmp(argv[2], "spi"))
5816                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5817 #endif
5818
5819         cmd_usage(cmdtp);
5820         return 1;
5821 }
5822
5823 U_BOOT_CMD(
5824         e1000, 7, 0, do_e1000,
5825         "Intel e1000 controller management",
5826         /*  */"<card#> print-mac-address\n"
5827 #ifdef CONFIG_E1000_SPI
5828         "e1000 <card#> spi show [<offset> [<length>]]\n"
5829         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5830         "e1000 <card#> spi program <addr> <offset> <length>\n"
5831         "e1000 <card#> spi checksum [update]\n"
5832 #endif
5833         "       - Manage the Intel E1000 PCI device"
5834 );
5835 #endif /* not CONFIG_CMD_E1000 */
5836
5837 #ifdef CONFIG_DM_ETH
5838 static int e1000_eth_start(struct udevice *dev)
5839 {
5840         struct eth_pdata *plat = dev_get_platdata(dev);
5841         struct e1000_hw *hw = dev_get_priv(dev);
5842
5843         return _e1000_init(hw, plat->enetaddr);
5844 }
5845
5846 static void e1000_eth_stop(struct udevice *dev)
5847 {
5848         struct e1000_hw *hw = dev_get_priv(dev);
5849
5850         _e1000_disable(hw);
5851 }
5852
5853 static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5854 {
5855         struct e1000_hw *hw = dev_get_priv(dev);
5856         int ret;
5857
5858         ret = _e1000_transmit(hw, packet, length);
5859
5860         return ret ? 0 : -ETIMEDOUT;
5861 }
5862
5863 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5864 {
5865         struct e1000_hw *hw = dev_get_priv(dev);
5866         int len;
5867
5868         len = _e1000_poll(hw);
5869         if (len)
5870                 *packetp = packet;
5871
5872         return len ? len : -EAGAIN;
5873 }
5874
5875 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5876 {
5877         struct e1000_hw *hw = dev_get_priv(dev);
5878
5879         fill_rx(hw);
5880
5881         return 0;
5882 }
5883
5884 static int e1000_eth_probe(struct udevice *dev)
5885 {
5886         struct eth_pdata *plat = dev_get_platdata(dev);
5887         struct e1000_hw *hw = dev_get_priv(dev);
5888         int ret;
5889
5890         hw->name = dev->name;
5891         ret = e1000_init_one(hw, trailing_strtol(dev->name),
5892                              dev, plat->enetaddr);
5893         if (ret < 0) {
5894                 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5895                 return ret;
5896         }
5897
5898         return 0;
5899 }
5900
5901 static int e1000_eth_bind(struct udevice *dev)
5902 {
5903         char name[20];
5904
5905         /*
5906          * A simple way to number the devices. When device tree is used this
5907          * is unnecessary, but when the device is just discovered on the PCI
5908          * bus we need a name. We could instead have the uclass figure out
5909          * which devices are different and number them.
5910          */
5911         e1000_name(name, num_cards++);
5912
5913         return device_set_name(dev, name);
5914 }
5915
5916 static const struct eth_ops e1000_eth_ops = {
5917         .start  = e1000_eth_start,
5918         .send   = e1000_eth_send,
5919         .recv   = e1000_eth_recv,
5920         .stop   = e1000_eth_stop,
5921         .free_pkt = e1000_free_pkt,
5922 };
5923
5924 static const struct udevice_id e1000_eth_ids[] = {
5925         { .compatible = "intel,e1000" },
5926         { }
5927 };
5928
5929 U_BOOT_DRIVER(eth_e1000) = {
5930         .name   = "eth_e1000",
5931         .id     = UCLASS_ETH,
5932         .of_match = e1000_eth_ids,
5933         .bind   = e1000_eth_bind,
5934         .probe  = e1000_eth_probe,
5935         .ops    = &e1000_eth_ops,
5936         .priv_auto_alloc_size = sizeof(struct e1000_hw),
5937         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5938 };
5939
5940 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5941 #endif