drivers/net/e1000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**************************************************************************
   3 Intel Pro 1000 for ppcboot/das-u-boot
   4 Drivers are port from Intel's Linux driver e1000-4.3.15
   5 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   6 tested on both gig copper and gig fiber boards
   7 ***************************************************************************/
   8 /*******************************************************************************
   9
  10
  11   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  12
  13
  14   Contact Information:
  15   Linux NICS <linux.nics@intel.com>
  16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18 *******************************************************************************/
  19 /*
  20  *  Copyright (C) Archway Digital Solutions.
  21  *
  22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23  *  2/9/2002
  24  *
  25  *  Copyright (C) Linux Networx.
  26  *  Massive upgrade to work with the new intel gigabit NICs.
  27  *  <ebiederman at lnxi dot com>
  28  *
  29  *  Copyright 2011 Freescale Semiconductor, Inc.
  30  */
  31
  32 #include <common.h>
  33 #include <command.h>
  34 #include <cpu_func.h>
  35 #include <dm.h>
  36 #include <errno.h>
  37 #include <log.h>
  38 #include <malloc.h>
  39 #include <memalign.h>
  40 #include <net.h>
  41 #include <pci.h>
  42 #include "e1000.h"
  43 #include <asm/cache.h>
  44
  45 #define TOUT_LOOP   100000
  46
  47 #ifdef CONFIG_DM_ETH
  48 #define virt_to_bus(devno, v)   dm_pci_virt_to_mem(devno, (void *) (v))
  49 #define bus_to_phys(devno, a)   dm_pci_mem_to_phys(devno, a)
  50 #else
  51 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  52 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  53 #endif
  54
  55 #define E1000_DEFAULT_PCI_PBA   0x00000030
  56 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  57
  58 /* NIC specific static variables go here */
  59
  60 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  61 #define E1000_BUFFER_ALIGN      128
  62
  63 /*
  64  * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  65  * Concurrent receiving on multiple active Ethernet devices will not work.
  66  * Normally U-Boot does not support this anyway. To fix it in this driver,
  67  * move these buffers and the tx/rx pointers to struct e1000_hw.
  68  */
  69 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  70 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  71 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  72
  73 static int tx_tail;
  74 static int rx_tail, rx_last;
  75 #ifdef CONFIG_DM_ETH
  76 static int num_cards;   /* Number of E1000 devices seen so far */
  77 #endif
  78
  79 static struct pci_device_id e1000_supported[] = {
  80         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  81         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  82         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  83         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  84         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  85         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  86         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  87         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  88         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  89         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  90         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  91         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  92         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  93         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  94         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  95         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  96         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  97         /* E1000 PCIe card */
  98         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  99         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
 100         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
 101         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
 102         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
 103         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
 104         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
 105         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
 106         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
 107         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
 108         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
 109         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
 110         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
 111         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
 112         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
 113         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
 114         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
 115         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
 116         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
 117         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
 118         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
 119         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
 120         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
 121         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
 122         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
 123         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
 124         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
 125         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
 126         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
 127         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
 128
 129         {}
 130 };
 131
 132 /* Function forward declarations */
 133 static int e1000_setup_link(struct e1000_hw *hw);
 134 static int e1000_setup_fiber_link(struct e1000_hw *hw);
 135 static int e1000_setup_copper_link(struct e1000_hw *hw);
 136 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 137 static void e1000_config_collision_dist(struct e1000_hw *hw);
 138 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 139 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 140 static int e1000_check_for_link(struct e1000_hw *hw);
 141 static int e1000_wait_autoneg(struct e1000_hw *hw);
 142 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 143                                        uint16_t * duplex);
 144 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 145                               uint16_t * phy_data);
 146 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 147                                uint16_t phy_data);
 148 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 149 static int e1000_phy_reset(struct e1000_hw *hw);
 150 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 151 static void e1000_set_media_type(struct e1000_hw *hw);
 152
 153 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 154 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
 155 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 156
 157 #ifndef CONFIG_E1000_NO_NVM
 158 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 159 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
 160 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 161                 uint16_t words,
 162                 uint16_t *data);
 163 /******************************************************************************
 164  * Raises the EEPROM's clock input.
 165  *
 166  * hw - Struct containing variables accessed by shared code
 167  * eecd - EECD's current value
 168  *****************************************************************************/
 169 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 170 {
 171         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 172          * wait 50 microseconds.
 173          */
 174         *eecd = *eecd | E1000_EECD_SK;
 175         E1000_WRITE_REG(hw, EECD, *eecd);
 176         E1000_WRITE_FLUSH(hw);
 177         udelay(50);
 178 }
 179
 180 /******************************************************************************
 181  * Lowers the EEPROM's clock input.
 182  *
 183  * hw - Struct containing variables accessed by shared code
 184  * eecd - EECD's current value
 185  *****************************************************************************/
 186 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 187 {
 188         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 189          * wait 50 microseconds.
 190          */
 191         *eecd = *eecd & ~E1000_EECD_SK;
 192         E1000_WRITE_REG(hw, EECD, *eecd);
 193         E1000_WRITE_FLUSH(hw);
 194         udelay(50);
 195 }
 196
 197 /******************************************************************************
 198  * Shift data bits out to the EEPROM.
 199  *
 200  * hw - Struct containing variables accessed by shared code
 201  * data - data to send to the EEPROM
 202  * count - number of bits to shift out
 203  *****************************************************************************/
 204 static void
 205 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 206 {
 207         uint32_t eecd;
 208         uint32_t mask;
 209
 210         /* We need to shift "count" bits out to the EEPROM. So, value in the
 211          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 212          * In order to do this, "data" must be broken down into bits.
 213          */
 214         mask = 0x01 << (count - 1);
 215         eecd = E1000_READ_REG(hw, EECD);
 216         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 217         do {
 218                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 219                  * and then raising and then lowering the clock (the SK bit controls
 220                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 221                  * by setting "DI" to "0" and then raising and then lowering the clock.
 222                  */
 223                 eecd &= ~E1000_EECD_DI;
 224
 225                 if (data & mask)
 226                         eecd |= E1000_EECD_DI;
 227
 228                 E1000_WRITE_REG(hw, EECD, eecd);
 229                 E1000_WRITE_FLUSH(hw);
 230
 231                 udelay(50);
 232
 233                 e1000_raise_ee_clk(hw, &eecd);
 234                 e1000_lower_ee_clk(hw, &eecd);
 235
 236                 mask = mask >> 1;
 237
 238         } while (mask);
 239
 240         /* We leave the "DI" bit set to "0" when we leave this routine. */
 241         eecd &= ~E1000_EECD_DI;
 242         E1000_WRITE_REG(hw, EECD, eecd);
 243 }
 244
 245 /******************************************************************************
 246  * Shift data bits in from the EEPROM
 247  *
 248  * hw - Struct containing variables accessed by shared code
 249  *****************************************************************************/
 250 static uint16_t
 251 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 252 {
 253         uint32_t eecd;
 254         uint32_t i;
 255         uint16_t data;
 256
 257         /* In order to read a register from the EEPROM, we need to shift 'count'
 258          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 259          * input to the EEPROM (setting the SK bit), and then reading the
 260          * value of the "DO" bit.  During this "shifting in" process the
 261          * "DI" bit should always be clear.
 262          */
 263
 264         eecd = E1000_READ_REG(hw, EECD);
 265
 266         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 267         data = 0;
 268
 269         for (i = 0; i < count; i++) {
 270                 data = data << 1;
 271                 e1000_raise_ee_clk(hw, &eecd);
 272
 273                 eecd = E1000_READ_REG(hw, EECD);
 274
 275                 eecd &= ~(E1000_EECD_DI);
 276                 if (eecd & E1000_EECD_DO)
 277                         data |= 1;
 278
 279                 e1000_lower_ee_clk(hw, &eecd);
 280         }
 281
 282         return data;
 283 }
 284
 285 /******************************************************************************
 286  * Returns EEPROM to a "standby" state
 287  *
 288  * hw - Struct containing variables accessed by shared code
 289  *****************************************************************************/
 290 void e1000_standby_eeprom(struct e1000_hw *hw)
 291 {
 292         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 293         uint32_t eecd;
 294
 295         eecd = E1000_READ_REG(hw, EECD);
 296
 297         if (eeprom->type == e1000_eeprom_microwire) {
 298                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 299                 E1000_WRITE_REG(hw, EECD, eecd);
 300                 E1000_WRITE_FLUSH(hw);
 301                 udelay(eeprom->delay_usec);
 302
 303                 /* Clock high */
 304                 eecd |= E1000_EECD_SK;
 305                 E1000_WRITE_REG(hw, EECD, eecd);
 306                 E1000_WRITE_FLUSH(hw);
 307                 udelay(eeprom->delay_usec);
 308
 309                 /* Select EEPROM */
 310                 eecd |= E1000_EECD_CS;
 311                 E1000_WRITE_REG(hw, EECD, eecd);
 312                 E1000_WRITE_FLUSH(hw);
 313                 udelay(eeprom->delay_usec);
 314
 315                 /* Clock low */
 316                 eecd &= ~E1000_EECD_SK;
 317                 E1000_WRITE_REG(hw, EECD, eecd);
 318                 E1000_WRITE_FLUSH(hw);
 319                 udelay(eeprom->delay_usec);
 320         } else if (eeprom->type == e1000_eeprom_spi) {
 321                 /* Toggle CS to flush commands */
 322                 eecd |= E1000_EECD_CS;
 323                 E1000_WRITE_REG(hw, EECD, eecd);
 324                 E1000_WRITE_FLUSH(hw);
 325                 udelay(eeprom->delay_usec);
 326                 eecd &= ~E1000_EECD_CS;
 327                 E1000_WRITE_REG(hw, EECD, eecd);
 328                 E1000_WRITE_FLUSH(hw);
 329                 udelay(eeprom->delay_usec);
 330         }
 331 }
 332
 333 /***************************************************************************
 334 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 335 *
 336 * hw - Struct containing variables accessed by shared code
 337 ****************************************************************************/
 338 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 339 {
 340         uint32_t eecd = 0;
 341
 342         DEBUGFUNC();
 343
 344         if (hw->mac_type == e1000_ich8lan)
 345                 return false;
 346
 347         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 348                 eecd = E1000_READ_REG(hw, EECD);
 349
 350                 /* Isolate bits 15 & 16 */
 351                 eecd = ((eecd >> 15) & 0x03);
 352
 353                 /* If both bits are set, device is Flash type */
 354                 if (eecd == 0x03)
 355                         return false;
 356         }
 357         return true;
 358 }
 359
 360 /******************************************************************************
 361  * Prepares EEPROM for access
 362  *
 363  * hw - Struct containing variables accessed by shared code
 364  *
 365  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 366  * function should be called before issuing a command to the EEPROM.
 367  *****************************************************************************/
 368 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 369 {
 370         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 371         uint32_t eecd, i = 0;
 372
 373         DEBUGFUNC();
 374
 375         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 376                 return -E1000_ERR_SWFW_SYNC;
 377         eecd = E1000_READ_REG(hw, EECD);
 378
 379         if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
 380                 /* Request EEPROM Access */
 381                 if (hw->mac_type > e1000_82544) {
 382                         eecd |= E1000_EECD_REQ;
 383                         E1000_WRITE_REG(hw, EECD, eecd);
 384                         eecd = E1000_READ_REG(hw, EECD);
 385                         while ((!(eecd & E1000_EECD_GNT)) &&
 386                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 387                                 i++;
 388                                 udelay(5);
 389                                 eecd = E1000_READ_REG(hw, EECD);
 390                         }
 391                         if (!(eecd & E1000_EECD_GNT)) {
 392                                 eecd &= ~E1000_EECD_REQ;
 393                                 E1000_WRITE_REG(hw, EECD, eecd);
 394                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 395                                 return -E1000_ERR_EEPROM;
 396                         }
 397                 }
 398         }
 399
 400         /* Setup EEPROM for Read/Write */
 401
 402         if (eeprom->type == e1000_eeprom_microwire) {
 403                 /* Clear SK and DI */
 404                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 405                 E1000_WRITE_REG(hw, EECD, eecd);
 406
 407                 /* Set CS */
 408                 eecd |= E1000_EECD_CS;
 409                 E1000_WRITE_REG(hw, EECD, eecd);
 410         } else if (eeprom->type == e1000_eeprom_spi) {
 411                 /* Clear SK and CS */
 412                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 413                 E1000_WRITE_REG(hw, EECD, eecd);
 414                 udelay(1);
 415         }
 416
 417         return E1000_SUCCESS;
 418 }
 419
 420 /******************************************************************************
 421  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 422  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 423  * registers must be mapped, or this will crash.
 424  *
 425  * hw - Struct containing variables accessed by shared code
 426  *****************************************************************************/
 427 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 428 {
 429         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 430         uint32_t eecd;
 431         int32_t ret_val = E1000_SUCCESS;
 432         uint16_t eeprom_size;
 433
 434         if (hw->mac_type == e1000_igb)
 435                 eecd = E1000_READ_REG(hw, I210_EECD);
 436         else
 437                 eecd = E1000_READ_REG(hw, EECD);
 438
 439         DEBUGFUNC();
 440
 441         switch (hw->mac_type) {
 442         case e1000_82542_rev2_0:
 443         case e1000_82542_rev2_1:
 444         case e1000_82543:
 445         case e1000_82544:
 446                 eeprom->type = e1000_eeprom_microwire;
 447                 eeprom->word_size = 64;
 448                 eeprom->opcode_bits = 3;
 449                 eeprom->address_bits = 6;
 450                 eeprom->delay_usec = 50;
 451                 eeprom->use_eerd = false;
 452                 eeprom->use_eewr = false;
 453         break;
 454         case e1000_82540:
 455         case e1000_82545:
 456         case e1000_82545_rev_3:
 457         case e1000_82546:
 458         case e1000_82546_rev_3:
 459                 eeprom->type = e1000_eeprom_microwire;
 460                 eeprom->opcode_bits = 3;
 461                 eeprom->delay_usec = 50;
 462                 if (eecd & E1000_EECD_SIZE) {
 463                         eeprom->word_size = 256;
 464                         eeprom->address_bits = 8;
 465                 } else {
 466                         eeprom->word_size = 64;
 467                         eeprom->address_bits = 6;
 468                 }
 469                 eeprom->use_eerd = false;
 470                 eeprom->use_eewr = false;
 471                 break;
 472         case e1000_82541:
 473         case e1000_82541_rev_2:
 474         case e1000_82547:
 475         case e1000_82547_rev_2:
 476                 if (eecd & E1000_EECD_TYPE) {
 477                         eeprom->type = e1000_eeprom_spi;
 478                         eeprom->opcode_bits = 8;
 479                         eeprom->delay_usec = 1;
 480                         if (eecd & E1000_EECD_ADDR_BITS) {
 481                                 eeprom->page_size = 32;
 482                                 eeprom->address_bits = 16;
 483                         } else {
 484                                 eeprom->page_size = 8;
 485                                 eeprom->address_bits = 8;
 486                         }
 487                 } else {
 488                         eeprom->type = e1000_eeprom_microwire;
 489                         eeprom->opcode_bits = 3;
 490                         eeprom->delay_usec = 50;
 491                         if (eecd & E1000_EECD_ADDR_BITS) {
 492                                 eeprom->word_size = 256;
 493                                 eeprom->address_bits = 8;
 494                         } else {
 495                                 eeprom->word_size = 64;
 496                                 eeprom->address_bits = 6;
 497                         }
 498                 }
 499                 eeprom->use_eerd = false;
 500                 eeprom->use_eewr = false;
 501                 break;
 502         case e1000_82571:
 503         case e1000_82572:
 504                 eeprom->type = e1000_eeprom_spi;
 505                 eeprom->opcode_bits = 8;
 506                 eeprom->delay_usec = 1;
 507                 if (eecd & E1000_EECD_ADDR_BITS) {
 508                         eeprom->page_size = 32;
 509                         eeprom->address_bits = 16;
 510                 } else {
 511                         eeprom->page_size = 8;
 512                         eeprom->address_bits = 8;
 513                 }
 514                 eeprom->use_eerd = false;
 515                 eeprom->use_eewr = false;
 516                 break;
 517         case e1000_82573:
 518         case e1000_82574:
 519                 eeprom->type = e1000_eeprom_spi;
 520                 eeprom->opcode_bits = 8;
 521                 eeprom->delay_usec = 1;
 522                 if (eecd & E1000_EECD_ADDR_BITS) {
 523                         eeprom->page_size = 32;
 524                         eeprom->address_bits = 16;
 525                 } else {
 526                         eeprom->page_size = 8;
 527                         eeprom->address_bits = 8;
 528                 }
 529                 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 530                         eeprom->use_eerd = true;
 531                         eeprom->use_eewr = true;
 532
 533                         eeprom->type = e1000_eeprom_flash;
 534                         eeprom->word_size = 2048;
 535
 536                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 537                  * Flash update issue on parts which use a FLASH for NVM. */
 538                         eecd &= ~E1000_EECD_AUPDEN;
 539                         E1000_WRITE_REG(hw, EECD, eecd);
 540                 }
 541                 break;
 542         case e1000_80003es2lan:
 543                 eeprom->type = e1000_eeprom_spi;
 544                 eeprom->opcode_bits = 8;
 545                 eeprom->delay_usec = 1;
 546                 if (eecd & E1000_EECD_ADDR_BITS) {
 547                         eeprom->page_size = 32;
 548                         eeprom->address_bits = 16;
 549                 } else {
 550                         eeprom->page_size = 8;
 551                         eeprom->address_bits = 8;
 552                 }
 553                 eeprom->use_eerd = true;
 554                 eeprom->use_eewr = false;
 555                 break;
 556         case e1000_igb:
 557                 /* i210 has 4k of iNVM mapped as EEPROM */
 558                 eeprom->type = e1000_eeprom_invm;
 559                 eeprom->opcode_bits = 8;
 560                 eeprom->delay_usec = 1;
 561                 eeprom->page_size = 32;
 562                 eeprom->address_bits = 16;
 563                 eeprom->use_eerd = true;
 564                 eeprom->use_eewr = false;
 565                 break;
 566         default:
 567                 break;
 568         }
 569
 570         if (eeprom->type == e1000_eeprom_spi ||
 571             eeprom->type == e1000_eeprom_invm) {
 572                 /* eeprom_size will be an enum [0..8] that maps
 573                  * to eeprom sizes 128B to
 574                  * 32KB (incremented by powers of 2).
 575                  */
 576                 if (hw->mac_type <= e1000_82547_rev_2) {
 577                         /* Set to default value for initial eeprom read. */
 578                         eeprom->word_size = 64;
 579                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 580                                         &eeprom_size);
 581                         if (ret_val)
 582                                 return ret_val;
 583                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 584                                 >> EEPROM_SIZE_SHIFT;
 585                         /* 256B eeprom size was not supported in earlier
 586                          * hardware, so we bump eeprom_size up one to
 587                          * ensure that "1" (which maps to 256B) is never
 588                          * the result used in the shifting logic below. */
 589                         if (eeprom_size)
 590                                 eeprom_size++;
 591                 } else {
 592                         eeprom_size = (uint16_t)((eecd &
 593                                 E1000_EECD_SIZE_EX_MASK) >>
 594                                 E1000_EECD_SIZE_EX_SHIFT);
 595                 }
 596
 597                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 598         }
 599         return ret_val;
 600 }
 601
 602 /******************************************************************************
 603  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 604  *
 605  * hw - Struct containing variables accessed by shared code
 606  *****************************************************************************/
 607 static int32_t
 608 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 609 {
 610         uint32_t attempts = 100000;
 611         uint32_t i, reg = 0;
 612         int32_t done = E1000_ERR_EEPROM;
 613
 614         for (i = 0; i < attempts; i++) {
 615                 if (eerd == E1000_EEPROM_POLL_READ) {
 616                         if (hw->mac_type == e1000_igb)
 617                                 reg = E1000_READ_REG(hw, I210_EERD);
 618                         else
 619                                 reg = E1000_READ_REG(hw, EERD);
 620                 } else {
 621                         if (hw->mac_type == e1000_igb)
 622                                 reg = E1000_READ_REG(hw, I210_EEWR);
 623                         else
 624                                 reg = E1000_READ_REG(hw, EEWR);
 625                 }
 626
 627                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 628                         done = E1000_SUCCESS;
 629                         break;
 630                 }
 631                 udelay(5);
 632         }
 633
 634         return done;
 635 }
 636
 637 /******************************************************************************
 638  * Reads a 16 bit word from the EEPROM using the EERD register.
 639  *
 640  * hw - Struct containing variables accessed by shared code
 641  * offset - offset of  word in the EEPROM to read
 642  * data - word read from the EEPROM
 643  * words - number of words to read
 644  *****************************************************************************/
 645 static int32_t
 646 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 647                         uint16_t offset,
 648                         uint16_t words,
 649                         uint16_t *data)
 650 {
 651         uint32_t i, eerd = 0;
 652         int32_t error = 0;
 653
 654         for (i = 0; i < words; i++) {
 655                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 656                         E1000_EEPROM_RW_REG_START;
 657
 658                 if (hw->mac_type == e1000_igb)
 659                         E1000_WRITE_REG(hw, I210_EERD, eerd);
 660                 else
 661                         E1000_WRITE_REG(hw, EERD, eerd);
 662
 663                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 664
 665                 if (error)
 666                         break;
 667
 668                 if (hw->mac_type == e1000_igb) {
 669                         data[i] = (E1000_READ_REG(hw, I210_EERD) >>
 670                                 E1000_EEPROM_RW_REG_DATA);
 671                 } else {
 672                         data[i] = (E1000_READ_REG(hw, EERD) >>
 673                                 E1000_EEPROM_RW_REG_DATA);
 674                 }
 675
 676         }
 677
 678         return error;
 679 }
 680
 681 void e1000_release_eeprom(struct e1000_hw *hw)
 682 {
 683         uint32_t eecd;
 684
 685         DEBUGFUNC();
 686
 687         eecd = E1000_READ_REG(hw, EECD);
 688
 689         if (hw->eeprom.type == e1000_eeprom_spi) {
 690                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 691                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 692
 693                 E1000_WRITE_REG(hw, EECD, eecd);
 694
 695                 udelay(hw->eeprom.delay_usec);
 696         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 697                 /* cleanup eeprom */
 698
 699                 /* CS on Microwire is active-high */
 700                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 701
 702                 E1000_WRITE_REG(hw, EECD, eecd);
 703
 704                 /* Rising edge of clock */
 705                 eecd |= E1000_EECD_SK;
 706                 E1000_WRITE_REG(hw, EECD, eecd);
 707                 E1000_WRITE_FLUSH(hw);
 708                 udelay(hw->eeprom.delay_usec);
 709
 710                 /* Falling edge of clock */
 711                 eecd &= ~E1000_EECD_SK;
 712                 E1000_WRITE_REG(hw, EECD, eecd);
 713                 E1000_WRITE_FLUSH(hw);
 714                 udelay(hw->eeprom.delay_usec);
 715         }
 716
 717         /* Stop requesting EEPROM access */
 718         if (hw->mac_type > e1000_82544) {
 719                 eecd &= ~E1000_EECD_REQ;
 720                 E1000_WRITE_REG(hw, EECD, eecd);
 721         }
 722
 723         e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 724 }
 725
 726 /******************************************************************************
 727  * Reads a 16 bit word from the EEPROM.
 728  *
 729  * hw - Struct containing variables accessed by shared code
 730  *****************************************************************************/
 731 static int32_t
 732 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 733 {
 734         uint16_t retry_count = 0;
 735         uint8_t spi_stat_reg;
 736
 737         DEBUGFUNC();
 738
 739         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 740          * EEPROM will signal that the command has been completed by clearing
 741          * bit 0 of the internal status register.  If it's not cleared within
 742          * 5 milliseconds, then error out.
 743          */
 744         retry_count = 0;
 745         do {
 746                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 747                         hw->eeprom.opcode_bits);
 748                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 749                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 750                         break;
 751
 752                 udelay(5);
 753                 retry_count += 5;
 754
 755                 e1000_standby_eeprom(hw);
 756         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 757
 758         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 759          * only 0-5mSec on 5V devices)
 760          */
 761         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 762                 DEBUGOUT("SPI EEPROM Status error\n");
 763                 return -E1000_ERR_EEPROM;
 764         }
 765
 766         return E1000_SUCCESS;
 767 }
 768
 769 /******************************************************************************
 770  * Reads a 16 bit word from the EEPROM.
 771  *
 772  * hw - Struct containing variables accessed by shared code
 773  * offset - offset of  word in the EEPROM to read
 774  * data - word read from the EEPROM
 775  *****************************************************************************/
 776 static int32_t
 777 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 778                 uint16_t words, uint16_t *data)
 779 {
 780         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 781         uint32_t i = 0;
 782
 783         DEBUGFUNC();
 784
 785         /* If eeprom is not yet detected, do so now */
 786         if (eeprom->word_size == 0)
 787                 e1000_init_eeprom_params(hw);
 788
 789         /* A check for invalid values:  offset too large, too many words,
 790          * and not enough words.
 791          */
 792         if ((offset >= eeprom->word_size) ||
 793                 (words > eeprom->word_size - offset) ||
 794                 (words == 0)) {
 795                 DEBUGOUT("\"words\" parameter out of bounds."
 796                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 797                 return -E1000_ERR_EEPROM;
 798         }
 799
 800         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 801          * directly. In this case, we need to acquire the EEPROM so that
 802          * FW or other port software does not interrupt.
 803          */
 804         if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 805                 hw->eeprom.use_eerd == false) {
 806
 807                 /* Prepare the EEPROM for bit-bang reading */
 808                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 809                         return -E1000_ERR_EEPROM;
 810         }
 811
 812         /* Eerd register EEPROM access requires no eeprom aquire/release */
 813         if (eeprom->use_eerd == true)
 814                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 815
 816         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 817          * acquired the EEPROM at this point, so any returns should relase it */
 818         if (eeprom->type == e1000_eeprom_spi) {
 819                 uint16_t word_in;
 820                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 821
 822                 if (e1000_spi_eeprom_ready(hw)) {
 823                         e1000_release_eeprom(hw);
 824                         return -E1000_ERR_EEPROM;
 825                 }
 826
 827                 e1000_standby_eeprom(hw);
 828
 829                 /* Some SPI eeproms use the 8th address bit embedded in
 830                  * the opcode */
 831                 if ((eeprom->address_bits == 8) && (offset >= 128))
 832                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 833
 834                 /* Send the READ command (opcode + addr)  */
 835                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 836                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 837                                 eeprom->address_bits);
 838
 839                 /* Read the data.  The address of the eeprom internally
 840                  * increments with each byte (spi) being read, saving on the
 841                  * overhead of eeprom setup and tear-down.  The address
 842                  * counter will roll over if reading beyond the size of
 843                  * the eeprom, thus allowing the entire memory to be read
 844                  * starting from any offset. */
 845                 for (i = 0; i < words; i++) {
 846                         word_in = e1000_shift_in_ee_bits(hw, 16);
 847                         data[i] = (word_in >> 8) | (word_in << 8);
 848                 }
 849         } else if (eeprom->type == e1000_eeprom_microwire) {
 850                 for (i = 0; i < words; i++) {
 851                         /* Send the READ command (opcode + addr)  */
 852                         e1000_shift_out_ee_bits(hw,
 853                                 EEPROM_READ_OPCODE_MICROWIRE,
 854                                 eeprom->opcode_bits);
 855                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 856                                 eeprom->address_bits);
 857
 858                         /* Read the data.  For microwire, each word requires
 859                          * the overhead of eeprom setup and tear-down. */
 860                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 861                         e1000_standby_eeprom(hw);
 862                 }
 863         }
 864
 865         /* End this read operation */
 866         e1000_release_eeprom(hw);
 867
 868         return E1000_SUCCESS;
 869 }
 870
 871 #ifndef CONFIG_DM_ETH
 872 /******************************************************************************
 873  *  e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
 874  *  @hw: pointer to the HW structure
 875  *  @offset: offset within the Shadow Ram to be written to
 876  *  @words: number of words to write
 877  *  @data: 16 bit word(s) to be written to the Shadow Ram
 878  *
 879  *  Writes data to Shadow Ram at offset using EEWR register.
 880  *
 881  *  If e1000_update_eeprom_checksum_i210 is not called after this function, the
 882  *  Shadow Ram will most likely contain an invalid checksum.
 883  *****************************************************************************/
 884 static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
 885                                        uint16_t words, uint16_t *data)
 886 {
 887         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 888         uint32_t i, k, eewr = 0;
 889         uint32_t attempts = 100000;
 890         int32_t ret_val = 0;
 891
 892         /* A check for invalid values:  offset too large, too many words,
 893          * too many words for the offset, and not enough words.
 894          */
 895         if ((offset >= eeprom->word_size) ||
 896             (words > (eeprom->word_size - offset)) || (words == 0)) {
 897                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 898                 ret_val = -E1000_ERR_EEPROM;
 899                 goto out;
 900         }
 901
 902         for (i = 0; i < words; i++) {
 903                 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
 904                                 | (data[i] << E1000_EEPROM_RW_REG_DATA) |
 905                                 E1000_EEPROM_RW_REG_START;
 906
 907                 E1000_WRITE_REG(hw, I210_EEWR, eewr);
 908
 909                 for (k = 0; k < attempts; k++) {
 910                         if (E1000_EEPROM_RW_REG_DONE &
 911                             E1000_READ_REG(hw, I210_EEWR)) {
 912                                 ret_val = 0;
 913                                 break;
 914                         }
 915                         udelay(5);
 916                 }
 917
 918                 if (ret_val) {
 919                         DEBUGOUT("Shadow RAM write EEWR timed out\n");
 920                         break;
 921                 }
 922         }
 923
 924 out:
 925         return ret_val;
 926 }
 927
 928 /******************************************************************************
 929  *  e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
 930  *  @hw: pointer to the HW structure
 931  *
 932  *****************************************************************************/
 933 static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
 934 {
 935         int32_t ret_val = -E1000_ERR_EEPROM;
 936         uint32_t i, reg;
 937
 938         for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
 939                 reg = E1000_READ_REG(hw, EECD);
 940                 if (reg & E1000_EECD_FLUDONE_I210) {
 941                         ret_val = 0;
 942                         break;
 943                 }
 944                 udelay(5);
 945         }
 946
 947         return ret_val;
 948 }
 949
 950 /******************************************************************************
 951  *  e1000_update_flash_i210 - Commit EEPROM to the flash
 952  *  @hw: pointer to the HW structure
 953  *
 954  *****************************************************************************/
 955 static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
 956 {
 957         int32_t ret_val = 0;
 958         uint32_t flup;
 959
 960         ret_val = e1000_pool_flash_update_done_i210(hw);
 961         if (ret_val == -E1000_ERR_EEPROM) {
 962                 DEBUGOUT("Flash update time out\n");
 963                 goto out;
 964         }
 965
 966         flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
 967         E1000_WRITE_REG(hw, EECD, flup);
 968
 969         ret_val = e1000_pool_flash_update_done_i210(hw);
 970         if (ret_val)
 971                 DEBUGOUT("Flash update time out\n");
 972         else
 973                 DEBUGOUT("Flash update complete\n");
 974
 975 out:
 976         return ret_val;
 977 }
 978
 979 /******************************************************************************
 980  *  e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
 981  *  @hw: pointer to the HW structure
 982  *
 983  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 984  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 985  *  value to the EEPROM. Next commit EEPROM data onto the Flash.
 986  *****************************************************************************/
 987 static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
 988 {
 989         int32_t ret_val = 0;
 990         uint16_t checksum = 0;
 991         uint16_t i, nvm_data;
 992
 993         /* Read the first word from the EEPROM. If this times out or fails, do
 994          * not continue or we could be in for a very long wait while every
 995          * EEPROM read fails
 996          */
 997         ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
 998         if (ret_val) {
 999                 DEBUGOUT("EEPROM read failed\n");
1000                 goto out;
1001         }
1002
1003         if (!(e1000_get_hw_eeprom_semaphore(hw))) {
1004                 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
1005                  * because we do not want to take the synchronization
1006                  * semaphores twice here.
1007                  */
1008
1009                 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1010                         ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1011                         if (ret_val) {
1012                                 e1000_put_hw_eeprom_semaphore(hw);
1013                                 DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1014                                 goto out;
1015                         }
1016                         checksum += nvm_data;
1017                 }
1018                 checksum = (uint16_t)EEPROM_SUM - checksum;
1019                 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1020                                                   &checksum);
1021                 if (ret_val) {
1022                         e1000_put_hw_eeprom_semaphore(hw);
1023                         DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1024                         goto out;
1025                 }
1026
1027                 e1000_put_hw_eeprom_semaphore(hw);
1028
1029                 ret_val = e1000_update_flash_i210(hw);
1030         } else {
1031                 ret_val = -E1000_ERR_SWFW_SYNC;
1032         }
1033
1034 out:
1035         return ret_val;
1036 }
1037 #endif
1038
1039 /******************************************************************************
1040  * Verifies that the EEPROM has a valid checksum
1041  *
1042  * hw - Struct containing variables accessed by shared code
1043  *
1044  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
1045  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
1046  * valid.
1047  *****************************************************************************/
1048 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
1049 {
1050         uint16_t i, checksum, checksum_reg, *buf;
1051
1052         DEBUGFUNC();
1053
1054         /* Allocate a temporary buffer */
1055         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1056         if (!buf) {
1057                 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
1058                 return -E1000_ERR_EEPROM;
1059         }
1060
1061         /* Read the EEPROM */
1062         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
1063                 E1000_ERR(hw, "Unable to read EEPROM!\n");
1064                 return -E1000_ERR_EEPROM;
1065         }
1066
1067         /* Compute the checksum */
1068         checksum = 0;
1069         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1070                 checksum += buf[i];
1071         checksum = ((uint16_t)EEPROM_SUM) - checksum;
1072         checksum_reg = buf[i];
1073
1074         /* Verify it! */
1075         if (checksum == checksum_reg)
1076                 return 0;
1077
1078         /* Hrm, verification failed, print an error */
1079         E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1080         E1000_ERR(hw, "  ...register was 0x%04hx, calculated 0x%04hx\n",
1081                   checksum_reg, checksum);
1082
1083         return -E1000_ERR_EEPROM;
1084 }
1085 #endif /* CONFIG_E1000_NO_NVM */
1086
1087 /*****************************************************************************
1088  * Set PHY to class A mode
1089  * Assumes the following operations will follow to enable the new class mode.
1090  *  1. Do a PHY soft reset
1091  *  2. Restart auto-negotiation or force link.
1092  *
1093  * hw - Struct containing variables accessed by shared code
1094  ****************************************************************************/
1095 static int32_t
1096 e1000_set_phy_mode(struct e1000_hw *hw)
1097 {
1098 #ifndef CONFIG_E1000_NO_NVM
1099         int32_t ret_val;
1100         uint16_t eeprom_data;
1101
1102         DEBUGFUNC();
1103
1104         if ((hw->mac_type == e1000_82545_rev_3) &&
1105                 (hw->media_type == e1000_media_type_copper)) {
1106                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1107                                 1, &eeprom_data);
1108                 if (ret_val)
1109                         return ret_val;
1110
1111                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1112                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
1113                         ret_val = e1000_write_phy_reg(hw,
1114                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
1115                         if (ret_val)
1116                                 return ret_val;
1117                         ret_val = e1000_write_phy_reg(hw,
1118                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
1119                         if (ret_val)
1120                                 return ret_val;
1121
1122                         hw->phy_reset_disable = false;
1123                 }
1124         }
1125 #endif
1126         return E1000_SUCCESS;
1127 }
1128
1129 #ifndef CONFIG_E1000_NO_NVM
1130 /***************************************************************************
1131  *
1132  * Obtaining software semaphore bit (SMBI) before resetting PHY.
1133  *
1134  * hw: Struct containing variables accessed by shared code
1135  *
1136  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1137  *            E1000_SUCCESS at any other case.
1138  *
1139  ***************************************************************************/
1140 static int32_t
1141 e1000_get_software_semaphore(struct e1000_hw *hw)
1142 {
1143          int32_t timeout = hw->eeprom.word_size + 1;
1144          uint32_t swsm;
1145
1146         DEBUGFUNC();
1147
1148         if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
1149                 return E1000_SUCCESS;
1150
1151         while (timeout) {
1152                 swsm = E1000_READ_REG(hw, SWSM);
1153                 /* If SMBI bit cleared, it is now set and we hold
1154                  * the semaphore */
1155                 if (!(swsm & E1000_SWSM_SMBI))
1156                         break;
1157                 mdelay(1);
1158                 timeout--;
1159         }
1160
1161         if (!timeout) {
1162                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1163                 return -E1000_ERR_RESET;
1164         }
1165
1166         return E1000_SUCCESS;
1167 }
1168 #endif
1169
1170 /***************************************************************************
1171  * This function clears HW semaphore bits.
1172  *
1173  * hw: Struct containing variables accessed by shared code
1174  *
1175  * returns: - None.
1176  *
1177  ***************************************************************************/
1178 static void
1179 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1180 {
1181 #ifndef CONFIG_E1000_NO_NVM
1182          uint32_t swsm;
1183
1184         DEBUGFUNC();
1185
1186         if (!hw->eeprom_semaphore_present)
1187                 return;
1188
1189         swsm = E1000_READ_REG(hw, SWSM);
1190         if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1191                 /* Release both semaphores. */
1192                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1193         } else
1194                 swsm &= ~(E1000_SWSM_SWESMBI);
1195         E1000_WRITE_REG(hw, SWSM, swsm);
1196 #endif
1197 }
1198
1199 /***************************************************************************
1200  *
1201  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1202  * adapter or Eeprom access.
1203  *
1204  * hw: Struct containing variables accessed by shared code
1205  *
1206  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1207  *            E1000_SUCCESS at any other case.
1208  *
1209  ***************************************************************************/
1210 static int32_t
1211 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1212 {
1213 #ifndef CONFIG_E1000_NO_NVM
1214         int32_t timeout;
1215         uint32_t swsm;
1216
1217         DEBUGFUNC();
1218
1219         if (!hw->eeprom_semaphore_present)
1220                 return E1000_SUCCESS;
1221
1222         if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1223                 /* Get the SW semaphore. */
1224                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1225                         return -E1000_ERR_EEPROM;
1226         }
1227
1228         /* Get the FW semaphore. */
1229         timeout = hw->eeprom.word_size + 1;
1230         while (timeout) {
1231                 swsm = E1000_READ_REG(hw, SWSM);
1232                 swsm |= E1000_SWSM_SWESMBI;
1233                 E1000_WRITE_REG(hw, SWSM, swsm);
1234                 /* if we managed to set the bit we got the semaphore. */
1235                 swsm = E1000_READ_REG(hw, SWSM);
1236                 if (swsm & E1000_SWSM_SWESMBI)
1237                         break;
1238
1239                 udelay(50);
1240                 timeout--;
1241         }
1242
1243         if (!timeout) {
1244                 /* Release semaphores */
1245                 e1000_put_hw_eeprom_semaphore(hw);
1246                 DEBUGOUT("Driver can't access the Eeprom - "
1247                                 "SWESMBI bit is set.\n");
1248                 return -E1000_ERR_EEPROM;
1249         }
1250 #endif
1251         return E1000_SUCCESS;
1252 }
1253
1254 /* Take ownership of the PHY */
1255 static int32_t
1256 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1257 {
1258         uint32_t swfw_sync = 0;
1259         uint32_t swmask = mask;
1260         uint32_t fwmask = mask << 16;
1261         int32_t timeout = 200;
1262
1263         DEBUGFUNC();
1264         while (timeout) {
1265                 if (e1000_get_hw_eeprom_semaphore(hw))
1266                         return -E1000_ERR_SWFW_SYNC;
1267
1268                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1269                 if (!(swfw_sync & (fwmask | swmask)))
1270                         break;
1271
1272                 /* firmware currently using resource (fwmask) */
1273                 /* or other software thread currently using resource (swmask) */
1274                 e1000_put_hw_eeprom_semaphore(hw);
1275                 mdelay(5);
1276                 timeout--;
1277         }
1278
1279         if (!timeout) {
1280                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1281                 return -E1000_ERR_SWFW_SYNC;
1282         }
1283
1284         swfw_sync |= swmask;
1285         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1286
1287         e1000_put_hw_eeprom_semaphore(hw);
1288         return E1000_SUCCESS;
1289 }
1290
1291 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1292 {
1293         uint32_t swfw_sync = 0;
1294
1295         DEBUGFUNC();
1296         while (e1000_get_hw_eeprom_semaphore(hw))
1297                 ; /* Empty */
1298
1299         swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1300         swfw_sync &= ~mask;
1301         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1302
1303         e1000_put_hw_eeprom_semaphore(hw);
1304 }
1305
1306 static bool e1000_is_second_port(struct e1000_hw *hw)
1307 {
1308         switch (hw->mac_type) {
1309         case e1000_80003es2lan:
1310         case e1000_82546:
1311         case e1000_82571:
1312                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1313                         return true;
1314                 /* Fallthrough */
1315         default:
1316                 return false;
1317         }
1318 }
1319
1320 #ifndef CONFIG_E1000_NO_NVM
1321 /******************************************************************************
1322  * Reads the adapter's MAC address from the EEPROM
1323  *
1324  * hw - Struct containing variables accessed by shared code
1325  * enetaddr - buffering where the MAC address will be stored
1326  *****************************************************************************/
1327 static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
1328                                            unsigned char enetaddr[6])
1329 {
1330         uint16_t offset;
1331         uint16_t eeprom_data;
1332         int i;
1333
1334         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1335                 offset = i >> 1;
1336                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1337                         DEBUGOUT("EEPROM Read Error\n");
1338                         return -E1000_ERR_EEPROM;
1339                 }
1340                 enetaddr[i] = eeprom_data & 0xff;
1341                 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1342         }
1343
1344         return 0;
1345 }
1346
1347 /******************************************************************************
1348  * Reads the adapter's MAC address from the RAL/RAH registers
1349  *
1350  * hw - Struct containing variables accessed by shared code
1351  * enetaddr - buffering where the MAC address will be stored
1352  *****************************************************************************/
1353 static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
1354                                          unsigned char enetaddr[6])
1355 {
1356         uint16_t offset, tmp;
1357         uint32_t reg_data = 0;
1358         int i;
1359
1360         if (hw->mac_type != e1000_igb)
1361                 return -E1000_ERR_MAC_TYPE;
1362
1363         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1364                 offset = i >> 1;
1365
1366                 if (offset == 0)
1367                         reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1368                 else if (offset == 1)
1369                         reg_data >>= 16;
1370                 else if (offset == 2)
1371                         reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1372                 tmp = reg_data & 0xffff;
1373
1374                 enetaddr[i] = tmp & 0xff;
1375                 enetaddr[i + 1] = (tmp >> 8) & 0xff;
1376         }
1377
1378         return 0;
1379 }
1380
1381 /******************************************************************************
1382  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1383  * second function of dual function devices
1384  *
1385  * hw - Struct containing variables accessed by shared code
1386  * enetaddr - buffering where the MAC address will be stored
1387  *****************************************************************************/
1388 static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1389 {
1390         int ret_val;
1391
1392         if (hw->mac_type == e1000_igb) {
1393                 /* i210 preloads MAC address into RAL/RAH registers */
1394                 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1395         } else {
1396                 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1397         }
1398         if (ret_val)
1399                 return ret_val;
1400
1401         /* Invert the last bit if this is the second device */
1402         if (e1000_is_second_port(hw))
1403                 enetaddr[5] ^= 1;
1404
1405         return 0;
1406 }
1407 #endif
1408
1409 /******************************************************************************
1410  * Initializes receive address filters.
1411  *
1412  * hw - Struct containing variables accessed by shared code
1413  *
1414  * Places the MAC address in receive address register 0 and clears the rest
1415  * of the receive addresss registers. Clears the multicast table. Assumes
1416  * the receiver is in reset when the routine is called.
1417  *****************************************************************************/
1418 static void
1419 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1420 {
1421         uint32_t i;
1422         uint32_t addr_low;
1423         uint32_t addr_high;
1424
1425         DEBUGFUNC();
1426
1427         /* Setup the receive address. */
1428         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1429         addr_low = (enetaddr[0] |
1430                     (enetaddr[1] << 8) |
1431                     (enetaddr[2] << 16) | (enetaddr[3] << 24));
1432
1433         addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1434
1435         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1436         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1437
1438         /* Zero out the other 15 receive addresses. */
1439         DEBUGOUT("Clearing RAR[1-15]\n");
1440         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1441                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1442                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1443         }
1444 }
1445
1446 /******************************************************************************
1447  * Clears the VLAN filer table
1448  *
1449  * hw - Struct containing variables accessed by shared code
1450  *****************************************************************************/
1451 static void
1452 e1000_clear_vfta(struct e1000_hw *hw)
1453 {
1454         uint32_t offset;
1455
1456         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1457                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1458 }
1459
1460 /******************************************************************************
1461  * Set the mac type member in the hw struct.
1462  *
1463  * hw - Struct containing variables accessed by shared code
1464  *****************************************************************************/
1465 int32_t
1466 e1000_set_mac_type(struct e1000_hw *hw)
1467 {
1468         DEBUGFUNC();
1469
1470         switch (hw->device_id) {
1471         case E1000_DEV_ID_82542:
1472                 switch (hw->revision_id) {
1473                 case E1000_82542_2_0_REV_ID:
1474                         hw->mac_type = e1000_82542_rev2_0;
1475                         break;
1476                 case E1000_82542_2_1_REV_ID:
1477                         hw->mac_type = e1000_82542_rev2_1;
1478                         break;
1479                 default:
1480                         /* Invalid 82542 revision ID */
1481                         return -E1000_ERR_MAC_TYPE;
1482                 }
1483                 break;
1484         case E1000_DEV_ID_82543GC_FIBER:
1485         case E1000_DEV_ID_82543GC_COPPER:
1486                 hw->mac_type = e1000_82543;
1487                 break;
1488         case E1000_DEV_ID_82544EI_COPPER:
1489         case E1000_DEV_ID_82544EI_FIBER:
1490         case E1000_DEV_ID_82544GC_COPPER:
1491         case E1000_DEV_ID_82544GC_LOM:
1492                 hw->mac_type = e1000_82544;
1493                 break;
1494         case E1000_DEV_ID_82540EM:
1495         case E1000_DEV_ID_82540EM_LOM:
1496         case E1000_DEV_ID_82540EP:
1497         case E1000_DEV_ID_82540EP_LOM:
1498         case E1000_DEV_ID_82540EP_LP:
1499                 hw->mac_type = e1000_82540;
1500                 break;
1501         case E1000_DEV_ID_82545EM_COPPER:
1502         case E1000_DEV_ID_82545EM_FIBER:
1503                 hw->mac_type = e1000_82545;
1504                 break;
1505         case E1000_DEV_ID_82545GM_COPPER:
1506         case E1000_DEV_ID_82545GM_FIBER:
1507         case E1000_DEV_ID_82545GM_SERDES:
1508                 hw->mac_type = e1000_82545_rev_3;
1509                 break;
1510         case E1000_DEV_ID_82546EB_COPPER:
1511         case E1000_DEV_ID_82546EB_FIBER:
1512         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1513                 hw->mac_type = e1000_82546;
1514                 break;
1515         case E1000_DEV_ID_82546GB_COPPER:
1516         case E1000_DEV_ID_82546GB_FIBER:
1517         case E1000_DEV_ID_82546GB_SERDES:
1518         case E1000_DEV_ID_82546GB_PCIE:
1519         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1520         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1521                 hw->mac_type = e1000_82546_rev_3;
1522                 break;
1523         case E1000_DEV_ID_82541EI:
1524         case E1000_DEV_ID_82541EI_MOBILE:
1525         case E1000_DEV_ID_82541ER_LOM:
1526                 hw->mac_type = e1000_82541;
1527                 break;
1528         case E1000_DEV_ID_82541ER:
1529         case E1000_DEV_ID_82541GI:
1530         case E1000_DEV_ID_82541GI_LF:
1531         case E1000_DEV_ID_82541GI_MOBILE:
1532                 hw->mac_type = e1000_82541_rev_2;
1533                 break;
1534         case E1000_DEV_ID_82547EI:
1535         case E1000_DEV_ID_82547EI_MOBILE:
1536                 hw->mac_type = e1000_82547;
1537                 break;
1538         case E1000_DEV_ID_82547GI:
1539                 hw->mac_type = e1000_82547_rev_2;
1540                 break;
1541         case E1000_DEV_ID_82571EB_COPPER:
1542         case E1000_DEV_ID_82571EB_FIBER:
1543         case E1000_DEV_ID_82571EB_SERDES:
1544         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1545         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1546         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1547         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1548         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1549         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1550                 hw->mac_type = e1000_82571;
1551                 break;
1552         case E1000_DEV_ID_82572EI_COPPER:
1553         case E1000_DEV_ID_82572EI_FIBER:
1554         case E1000_DEV_ID_82572EI_SERDES:
1555         case E1000_DEV_ID_82572EI:
1556                 hw->mac_type = e1000_82572;
1557                 break;
1558         case E1000_DEV_ID_82573E:
1559         case E1000_DEV_ID_82573E_IAMT:
1560         case E1000_DEV_ID_82573L:
1561                 hw->mac_type = e1000_82573;
1562                 break;
1563         case E1000_DEV_ID_82574L:
1564                 hw->mac_type = e1000_82574;
1565                 break;
1566         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1567         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1568         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1569         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1570                 hw->mac_type = e1000_80003es2lan;
1571                 break;
1572         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1573         case E1000_DEV_ID_ICH8_IGP_AMT:
1574         case E1000_DEV_ID_ICH8_IGP_C:
1575         case E1000_DEV_ID_ICH8_IFE:
1576         case E1000_DEV_ID_ICH8_IFE_GT:
1577         case E1000_DEV_ID_ICH8_IFE_G:
1578         case E1000_DEV_ID_ICH8_IGP_M:
1579                 hw->mac_type = e1000_ich8lan;
1580                 break;
1581         case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1582         case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1583         case PCI_DEVICE_ID_INTEL_I210_COPPER:
1584         case PCI_DEVICE_ID_INTEL_I211_COPPER:
1585         case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1586         case PCI_DEVICE_ID_INTEL_I210_SERDES:
1587         case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1588         case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1589                 hw->mac_type = e1000_igb;
1590                 break;
1591         default:
1592                 /* Should never have loaded on this device */
1593                 return -E1000_ERR_MAC_TYPE;
1594         }
1595         return E1000_SUCCESS;
1596 }
1597
1598 /******************************************************************************
1599  * Reset the transmit and receive units; mask and clear all interrupts.
1600  *
1601  * hw - Struct containing variables accessed by shared code
1602  *****************************************************************************/
1603 void
1604 e1000_reset_hw(struct e1000_hw *hw)
1605 {
1606         uint32_t ctrl;
1607         uint32_t ctrl_ext;
1608         uint32_t manc;
1609         uint32_t pba = 0;
1610         uint32_t reg;
1611
1612         DEBUGFUNC();
1613
1614         /* get the correct pba value for both PCI and PCIe*/
1615         if (hw->mac_type <  e1000_82571)
1616                 pba = E1000_DEFAULT_PCI_PBA;
1617         else
1618                 pba = E1000_DEFAULT_PCIE_PBA;
1619
1620         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1621         if (hw->mac_type == e1000_82542_rev2_0) {
1622                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1623 #ifdef CONFIG_DM_ETH
1624                 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1625                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1626 #else
1627                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1628                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1629 #endif
1630         }
1631
1632         /* Clear interrupt mask to stop board from generating interrupts */
1633         DEBUGOUT("Masking off all interrupts\n");
1634         if (hw->mac_type == e1000_igb)
1635                 E1000_WRITE_REG(hw, I210_IAM, 0);
1636         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1637
1638         /* Disable the Transmit and Receive units.  Then delay to allow
1639          * any pending transactions to complete before we hit the MAC with
1640          * the global reset.
1641          */
1642         E1000_WRITE_REG(hw, RCTL, 0);
1643         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1644         E1000_WRITE_FLUSH(hw);
1645
1646         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1647         hw->tbi_compatibility_on = false;
1648
1649         /* Delay to allow any outstanding PCI transactions to complete before
1650          * resetting the device
1651          */
1652         mdelay(10);
1653
1654         /* Issue a global reset to the MAC.  This will reset the chip's
1655          * transmit, receive, DMA, and link units.  It will not effect
1656          * the current PCI configuration.  The global reset bit is self-
1657          * clearing, and should clear within a microsecond.
1658          */
1659         DEBUGOUT("Issuing a global reset to MAC\n");
1660         ctrl = E1000_READ_REG(hw, CTRL);
1661
1662         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1663
1664         /* Force a reload from the EEPROM if necessary */
1665         if (hw->mac_type == e1000_igb) {
1666                 mdelay(20);
1667                 reg = E1000_READ_REG(hw, STATUS);
1668                 if (reg & E1000_STATUS_PF_RST_DONE)
1669                         DEBUGOUT("PF OK\n");
1670                 reg = E1000_READ_REG(hw, I210_EECD);
1671                 if (reg & E1000_EECD_AUTO_RD)
1672                         DEBUGOUT("EEC OK\n");
1673         } else if (hw->mac_type < e1000_82540) {
1674                 /* Wait for reset to complete */
1675                 udelay(10);
1676                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1677                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1678                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1679                 E1000_WRITE_FLUSH(hw);
1680                 /* Wait for EEPROM reload */
1681                 mdelay(2);
1682         } else {
1683                 /* Wait for EEPROM reload (it happens automatically) */
1684                 mdelay(4);
1685                 /* Dissable HW ARPs on ASF enabled adapters */
1686                 manc = E1000_READ_REG(hw, MANC);
1687                 manc &= ~(E1000_MANC_ARP_EN);
1688                 E1000_WRITE_REG(hw, MANC, manc);
1689         }
1690
1691         /* Clear interrupt mask to stop board from generating interrupts */
1692         DEBUGOUT("Masking off all interrupts\n");
1693         if (hw->mac_type == e1000_igb)
1694                 E1000_WRITE_REG(hw, I210_IAM, 0);
1695         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1696
1697         /* Clear any pending interrupt events. */
1698         E1000_READ_REG(hw, ICR);
1699
1700         /* If MWI was previously enabled, reenable it. */
1701         if (hw->mac_type == e1000_82542_rev2_0) {
1702 #ifdef CONFIG_DM_ETH
1703                 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1704 #else
1705                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1706 #endif
1707         }
1708         if (hw->mac_type != e1000_igb)
1709                 E1000_WRITE_REG(hw, PBA, pba);
1710 }
1711
1712 /******************************************************************************
1713  *
1714  * Initialize a number of hardware-dependent bits
1715  *
1716  * hw: Struct containing variables accessed by shared code
1717  *
1718  * This function contains hardware limitation workarounds for PCI-E adapters
1719  *
1720  *****************************************************************************/
1721 static void
1722 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1723 {
1724         if ((hw->mac_type >= e1000_82571) &&
1725                         (!hw->initialize_hw_bits_disable)) {
1726                 /* Settings common to all PCI-express silicon */
1727                 uint32_t reg_ctrl, reg_ctrl_ext;
1728                 uint32_t reg_tarc0, reg_tarc1;
1729                 uint32_t reg_tctl;
1730                 uint32_t reg_txdctl, reg_txdctl1;
1731
1732                 /* link autonegotiation/sync workarounds */
1733                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1734                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1735
1736                 /* Enable not-done TX descriptor counting */
1737                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1738                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1739                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1740
1741                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1742                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1743                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1744
1745
1746                 switch (hw->mac_type) {
1747                 case e1000_igb:                 /* IGB is cool */
1748                         return;
1749                 case e1000_82571:
1750                 case e1000_82572:
1751                         /* Clear PHY TX compatible mode bits */
1752                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1753                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1754
1755                         /* link autonegotiation/sync workarounds */
1756                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1757
1758                         /* TX ring control fixes */
1759                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1760
1761                         /* Multiple read bit is reversed polarity */
1762                         reg_tctl = E1000_READ_REG(hw, TCTL);
1763                         if (reg_tctl & E1000_TCTL_MULR)
1764                                 reg_tarc1 &= ~(1 << 28);
1765                         else
1766                                 reg_tarc1 |= (1 << 28);
1767
1768                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1769                         break;
1770                 case e1000_82573:
1771                 case e1000_82574:
1772                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1773                         reg_ctrl_ext &= ~(1 << 23);
1774                         reg_ctrl_ext |= (1 << 22);
1775
1776                         /* TX byte count fix */
1777                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1778                         reg_ctrl &= ~(1 << 29);
1779
1780                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1781                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1782                         break;
1783                 case e1000_80003es2lan:
1784         /* improve small packet performace for fiber/serdes */
1785                         if ((hw->media_type == e1000_media_type_fiber)
1786                         || (hw->media_type ==
1787                                 e1000_media_type_internal_serdes)) {
1788                                 reg_tarc0 &= ~(1 << 20);
1789                         }
1790
1791                 /* Multiple read bit is reversed polarity */
1792                         reg_tctl = E1000_READ_REG(hw, TCTL);
1793                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1794                         if (reg_tctl & E1000_TCTL_MULR)
1795                                 reg_tarc1 &= ~(1 << 28);
1796                         else
1797                                 reg_tarc1 |= (1 << 28);
1798
1799                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1800                         break;
1801                 case e1000_ich8lan:
1802                         /* Reduce concurrent DMA requests to 3 from 4 */
1803                         if ((hw->revision_id < 3) ||
1804                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1805                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1806                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1807
1808                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1809                         reg_ctrl_ext |= (1 << 22);
1810                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1811
1812                         /* workaround TX hang with TSO=on */
1813                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1814
1815                         /* Multiple read bit is reversed polarity */
1816                         reg_tctl = E1000_READ_REG(hw, TCTL);
1817                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1818                         if (reg_tctl & E1000_TCTL_MULR)
1819                                 reg_tarc1 &= ~(1 << 28);
1820                         else
1821                                 reg_tarc1 |= (1 << 28);
1822
1823                         /* workaround TX hang with TSO=on */
1824                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1825
1826                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1827                         break;
1828                 default:
1829                         break;
1830                 }
1831
1832                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1833         }
1834 }
1835
1836 /******************************************************************************
1837  * Performs basic configuration of the adapter.
1838  *
1839  * hw - Struct containing variables accessed by shared code
1840  *
1841  * Assumes that the controller has previously been reset and is in a
1842  * post-reset uninitialized state. Initializes the receive address registers,
1843  * multicast table, and VLAN filter table. Calls routines to setup link
1844  * configuration and flow control settings. Clears all on-chip counters. Leaves
1845  * the transmit and receive units disabled and uninitialized.
1846  *****************************************************************************/
1847 static int
1848 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1849 {
1850         uint32_t ctrl;
1851         uint32_t i;
1852         int32_t ret_val;
1853         uint16_t pcix_cmd_word;
1854         uint16_t pcix_stat_hi_word;
1855         uint16_t cmd_mmrbc;
1856         uint16_t stat_mmrbc;
1857         uint32_t mta_size;
1858         uint32_t reg_data;
1859         uint32_t ctrl_ext;
1860         DEBUGFUNC();
1861         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1862         if ((hw->mac_type == e1000_ich8lan) &&
1863                 ((hw->revision_id < 3) ||
1864                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1865                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1866                         reg_data = E1000_READ_REG(hw, STATUS);
1867                         reg_data &= ~0x80000000;
1868                         E1000_WRITE_REG(hw, STATUS, reg_data);
1869         }
1870         /* Do not need initialize Identification LED */
1871
1872         /* Set the media type and TBI compatibility */
1873         e1000_set_media_type(hw);
1874
1875         /* Must be called after e1000_set_media_type
1876          * because media_type is used */
1877         e1000_initialize_hardware_bits(hw);
1878
1879         /* Disabling VLAN filtering. */
1880         DEBUGOUT("Initializing the IEEE VLAN\n");
1881         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1882         if (hw->mac_type != e1000_ich8lan) {
1883                 if (hw->mac_type < e1000_82545_rev_3)
1884                         E1000_WRITE_REG(hw, VET, 0);
1885                 e1000_clear_vfta(hw);
1886         }
1887
1888         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1889         if (hw->mac_type == e1000_82542_rev2_0) {
1890                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1891 #ifdef CONFIG_DM_ETH
1892                 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1893                                       hw->
1894                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1895 #else
1896                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1897                                       hw->
1898                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1899 #endif
1900                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1901                 E1000_WRITE_FLUSH(hw);
1902                 mdelay(5);
1903         }
1904
1905         /* Setup the receive address. This involves initializing all of the Receive
1906          * Address Registers (RARs 0 - 15).
1907          */
1908         e1000_init_rx_addrs(hw, enetaddr);
1909
1910         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1911         if (hw->mac_type == e1000_82542_rev2_0) {
1912                 E1000_WRITE_REG(hw, RCTL, 0);
1913                 E1000_WRITE_FLUSH(hw);
1914                 mdelay(1);
1915 #ifdef CONFIG_DM_ETH
1916                 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1917 #else
1918                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1919 #endif
1920         }
1921
1922         /* Zero out the Multicast HASH table */
1923         DEBUGOUT("Zeroing the MTA\n");
1924         mta_size = E1000_MC_TBL_SIZE;
1925         if (hw->mac_type == e1000_ich8lan)
1926                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1927         for (i = 0; i < mta_size; i++) {
1928                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1929                 /* use write flush to prevent Memory Write Block (MWB) from
1930                  * occuring when accessing our register space */
1931                 E1000_WRITE_FLUSH(hw);
1932         }
1933
1934         switch (hw->mac_type) {
1935         case e1000_82545_rev_3:
1936         case e1000_82546_rev_3:
1937         case e1000_igb:
1938                 break;
1939         default:
1940         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1941         if (hw->bus_type == e1000_bus_type_pcix) {
1942 #ifdef CONFIG_DM_ETH
1943                 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1944                                      &pcix_cmd_word);
1945                 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1946                                      &pcix_stat_hi_word);
1947 #else
1948                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1949                                      &pcix_cmd_word);
1950                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1951                                      &pcix_stat_hi_word);
1952 #endif
1953                 cmd_mmrbc =
1954                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1955                     PCIX_COMMAND_MMRBC_SHIFT;
1956                 stat_mmrbc =
1957                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1958                     PCIX_STATUS_HI_MMRBC_SHIFT;
1959                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1960                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1961                 if (cmd_mmrbc > stat_mmrbc) {
1962                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1963                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1964 #ifdef CONFIG_DM_ETH
1965                         dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1966                                               pcix_cmd_word);
1967 #else
1968                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1969                                               pcix_cmd_word);
1970 #endif
1971                 }
1972         }
1973                 break;
1974         }
1975
1976         /* More time needed for PHY to initialize */
1977         if (hw->mac_type == e1000_ich8lan)
1978                 mdelay(15);
1979         if (hw->mac_type == e1000_igb)
1980                 mdelay(15);
1981
1982         /* Call a subroutine to configure the link and setup flow control. */
1983         ret_val = e1000_setup_link(hw);
1984
1985         /* Set the transmit descriptor write-back policy */
1986         if (hw->mac_type > e1000_82544) {
1987                 ctrl = E1000_READ_REG(hw, TXDCTL);
1988                 ctrl =
1989                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1990                     E1000_TXDCTL_FULL_TX_DESC_WB;
1991                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1992         }
1993
1994         /* Set the receive descriptor write back policy */
1995         if (hw->mac_type >= e1000_82571) {
1996                 ctrl = E1000_READ_REG(hw, RXDCTL);
1997                 ctrl =
1998                     (ctrl & ~E1000_RXDCTL_WTHRESH) |
1999                     E1000_RXDCTL_FULL_RX_DESC_WB;
2000                 E1000_WRITE_REG(hw, RXDCTL, ctrl);
2001         }
2002
2003         switch (hw->mac_type) {
2004         default:
2005                 break;
2006         case e1000_80003es2lan:
2007                 /* Enable retransmit on late collisions */
2008                 reg_data = E1000_READ_REG(hw, TCTL);
2009                 reg_data |= E1000_TCTL_RTLC;
2010                 E1000_WRITE_REG(hw, TCTL, reg_data);
2011
2012                 /* Configure Gigabit Carry Extend Padding */
2013                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
2014                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
2015                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
2016                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
2017
2018                 /* Configure Transmit Inter-Packet Gap */
2019                 reg_data = E1000_READ_REG(hw, TIPG);
2020                 reg_data &= ~E1000_TIPG_IPGT_MASK;
2021                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2022                 E1000_WRITE_REG(hw, TIPG, reg_data);
2023
2024                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
2025                 reg_data &= ~0x00100000;
2026                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
2027                 /* Fall through */
2028         case e1000_82571:
2029         case e1000_82572:
2030         case e1000_ich8lan:
2031                 ctrl = E1000_READ_REG(hw, TXDCTL1);
2032                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
2033                         | E1000_TXDCTL_FULL_TX_DESC_WB;
2034                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
2035                 break;
2036         case e1000_82573:
2037         case e1000_82574:
2038                 reg_data = E1000_READ_REG(hw, GCR);
2039                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2040                 E1000_WRITE_REG(hw, GCR, reg_data);
2041         case e1000_igb:
2042                 break;
2043         }
2044
2045         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
2046                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
2047                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2048                 /* Relaxed ordering must be disabled to avoid a parity
2049                  * error crash in a PCI slot. */
2050                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2051                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2052         }
2053
2054         return ret_val;
2055 }
2056
2057 /******************************************************************************
2058  * Configures flow control and link settings.
2059  *
2060  * hw - Struct containing variables accessed by shared code
2061  *
2062  * Determines which flow control settings to use. Calls the apropriate media-
2063  * specific link configuration function. Configures the flow control settings.
2064  * Assuming the adapter has a valid link partner, a valid link should be
2065  * established. Assumes the hardware has previously been reset and the
2066  * transmitter and receiver are not enabled.
2067  *****************************************************************************/
2068 static int
2069 e1000_setup_link(struct e1000_hw *hw)
2070 {
2071         int32_t ret_val;
2072 #ifndef CONFIG_E1000_NO_NVM
2073         uint32_t ctrl_ext;
2074         uint16_t eeprom_data;
2075 #endif
2076
2077         DEBUGFUNC();
2078
2079         /* In the case of the phy reset being blocked, we already have a link.
2080          * We do not have to set it up again. */
2081         if (e1000_check_phy_reset_block(hw))
2082                 return E1000_SUCCESS;
2083
2084 #ifndef CONFIG_E1000_NO_NVM
2085         /* Read and store word 0x0F of the EEPROM. This word contains bits
2086          * that determine the hardware's default PAUSE (flow control) mode,
2087          * a bit that determines whether the HW defaults to enabling or
2088          * disabling auto-negotiation, and the direction of the
2089          * SW defined pins. If there is no SW over-ride of the flow
2090          * control setting, then the variable hw->fc will
2091          * be initialized based on a value in the EEPROM.
2092          */
2093         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2094                                 &eeprom_data) < 0) {
2095                 DEBUGOUT("EEPROM Read Error\n");
2096                 return -E1000_ERR_EEPROM;
2097         }
2098 #endif
2099         if (hw->fc == e1000_fc_default) {
2100                 switch (hw->mac_type) {
2101                 case e1000_ich8lan:
2102                 case e1000_82573:
2103                 case e1000_82574:
2104                 case e1000_igb:
2105                         hw->fc = e1000_fc_full;
2106                         break;
2107                 default:
2108 #ifndef CONFIG_E1000_NO_NVM
2109                         ret_val = e1000_read_eeprom(hw,
2110                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2111                         if (ret_val) {
2112                                 DEBUGOUT("EEPROM Read Error\n");
2113                                 return -E1000_ERR_EEPROM;
2114                         }
2115                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2116                                 hw->fc = e1000_fc_none;
2117                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2118                                     EEPROM_WORD0F_ASM_DIR)
2119                                 hw->fc = e1000_fc_tx_pause;
2120                         else
2121 #endif
2122                                 hw->fc = e1000_fc_full;
2123                         break;
2124                 }
2125         }
2126
2127         /* We want to save off the original Flow Control configuration just
2128          * in case we get disconnected and then reconnected into a different
2129          * hub or switch with different Flow Control capabilities.
2130          */
2131         if (hw->mac_type == e1000_82542_rev2_0)
2132                 hw->fc &= (~e1000_fc_tx_pause);
2133
2134         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2135                 hw->fc &= (~e1000_fc_rx_pause);
2136
2137         hw->original_fc = hw->fc;
2138
2139         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2140
2141 #ifndef CONFIG_E1000_NO_NVM
2142         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
2143          * polarity value for the SW controlled pins, and setup the
2144          * Extended Device Control reg with that info.
2145          * This is needed because one of the SW controlled pins is used for
2146          * signal detection.  So this should be done before e1000_setup_pcs_link()
2147          * or e1000_phy_setup() is called.
2148          */
2149         if (hw->mac_type == e1000_82543) {
2150                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2151                             SWDPIO__EXT_SHIFT);
2152                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2153         }
2154 #endif
2155
2156         /* Call the necessary subroutine to configure the link. */
2157         ret_val = (hw->media_type == e1000_media_type_fiber) ?
2158             e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
2159         if (ret_val < 0) {
2160                 return ret_val;
2161         }
2162
2163         /* Initialize the flow control address, type, and PAUSE timer
2164          * registers to their default values.  This is done even if flow
2165          * control is disabled, because it does not hurt anything to
2166          * initialize these registers.
2167          */
2168         DEBUGOUT("Initializing the Flow Control address, type"
2169                         "and timer regs\n");
2170
2171         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
2172         if (hw->mac_type != e1000_ich8lan) {
2173                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2174                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2175                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2176         }
2177
2178         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2179
2180         /* Set the flow control receive threshold registers.  Normally,
2181          * these registers will be set to a default threshold that may be
2182          * adjusted later by the driver's runtime code.  However, if the
2183          * ability to transmit pause frames in not enabled, then these
2184          * registers will be set to 0.
2185          */
2186         if (!(hw->fc & e1000_fc_tx_pause)) {
2187                 E1000_WRITE_REG(hw, FCRTL, 0);
2188                 E1000_WRITE_REG(hw, FCRTH, 0);
2189         } else {
2190                 /* We need to set up the Receive Threshold high and low water marks
2191                  * as well as (optionally) enabling the transmission of XON frames.
2192                  */
2193                 if (hw->fc_send_xon) {
2194                         E1000_WRITE_REG(hw, FCRTL,
2195                                         (hw->fc_low_water | E1000_FCRTL_XONE));
2196                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2197                 } else {
2198                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2199                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2200                 }
2201         }
2202         return ret_val;
2203 }
2204
2205 /******************************************************************************
2206  * Sets up link for a fiber based adapter
2207  *
2208  * hw - Struct containing variables accessed by shared code
2209  *
2210  * Manipulates Physical Coding Sublayer functions in order to configure
2211  * link. Assumes the hardware has been previously reset and the transmitter
2212  * and receiver are not enabled.
2213  *****************************************************************************/
2214 static int
2215 e1000_setup_fiber_link(struct e1000_hw *hw)
2216 {
2217         uint32_t ctrl;
2218         uint32_t status;
2219         uint32_t txcw = 0;
2220         uint32_t i;
2221         uint32_t signal;
2222         int32_t ret_val;
2223
2224         DEBUGFUNC();
2225         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2226          * set when the optics detect a signal. On older adapters, it will be
2227          * cleared when there is a signal
2228          */
2229         ctrl = E1000_READ_REG(hw, CTRL);
2230         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2231                 signal = E1000_CTRL_SWDPIN1;
2232         else
2233                 signal = 0;
2234
2235         printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2236                ctrl);
2237         /* Take the link out of reset */
2238         ctrl &= ~(E1000_CTRL_LRST);
2239
2240         e1000_config_collision_dist(hw);
2241
2242         /* Check for a software override of the flow control settings, and setup
2243          * the device accordingly.  If auto-negotiation is enabled, then software
2244          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2245          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2246          * auto-negotiation is disabled, then software will have to manually
2247          * configure the two flow control enable bits in the CTRL register.
2248          *
2249          * The possible values of the "fc" parameter are:
2250          *      0:  Flow control is completely disabled
2251          *      1:  Rx flow control is enabled (we can receive pause frames, but
2252          *          not send pause frames).
2253          *      2:  Tx flow control is enabled (we can send pause frames but we do
2254          *          not support receiving pause frames).
2255          *      3:  Both Rx and TX flow control (symmetric) are enabled.
2256          */
2257         switch (hw->fc) {
2258         case e1000_fc_none:
2259                 /* Flow control is completely disabled by a software over-ride. */
2260                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2261                 break;
2262         case e1000_fc_rx_pause:
2263                 /* RX Flow control is enabled and TX Flow control is disabled by a
2264                  * software over-ride. Since there really isn't a way to advertise
2265                  * that we are capable of RX Pause ONLY, we will advertise that we
2266                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2267                  *  disable the adapter's ability to send PAUSE frames.
2268                  */
2269                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2270                 break;
2271         case e1000_fc_tx_pause:
2272                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2273                  * software over-ride.
2274                  */
2275                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2276                 break;
2277         case e1000_fc_full:
2278                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2279                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2280                 break;
2281         default:
2282                 DEBUGOUT("Flow control param set incorrectly\n");
2283                 return -E1000_ERR_CONFIG;
2284                 break;
2285         }
2286
2287         /* Since auto-negotiation is enabled, take the link out of reset (the link
2288          * will be in reset, because we previously reset the chip). This will
2289          * restart auto-negotiation.  If auto-neogtiation is successful then the
2290          * link-up status bit will be set and the flow control enable bits (RFCE
2291          * and TFCE) will be set according to their negotiated value.
2292          */
2293         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2294
2295         E1000_WRITE_REG(hw, TXCW, txcw);
2296         E1000_WRITE_REG(hw, CTRL, ctrl);
2297         E1000_WRITE_FLUSH(hw);
2298
2299         hw->txcw = txcw;
2300         mdelay(1);
2301
2302         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2303          * indication in the Device Status Register.  Time-out if a link isn't
2304          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2305          * less than 500 milliseconds even if the other end is doing it in SW).
2306          */
2307         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2308                 DEBUGOUT("Looking for Link\n");
2309                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2310                         mdelay(10);
2311                         status = E1000_READ_REG(hw, STATUS);
2312                         if (status & E1000_STATUS_LU)
2313                                 break;
2314                 }
2315                 if (i == (LINK_UP_TIMEOUT / 10)) {
2316                         /* AutoNeg failed to achieve a link, so we'll call
2317                          * e1000_check_for_link. This routine will force the link up if we
2318                          * detect a signal. This will allow us to communicate with
2319                          * non-autonegotiating link partners.
2320                          */
2321                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2322                         hw->autoneg_failed = 1;
2323                         ret_val = e1000_check_for_link(hw);
2324                         if (ret_val < 0) {
2325                                 DEBUGOUT("Error while checking for link\n");
2326                                 return ret_val;
2327                         }
2328                         hw->autoneg_failed = 0;
2329                 } else {
2330                         hw->autoneg_failed = 0;
2331                         DEBUGOUT("Valid Link Found\n");
2332                 }
2333         } else {
2334                 DEBUGOUT("No Signal Detected\n");
2335                 return -E1000_ERR_NOLINK;
2336         }
2337         return 0;
2338 }
2339
2340 /******************************************************************************
2341 * Make sure we have a valid PHY and change PHY mode before link setup.
2342 *
2343 * hw - Struct containing variables accessed by shared code
2344 ******************************************************************************/
2345 static int32_t
2346 e1000_copper_link_preconfig(struct e1000_hw *hw)
2347 {
2348         uint32_t ctrl;
2349         int32_t ret_val;
2350         uint16_t phy_data;
2351
2352         DEBUGFUNC();
2353
2354         ctrl = E1000_READ_REG(hw, CTRL);
2355         /* With 82543, we need to force speed and duplex on the MAC equal to what
2356          * the PHY speed and duplex configuration is. In addition, we need to
2357          * perform a hardware reset on the PHY to take it out of reset.
2358          */
2359         if (hw->mac_type > e1000_82543) {
2360                 ctrl |= E1000_CTRL_SLU;
2361                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2362                 E1000_WRITE_REG(hw, CTRL, ctrl);
2363         } else {
2364                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2365                                 | E1000_CTRL_SLU);
2366                 E1000_WRITE_REG(hw, CTRL, ctrl);
2367                 ret_val = e1000_phy_hw_reset(hw);
2368                 if (ret_val)
2369                         return ret_val;
2370         }
2371
2372         /* Make sure we have a valid PHY */
2373         ret_val = e1000_detect_gig_phy(hw);
2374         if (ret_val) {
2375                 DEBUGOUT("Error, did not detect valid phy.\n");
2376                 return ret_val;
2377         }
2378         DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2379
2380         /* Set PHY to class A mode (if necessary) */
2381         ret_val = e1000_set_phy_mode(hw);
2382         if (ret_val)
2383                 return ret_val;
2384         if ((hw->mac_type == e1000_82545_rev_3) ||
2385                 (hw->mac_type == e1000_82546_rev_3)) {
2386                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2387                                 &phy_data);
2388                 phy_data |= 0x00000008;
2389                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2390                                 phy_data);
2391         }
2392
2393         if (hw->mac_type <= e1000_82543 ||
2394                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2395                 hw->mac_type == e1000_82541_rev_2
2396                 || hw->mac_type == e1000_82547_rev_2)
2397                         hw->phy_reset_disable = false;
2398
2399         return E1000_SUCCESS;
2400 }
2401
2402 /*****************************************************************************
2403  *
2404  * This function sets the lplu state according to the active flag.  When
2405  * activating lplu this function also disables smart speed and vise versa.
2406  * lplu will not be activated unless the device autonegotiation advertisment
2407  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2408  * hw: Struct containing variables accessed by shared code
2409  * active - true to enable lplu false to disable lplu.
2410  *
2411  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2412  *            E1000_SUCCESS at any other case.
2413  *
2414  ****************************************************************************/
2415
2416 static int32_t
2417 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2418 {
2419         uint32_t phy_ctrl = 0;
2420         int32_t ret_val;
2421         uint16_t phy_data;
2422         DEBUGFUNC();
2423
2424         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2425             && hw->phy_type != e1000_phy_igp_3)
2426                 return E1000_SUCCESS;
2427
2428         /* During driver activity LPLU should not be used or it will attain link
2429          * from the lowest speeds starting from 10Mbps. The capability is used
2430          * for Dx transitions and states */
2431         if (hw->mac_type == e1000_82541_rev_2
2432                         || hw->mac_type == e1000_82547_rev_2) {
2433                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2434                                 &phy_data);
2435                 if (ret_val)
2436                         return ret_val;
2437         } else if (hw->mac_type == e1000_ich8lan) {
2438                 /* MAC writes into PHY register based on the state transition
2439                  * and start auto-negotiation. SW driver can overwrite the
2440                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2441                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2442         } else {
2443                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2444                                 &phy_data);
2445                 if (ret_val)
2446                         return ret_val;
2447         }
2448
2449         if (!active) {
2450                 if (hw->mac_type == e1000_82541_rev_2 ||
2451                         hw->mac_type == e1000_82547_rev_2) {
2452                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2453                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2454                                         phy_data);
2455                         if (ret_val)
2456                                 return ret_val;
2457                 } else {
2458                         if (hw->mac_type == e1000_ich8lan) {
2459                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2460                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2461                         } else {
2462                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2463                                 ret_val = e1000_write_phy_reg(hw,
2464                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2465                                 if (ret_val)
2466                                         return ret_val;
2467                         }
2468                 }
2469
2470         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2471          * Dx states where the power conservation is most important.  During
2472          * driver activity we should enable SmartSpeed, so performance is
2473          * maintained. */
2474                 if (hw->smart_speed == e1000_smart_speed_on) {
2475                         ret_val = e1000_read_phy_reg(hw,
2476                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2477                         if (ret_val)
2478                                 return ret_val;
2479
2480                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2481                         ret_val = e1000_write_phy_reg(hw,
2482                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2483                         if (ret_val)
2484                                 return ret_val;
2485                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2486                         ret_val = e1000_read_phy_reg(hw,
2487                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2488                         if (ret_val)
2489                                 return ret_val;
2490
2491                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2492                         ret_val = e1000_write_phy_reg(hw,
2493                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2494                         if (ret_val)
2495                                 return ret_val;
2496                 }
2497
2498         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2499                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2500                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2501
2502                 if (hw->mac_type == e1000_82541_rev_2 ||
2503                     hw->mac_type == e1000_82547_rev_2) {
2504                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2505                         ret_val = e1000_write_phy_reg(hw,
2506                                         IGP01E1000_GMII_FIFO, phy_data);
2507                         if (ret_val)
2508                                 return ret_val;
2509                 } else {
2510                         if (hw->mac_type == e1000_ich8lan) {
2511                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2512                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2513                         } else {
2514                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2515                                 ret_val = e1000_write_phy_reg(hw,
2516                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2517                                 if (ret_val)
2518                                         return ret_val;
2519                         }
2520                 }
2521
2522                 /* When LPLU is enabled we should disable SmartSpeed */
2523                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2524                                 &phy_data);
2525                 if (ret_val)
2526                         return ret_val;
2527
2528                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2529                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2530                                 phy_data);
2531                 if (ret_val)
2532                         return ret_val;
2533         }
2534         return E1000_SUCCESS;
2535 }
2536
2537 /*****************************************************************************
2538  *
2539  * This function sets the lplu d0 state according to the active flag.  When
2540  * activating lplu this function also disables smart speed and vise versa.
2541  * lplu will not be activated unless the device autonegotiation advertisment
2542  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2543  * hw: Struct containing variables accessed by shared code
2544  * active - true to enable lplu false to disable lplu.
2545  *
2546  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2547  *            E1000_SUCCESS at any other case.
2548  *
2549  ****************************************************************************/
2550
2551 static int32_t
2552 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2553 {
2554         uint32_t phy_ctrl = 0;
2555         int32_t ret_val;
2556         uint16_t phy_data;
2557         DEBUGFUNC();
2558
2559         if (hw->mac_type <= e1000_82547_rev_2)
2560                 return E1000_SUCCESS;
2561
2562         if (hw->mac_type == e1000_ich8lan) {
2563                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2564         } else if (hw->mac_type == e1000_igb) {
2565                 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2566         } else {
2567                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2568                                 &phy_data);
2569                 if (ret_val)
2570                         return ret_val;
2571         }
2572
2573         if (!active) {
2574                 if (hw->mac_type == e1000_ich8lan) {
2575                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2576                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2577                 } else if (hw->mac_type == e1000_igb) {
2578                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2579                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2580                 } else {
2581                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2582                         ret_val = e1000_write_phy_reg(hw,
2583                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2584                         if (ret_val)
2585                                 return ret_val;
2586                 }
2587
2588                 if (hw->mac_type == e1000_igb)
2589                         return E1000_SUCCESS;
2590
2591         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2592          * Dx states where the power conservation is most important.  During
2593          * driver activity we should enable SmartSpeed, so performance is
2594          * maintained. */
2595                 if (hw->smart_speed == e1000_smart_speed_on) {
2596                         ret_val = e1000_read_phy_reg(hw,
2597                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2598                         if (ret_val)
2599                                 return ret_val;
2600
2601                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2602                         ret_val = e1000_write_phy_reg(hw,
2603                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2604                         if (ret_val)
2605                                 return ret_val;
2606                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2607                         ret_val = e1000_read_phy_reg(hw,
2608                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2609                         if (ret_val)
2610                                 return ret_val;
2611
2612                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2613                         ret_val = e1000_write_phy_reg(hw,
2614                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2615                         if (ret_val)
2616                                 return ret_val;
2617                 }
2618
2619
2620         } else {
2621
2622                 if (hw->mac_type == e1000_ich8lan) {
2623                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2624                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2625                 } else if (hw->mac_type == e1000_igb) {
2626                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2627                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2628                 } else {
2629                         phy_data |= IGP02E1000_PM_D0_LPLU;
2630                         ret_val = e1000_write_phy_reg(hw,
2631                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2632                         if (ret_val)
2633                                 return ret_val;
2634                 }
2635
2636                 if (hw->mac_type == e1000_igb)
2637                         return E1000_SUCCESS;
2638
2639                 /* When LPLU is enabled we should disable SmartSpeed */
2640                 ret_val = e1000_read_phy_reg(hw,
2641                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2642                 if (ret_val)
2643                         return ret_val;
2644
2645                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2646                 ret_val = e1000_write_phy_reg(hw,
2647                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2648                 if (ret_val)
2649                         return ret_val;
2650
2651         }
2652         return E1000_SUCCESS;
2653 }
2654
2655 /********************************************************************
2656 * Copper link setup for e1000_phy_igp series.
2657 *
2658 * hw - Struct containing variables accessed by shared code
2659 *********************************************************************/
2660 static int32_t
2661 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2662 {
2663         uint32_t led_ctrl;
2664         int32_t ret_val;
2665         uint16_t phy_data;
2666
2667         DEBUGFUNC();
2668
2669         if (hw->phy_reset_disable)
2670                 return E1000_SUCCESS;
2671
2672         ret_val = e1000_phy_reset(hw);
2673         if (ret_val) {
2674                 DEBUGOUT("Error Resetting the PHY\n");
2675                 return ret_val;
2676         }
2677
2678         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2679         mdelay(15);
2680         if (hw->mac_type != e1000_ich8lan) {
2681                 /* Configure activity LED after PHY reset */
2682                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2683                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2684                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2685                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2686         }
2687
2688         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2689         if (hw->phy_type == e1000_phy_igp) {
2690                 /* disable lplu d3 during driver init */
2691                 ret_val = e1000_set_d3_lplu_state(hw, false);
2692                 if (ret_val) {
2693                         DEBUGOUT("Error Disabling LPLU D3\n");
2694                         return ret_val;
2695                 }
2696         }
2697
2698         /* disable lplu d0 during driver init */
2699         ret_val = e1000_set_d0_lplu_state(hw, false);
2700         if (ret_val) {
2701                 DEBUGOUT("Error Disabling LPLU D0\n");
2702                 return ret_val;
2703         }
2704         /* Configure mdi-mdix settings */
2705         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2706         if (ret_val)
2707                 return ret_val;
2708
2709         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2710                 hw->dsp_config_state = e1000_dsp_config_disabled;
2711                 /* Force MDI for earlier revs of the IGP PHY */
2712                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2713                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2714                 hw->mdix = 1;
2715
2716         } else {
2717                 hw->dsp_config_state = e1000_dsp_config_enabled;
2718                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2719
2720                 switch (hw->mdix) {
2721                 case 1:
2722                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2723                         break;
2724                 case 2:
2725                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2726                         break;
2727                 case 0:
2728                 default:
2729                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2730                         break;
2731                 }
2732         }
2733         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2734         if (ret_val)
2735                 return ret_val;
2736
2737         /* set auto-master slave resolution settings */
2738         if (hw->autoneg) {
2739                 e1000_ms_type phy_ms_setting = hw->master_slave;
2740
2741                 if (hw->ffe_config_state == e1000_ffe_config_active)
2742                         hw->ffe_config_state = e1000_ffe_config_enabled;
2743
2744                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2745                         hw->dsp_config_state = e1000_dsp_config_enabled;
2746
2747                 /* when autonegotiation advertisment is only 1000Mbps then we
2748                   * should disable SmartSpeed and enable Auto MasterSlave
2749                   * resolution as hardware default. */
2750                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2751                         /* Disable SmartSpeed */
2752                         ret_val = e1000_read_phy_reg(hw,
2753                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2754                         if (ret_val)
2755                                 return ret_val;
2756                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2757                         ret_val = e1000_write_phy_reg(hw,
2758                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2759                         if (ret_val)
2760                                 return ret_val;
2761                         /* Set auto Master/Slave resolution process */
2762                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2763                                         &phy_data);
2764                         if (ret_val)
2765                                 return ret_val;
2766                         phy_data &= ~CR_1000T_MS_ENABLE;
2767                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2768                                         phy_data);
2769                         if (ret_val)
2770                                 return ret_val;
2771                 }
2772
2773                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2774                 if (ret_val)
2775                         return ret_val;
2776
2777                 /* load defaults for future use */
2778                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2779                                 ((phy_data & CR_1000T_MS_VALUE) ?
2780                                 e1000_ms_force_master :
2781                                 e1000_ms_force_slave) :
2782                                 e1000_ms_auto;
2783
2784                 switch (phy_ms_setting) {
2785                 case e1000_ms_force_master:
2786                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2787                         break;
2788                 case e1000_ms_force_slave:
2789                         phy_data |= CR_1000T_MS_ENABLE;
2790                         phy_data &= ~(CR_1000T_MS_VALUE);
2791                         break;
2792                 case e1000_ms_auto:
2793                         phy_data &= ~CR_1000T_MS_ENABLE;
2794                 default:
2795                         break;
2796                 }
2797                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2798                 if (ret_val)
2799                         return ret_val;
2800         }
2801
2802         return E1000_SUCCESS;
2803 }
2804
2805 /*****************************************************************************
2806  * This function checks the mode of the firmware.
2807  *
2808  * returns  - true when the mode is IAMT or false.
2809  ****************************************************************************/
2810 bool
2811 e1000_check_mng_mode(struct e1000_hw *hw)
2812 {
2813         uint32_t fwsm;
2814         DEBUGFUNC();
2815
2816         fwsm = E1000_READ_REG(hw, FWSM);
2817
2818         if (hw->mac_type == e1000_ich8lan) {
2819                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2820                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2821                         return true;
2822         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2823                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2824                         return true;
2825
2826         return false;
2827 }
2828
2829 static int32_t
2830 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2831 {
2832         uint16_t swfw = E1000_SWFW_PHY0_SM;
2833         uint32_t reg_val;
2834         DEBUGFUNC();
2835
2836         if (e1000_is_second_port(hw))
2837                 swfw = E1000_SWFW_PHY1_SM;
2838
2839         if (e1000_swfw_sync_acquire(hw, swfw))
2840                 return -E1000_ERR_SWFW_SYNC;
2841
2842         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2843                         & E1000_KUMCTRLSTA_OFFSET) | data;
2844         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2845         udelay(2);
2846
2847         return E1000_SUCCESS;
2848 }
2849
2850 static int32_t
2851 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2852 {
2853         uint16_t swfw = E1000_SWFW_PHY0_SM;
2854         uint32_t reg_val;
2855         DEBUGFUNC();
2856
2857         if (e1000_is_second_port(hw))
2858                 swfw = E1000_SWFW_PHY1_SM;
2859
2860         if (e1000_swfw_sync_acquire(hw, swfw)) {
2861                 debug("%s[%i]\n", __func__, __LINE__);
2862                 return -E1000_ERR_SWFW_SYNC;
2863         }
2864
2865         /* Write register address */
2866         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2867                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2868         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2869         udelay(2);
2870
2871         /* Read the data returned */
2872         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2873         *data = (uint16_t)reg_val;
2874
2875         return E1000_SUCCESS;
2876 }
2877
2878 /********************************************************************
2879 * Copper link setup for e1000_phy_gg82563 series.
2880 *
2881 * hw - Struct containing variables accessed by shared code
2882 *********************************************************************/
2883 static int32_t
2884 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2885 {
2886         int32_t ret_val;
2887         uint16_t phy_data;
2888         uint32_t reg_data;
2889
2890         DEBUGFUNC();
2891
2892         if (!hw->phy_reset_disable) {
2893                 /* Enable CRS on TX for half-duplex operation. */
2894                 ret_val = e1000_read_phy_reg(hw,
2895                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2896                 if (ret_val)
2897                         return ret_val;
2898
2899                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2900                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2901                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2902
2903                 ret_val = e1000_write_phy_reg(hw,
2904                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2905                 if (ret_val)
2906                         return ret_val;
2907
2908                 /* Options:
2909                  *   MDI/MDI-X = 0 (default)
2910                  *   0 - Auto for all speeds
2911                  *   1 - MDI mode
2912                  *   2 - MDI-X mode
2913                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2914                  */
2915                 ret_val = e1000_read_phy_reg(hw,
2916                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2917                 if (ret_val)
2918                         return ret_val;
2919
2920                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2921
2922                 switch (hw->mdix) {
2923                 case 1:
2924                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2925                         break;
2926                 case 2:
2927                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2928                         break;
2929                 case 0:
2930                 default:
2931                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2932                         break;
2933                 }
2934
2935                 /* Options:
2936                  *   disable_polarity_correction = 0 (default)
2937                  *       Automatic Correction for Reversed Cable Polarity
2938                  *   0 - Disabled
2939                  *   1 - Enabled
2940                  */
2941                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2942                 ret_val = e1000_write_phy_reg(hw,
2943                                 GG82563_PHY_SPEC_CTRL, phy_data);
2944
2945                 if (ret_val)
2946                         return ret_val;
2947
2948                 /* SW Reset the PHY so all changes take effect */
2949                 ret_val = e1000_phy_reset(hw);
2950                 if (ret_val) {
2951                         DEBUGOUT("Error Resetting the PHY\n");
2952                         return ret_val;
2953                 }
2954         } /* phy_reset_disable */
2955
2956         if (hw->mac_type == e1000_80003es2lan) {
2957                 /* Bypass RX and TX FIFO's */
2958                 ret_val = e1000_write_kmrn_reg(hw,
2959                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2960                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2961                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2962                 if (ret_val)
2963                         return ret_val;
2964
2965                 ret_val = e1000_read_phy_reg(hw,
2966                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2967                 if (ret_val)
2968                         return ret_val;
2969
2970                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2971                 ret_val = e1000_write_phy_reg(hw,
2972                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2973
2974                 if (ret_val)
2975                         return ret_val;
2976
2977                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2978                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2979                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2980
2981                 ret_val = e1000_read_phy_reg(hw,
2982                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2983                 if (ret_val)
2984                         return ret_val;
2985
2986         /* Do not init these registers when the HW is in IAMT mode, since the
2987          * firmware will have already initialized them.  We only initialize
2988          * them if the HW is not in IAMT mode.
2989          */
2990                 if (e1000_check_mng_mode(hw) == false) {
2991                         /* Enable Electrical Idle on the PHY */
2992                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2993                         ret_val = e1000_write_phy_reg(hw,
2994                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2995                         if (ret_val)
2996                                 return ret_val;
2997
2998                         ret_val = e1000_read_phy_reg(hw,
2999                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
3000                         if (ret_val)
3001                                 return ret_val;
3002
3003                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3004                         ret_val = e1000_write_phy_reg(hw,
3005                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
3006
3007                         if (ret_val)
3008                                 return ret_val;
3009                 }
3010
3011                 /* Workaround: Disable padding in Kumeran interface in the MAC
3012                  * and in the PHY to avoid CRC errors.
3013                  */
3014                 ret_val = e1000_read_phy_reg(hw,
3015                                 GG82563_PHY_INBAND_CTRL, &phy_data);
3016                 if (ret_val)
3017                         return ret_val;
3018                 phy_data |= GG82563_ICR_DIS_PADDING;
3019                 ret_val = e1000_write_phy_reg(hw,
3020                                 GG82563_PHY_INBAND_CTRL, phy_data);
3021                 if (ret_val)
3022                         return ret_val;
3023         }
3024         return E1000_SUCCESS;
3025 }
3026
3027 /********************************************************************
3028 * Copper link setup for e1000_phy_m88 series.
3029 *
3030 * hw - Struct containing variables accessed by shared code
3031 *********************************************************************/
3032 static int32_t
3033 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
3034 {
3035         int32_t ret_val;
3036         uint16_t phy_data;
3037
3038         DEBUGFUNC();
3039
3040         if (hw->phy_reset_disable)
3041                 return E1000_SUCCESS;
3042
3043         /* Enable CRS on TX. This must be set for half-duplex operation. */
3044         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3045         if (ret_val)
3046                 return ret_val;
3047
3048         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3049
3050         /* Options:
3051          *   MDI/MDI-X = 0 (default)
3052          *   0 - Auto for all speeds
3053          *   1 - MDI mode
3054          *   2 - MDI-X mode
3055          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3056          */
3057         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3058
3059         switch (hw->mdix) {
3060         case 1:
3061                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3062                 break;
3063         case 2:
3064                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3065                 break;
3066         case 3:
3067                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3068                 break;
3069         case 0:
3070         default:
3071                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3072                 break;
3073         }
3074
3075         /* Options:
3076          *   disable_polarity_correction = 0 (default)
3077          *       Automatic Correction for Reversed Cable Polarity
3078          *   0 - Disabled
3079          *   1 - Enabled
3080          */
3081         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
3082         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3083         if (ret_val)
3084                 return ret_val;
3085
3086         if (hw->phy_revision < M88E1011_I_REV_4) {
3087                 /* Force TX_CLK in the Extended PHY Specific Control Register
3088                  * to 25MHz clock.
3089                  */
3090                 ret_val = e1000_read_phy_reg(hw,
3091                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3092                 if (ret_val)
3093                         return ret_val;
3094
3095                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3096
3097                 if ((hw->phy_revision == E1000_REVISION_2) &&
3098                         (hw->phy_id == M88E1111_I_PHY_ID)) {
3099                         /* Vidalia Phy, set the downshift counter to 5x */
3100                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3101                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3102                         ret_val = e1000_write_phy_reg(hw,
3103                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3104                         if (ret_val)
3105                                 return ret_val;
3106                 } else {
3107                         /* Configure Master and Slave downshift values */
3108                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3109                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3110                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3111                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3112                         ret_val = e1000_write_phy_reg(hw,
3113                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3114                         if (ret_val)
3115                                 return ret_val;
3116                 }
3117         }
3118
3119         /* SW Reset the PHY so all changes take effect */
3120         ret_val = e1000_phy_reset(hw);
3121         if (ret_val) {
3122                 DEBUGOUT("Error Resetting the PHY\n");
3123                 return ret_val;
3124         }
3125
3126         return E1000_SUCCESS;
3127 }
3128
3129 /********************************************************************
3130 * Setup auto-negotiation and flow control advertisements,
3131 * and then perform auto-negotiation.
3132 *
3133 * hw - Struct containing variables accessed by shared code
3134 *********************************************************************/
3135 static int32_t
3136 e1000_copper_link_autoneg(struct e1000_hw *hw)
3137 {
3138         int32_t ret_val;
3139         uint16_t phy_data;
3140
3141         DEBUGFUNC();
3142
3143         /* Perform some bounds checking on the hw->autoneg_advertised
3144          * parameter.  If this variable is zero, then set it to the default.
3145          */
3146         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3147
3148         /* If autoneg_advertised is zero, we assume it was not defaulted
3149          * by the calling code so we set to advertise full capability.
3150          */
3151         if (hw->autoneg_advertised == 0)
3152                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3153
3154         /* IFE phy only supports 10/100 */
3155         if (hw->phy_type == e1000_phy_ife)
3156                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3157
3158         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3159         ret_val = e1000_phy_setup_autoneg(hw);
3160         if (ret_val) {
3161                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3162                 return ret_val;
3163         }
3164         DEBUGOUT("Restarting Auto-Neg\n");
3165
3166         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
3167          * the Auto Neg Restart bit in the PHY control register.
3168          */
3169         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3170         if (ret_val)
3171                 return ret_val;
3172
3173         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3174         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3175         if (ret_val)
3176                 return ret_val;
3177
3178         /* Does the user want to wait for Auto-Neg to complete here, or
3179          * check at a later time (for example, callback routine).
3180          */
3181         /* If we do not wait for autonegtation to complete I
3182          * do not see a valid link status.
3183          * wait_autoneg_complete = 1 .
3184          */
3185         if (hw->wait_autoneg_complete) {
3186                 ret_val = e1000_wait_autoneg(hw);
3187                 if (ret_val) {
3188                         DEBUGOUT("Error while waiting for autoneg"
3189                                         "to complete\n");
3190                         return ret_val;
3191                 }
3192         }
3193
3194         hw->get_link_status = true;
3195
3196         return E1000_SUCCESS;
3197 }
3198
3199 /******************************************************************************
3200 * Config the MAC and the PHY after link is up.
3201 *   1) Set up the MAC to the current PHY speed/duplex
3202 *      if we are on 82543.  If we
3203 *      are on newer silicon, we only need to configure
3204 *      collision distance in the Transmit Control Register.
3205 *   2) Set up flow control on the MAC to that established with
3206 *      the link partner.
3207 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3208 *
3209 * hw - Struct containing variables accessed by shared code
3210 ******************************************************************************/
3211 static int32_t
3212 e1000_copper_link_postconfig(struct e1000_hw *hw)
3213 {
3214         int32_t ret_val;
3215         DEBUGFUNC();
3216
3217         if (hw->mac_type >= e1000_82544) {
3218                 e1000_config_collision_dist(hw);
3219         } else {
3220                 ret_val = e1000_config_mac_to_phy(hw);
3221                 if (ret_val) {
3222                         DEBUGOUT("Error configuring MAC to PHY settings\n");
3223                         return ret_val;
3224                 }
3225         }
3226         ret_val = e1000_config_fc_after_link_up(hw);
3227         if (ret_val) {
3228                 DEBUGOUT("Error Configuring Flow Control\n");
3229                 return ret_val;
3230         }
3231         return E1000_SUCCESS;
3232 }
3233
3234 /******************************************************************************
3235 * Detects which PHY is present and setup the speed and duplex
3236 *
3237 * hw - Struct containing variables accessed by shared code
3238 ******************************************************************************/
3239 static int
3240 e1000_setup_copper_link(struct e1000_hw *hw)
3241 {
3242         int32_t ret_val;
3243         uint16_t i;
3244         uint16_t phy_data;
3245         uint16_t reg_data;
3246
3247         DEBUGFUNC();
3248
3249         switch (hw->mac_type) {
3250         case e1000_80003es2lan:
3251         case e1000_ich8lan:
3252                 /* Set the mac to wait the maximum time between each
3253                  * iteration and increase the max iterations when
3254                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3255                 ret_val = e1000_write_kmrn_reg(hw,
3256                                 GG82563_REG(0x34, 4), 0xFFFF);
3257                 if (ret_val)
3258                         return ret_val;
3259                 ret_val = e1000_read_kmrn_reg(hw,
3260                                 GG82563_REG(0x34, 9), &reg_data);
3261                 if (ret_val)
3262                         return ret_val;
3263                 reg_data |= 0x3F;
3264                 ret_val = e1000_write_kmrn_reg(hw,
3265                                 GG82563_REG(0x34, 9), reg_data);
3266                 if (ret_val)
3267                         return ret_val;
3268         default:
3269                 break;
3270         }
3271
3272         /* Check if it is a valid PHY and set PHY mode if necessary. */
3273         ret_val = e1000_copper_link_preconfig(hw);
3274         if (ret_val)
3275                 return ret_val;
3276         switch (hw->mac_type) {
3277         case e1000_80003es2lan:
3278                 /* Kumeran registers are written-only */
3279                 reg_data =
3280                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3281                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3282                 ret_val = e1000_write_kmrn_reg(hw,
3283                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3284                 if (ret_val)
3285                         return ret_val;
3286                 break;
3287         default:
3288                 break;
3289         }
3290
3291         if (hw->phy_type == e1000_phy_igp ||
3292                 hw->phy_type == e1000_phy_igp_3 ||
3293                 hw->phy_type == e1000_phy_igp_2) {
3294                 ret_val = e1000_copper_link_igp_setup(hw);
3295                 if (ret_val)
3296                         return ret_val;
3297         } else if (hw->phy_type == e1000_phy_m88 ||
3298                 hw->phy_type == e1000_phy_igb) {
3299                 ret_val = e1000_copper_link_mgp_setup(hw);
3300                 if (ret_val)
3301                         return ret_val;
3302         } else if (hw->phy_type == e1000_phy_gg82563) {
3303                 ret_val = e1000_copper_link_ggp_setup(hw);
3304                 if (ret_val)
3305                         return ret_val;
3306         }
3307
3308         /* always auto */
3309         /* Setup autoneg and flow control advertisement
3310           * and perform autonegotiation */
3311         ret_val = e1000_copper_link_autoneg(hw);
3312         if (ret_val)
3313                 return ret_val;
3314
3315         /* Check link status. Wait up to 100 microseconds for link to become
3316          * valid.
3317          */
3318         for (i = 0; i < 10; i++) {
3319                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3320                 if (ret_val)
3321                         return ret_val;
3322                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3323                 if (ret_val)
3324                         return ret_val;
3325
3326                 if (phy_data & MII_SR_LINK_STATUS) {
3327                         /* Config the MAC and PHY after link is up */
3328                         ret_val = e1000_copper_link_postconfig(hw);
3329                         if (ret_val)
3330                                 return ret_val;
3331
3332                         DEBUGOUT("Valid link established!!!\n");
3333                         return E1000_SUCCESS;
3334                 }
3335                 udelay(10);
3336         }
3337
3338         DEBUGOUT("Unable to establish link!!!\n");
3339         return E1000_SUCCESS;
3340 }
3341
3342 /******************************************************************************
3343 * Configures PHY autoneg and flow control advertisement settings
3344 *
3345 * hw - Struct containing variables accessed by shared code
3346 ******************************************************************************/
3347 int32_t
3348 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3349 {
3350         int32_t ret_val;
3351         uint16_t mii_autoneg_adv_reg;
3352         uint16_t mii_1000t_ctrl_reg;
3353
3354         DEBUGFUNC();
3355
3356         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3357         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3358         if (ret_val)
3359                 return ret_val;
3360
3361         if (hw->phy_type != e1000_phy_ife) {
3362                 /* Read the MII 1000Base-T Control Register (Address 9). */
3363                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3364                                 &mii_1000t_ctrl_reg);
3365                 if (ret_val)
3366                         return ret_val;
3367         } else
3368                 mii_1000t_ctrl_reg = 0;
3369
3370         /* Need to parse both autoneg_advertised and fc and set up
3371          * the appropriate PHY registers.  First we will parse for
3372          * autoneg_advertised software override.  Since we can advertise
3373          * a plethora of combinations, we need to check each bit
3374          * individually.
3375          */
3376
3377         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3378          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3379          * the  1000Base-T Control Register (Address 9).
3380          */
3381         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3382         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3383
3384         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3385
3386         /* Do we want to advertise 10 Mb Half Duplex? */
3387         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3388                 DEBUGOUT("Advertise 10mb Half duplex\n");
3389                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3390         }
3391
3392         /* Do we want to advertise 10 Mb Full Duplex? */
3393         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3394                 DEBUGOUT("Advertise 10mb Full duplex\n");
3395                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3396         }
3397
3398         /* Do we want to advertise 100 Mb Half Duplex? */
3399         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3400                 DEBUGOUT("Advertise 100mb Half duplex\n");
3401                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3402         }
3403
3404         /* Do we want to advertise 100 Mb Full Duplex? */
3405         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3406                 DEBUGOUT("Advertise 100mb Full duplex\n");
3407                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3408         }
3409
3410         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3411         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3412                 DEBUGOUT
3413                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3414         }
3415
3416         /* Do we want to advertise 1000 Mb Full Duplex? */
3417         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3418                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3419                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3420         }
3421
3422         /* Check for a software override of the flow control settings, and
3423          * setup the PHY advertisement registers accordingly.  If
3424          * auto-negotiation is enabled, then software will have to set the
3425          * "PAUSE" bits to the correct value in the Auto-Negotiation
3426          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3427          *
3428          * The possible values of the "fc" parameter are:
3429          *      0:  Flow control is completely disabled
3430          *      1:  Rx flow control is enabled (we can receive pause frames
3431          *          but not send pause frames).
3432          *      2:  Tx flow control is enabled (we can send pause frames
3433          *          but we do not support receiving pause frames).
3434          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3435          *  other:  No software override.  The flow control configuration
3436          *          in the EEPROM is used.
3437          */
3438         switch (hw->fc) {
3439         case e1000_fc_none:     /* 0 */
3440                 /* Flow control (RX & TX) is completely disabled by a
3441                  * software over-ride.
3442                  */
3443                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3444                 break;
3445         case e1000_fc_rx_pause: /* 1 */
3446                 /* RX Flow control is enabled, and TX Flow control is
3447                  * disabled, by a software over-ride.
3448                  */
3449                 /* Since there really isn't a way to advertise that we are
3450                  * capable of RX Pause ONLY, we will advertise that we
3451                  * support both symmetric and asymmetric RX PAUSE.  Later
3452                  * (in e1000_config_fc_after_link_up) we will disable the
3453                  *hw's ability to send PAUSE frames.
3454                  */
3455                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3456                 break;
3457         case e1000_fc_tx_pause: /* 2 */
3458                 /* TX Flow control is enabled, and RX Flow control is
3459                  * disabled, by a software over-ride.
3460                  */
3461                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3462                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3463                 break;
3464         case e1000_fc_full:     /* 3 */
3465                 /* Flow control (both RX and TX) is enabled by a software
3466                  * over-ride.
3467                  */
3468                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3469                 break;
3470         default:
3471                 DEBUGOUT("Flow control param set incorrectly\n");
3472                 return -E1000_ERR_CONFIG;
3473         }
3474
3475         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3476         if (ret_val)
3477                 return ret_val;
3478
3479         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3480
3481         if (hw->phy_type != e1000_phy_ife) {
3482                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3483                                 mii_1000t_ctrl_reg);
3484                 if (ret_val)
3485                         return ret_val;
3486         }
3487
3488         return E1000_SUCCESS;
3489 }
3490
3491 /******************************************************************************
3492 * Sets the collision distance in the Transmit Control register
3493 *
3494 * hw - Struct containing variables accessed by shared code
3495 *
3496 * Link should have been established previously. Reads the speed and duplex
3497 * information from the Device Status register.
3498 ******************************************************************************/
3499 static void
3500 e1000_config_collision_dist(struct e1000_hw *hw)
3501 {
3502         uint32_t tctl, coll_dist;
3503
3504         DEBUGFUNC();
3505
3506         if (hw->mac_type < e1000_82543)
3507                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3508         else
3509                 coll_dist = E1000_COLLISION_DISTANCE;
3510
3511         tctl = E1000_READ_REG(hw, TCTL);
3512
3513         tctl &= ~E1000_TCTL_COLD;
3514         tctl |= coll_dist << E1000_COLD_SHIFT;
3515
3516         E1000_WRITE_REG(hw, TCTL, tctl);
3517         E1000_WRITE_FLUSH(hw);
3518 }
3519
3520 /******************************************************************************
3521 * Sets MAC speed and duplex settings to reflect the those in the PHY
3522 *
3523 * hw - Struct containing variables accessed by shared code
3524 * mii_reg - data to write to the MII control register
3525 *
3526 * The contents of the PHY register containing the needed information need to
3527 * be passed in.
3528 ******************************************************************************/
3529 static int
3530 e1000_config_mac_to_phy(struct e1000_hw *hw)
3531 {
3532         uint32_t ctrl;
3533         uint16_t phy_data;
3534
3535         DEBUGFUNC();
3536
3537         /* Read the Device Control Register and set the bits to Force Speed
3538          * and Duplex.
3539          */
3540         ctrl = E1000_READ_REG(hw, CTRL);
3541         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3542         ctrl &= ~(E1000_CTRL_ILOS);
3543         ctrl |= (E1000_CTRL_SPD_SEL);
3544
3545         /* Set up duplex in the Device Control and Transmit Control
3546          * registers depending on negotiated values.
3547          */
3548         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3549                 DEBUGOUT("PHY Read Error\n");
3550                 return -E1000_ERR_PHY;
3551         }
3552         if (phy_data & M88E1000_PSSR_DPLX)
3553                 ctrl |= E1000_CTRL_FD;
3554         else
3555                 ctrl &= ~E1000_CTRL_FD;
3556
3557         e1000_config_collision_dist(hw);
3558
3559         /* Set up speed in the Device Control register depending on
3560          * negotiated values.
3561          */
3562         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3563                 ctrl |= E1000_CTRL_SPD_1000;
3564         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3565                 ctrl |= E1000_CTRL_SPD_100;
3566         /* Write the configured values back to the Device Control Reg. */
3567         E1000_WRITE_REG(hw, CTRL, ctrl);
3568         return 0;
3569 }
3570
3571 /******************************************************************************
3572  * Forces the MAC's flow control settings.
3573  *
3574  * hw - Struct containing variables accessed by shared code
3575  *
3576  * Sets the TFCE and RFCE bits in the device control register to reflect
3577  * the adapter settings. TFCE and RFCE need to be explicitly set by
3578  * software when a Copper PHY is used because autonegotiation is managed
3579  * by the PHY rather than the MAC. Software must also configure these
3580  * bits when link is forced on a fiber connection.
3581  *****************************************************************************/
3582 static int
3583 e1000_force_mac_fc(struct e1000_hw *hw)
3584 {
3585         uint32_t ctrl;
3586
3587         DEBUGFUNC();
3588
3589         /* Get the current configuration of the Device Control Register */
3590         ctrl = E1000_READ_REG(hw, CTRL);
3591
3592         /* Because we didn't get link via the internal auto-negotiation
3593          * mechanism (we either forced link or we got link via PHY
3594          * auto-neg), we have to manually enable/disable transmit an
3595          * receive flow control.
3596          *
3597          * The "Case" statement below enables/disable flow control
3598          * according to the "hw->fc" parameter.
3599          *
3600          * The possible values of the "fc" parameter are:
3601          *      0:  Flow control is completely disabled
3602          *      1:  Rx flow control is enabled (we can receive pause
3603          *          frames but not send pause frames).
3604          *      2:  Tx flow control is enabled (we can send pause frames
3605          *          frames but we do not receive pause frames).
3606          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3607          *  other:  No other values should be possible at this point.
3608          */
3609
3610         switch (hw->fc) {
3611         case e1000_fc_none:
3612                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3613                 break;
3614         case e1000_fc_rx_pause:
3615                 ctrl &= (~E1000_CTRL_TFCE);
3616                 ctrl |= E1000_CTRL_RFCE;
3617                 break;
3618         case e1000_fc_tx_pause:
3619                 ctrl &= (~E1000_CTRL_RFCE);
3620                 ctrl |= E1000_CTRL_TFCE;
3621                 break;
3622         case e1000_fc_full:
3623                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3624                 break;
3625         default:
3626                 DEBUGOUT("Flow control param set incorrectly\n");
3627                 return -E1000_ERR_CONFIG;
3628         }
3629
3630         /* Disable TX Flow Control for 82542 (rev 2.0) */
3631         if (hw->mac_type == e1000_82542_rev2_0)
3632                 ctrl &= (~E1000_CTRL_TFCE);
3633
3634         E1000_WRITE_REG(hw, CTRL, ctrl);
3635         return 0;
3636 }
3637
3638 /******************************************************************************
3639  * Configures flow control settings after link is established
3640  *
3641  * hw - Struct containing variables accessed by shared code
3642  *
3643  * Should be called immediately after a valid link has been established.
3644  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3645  * and autonegotiation is enabled, the MAC flow control settings will be set
3646  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3647  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3648  *****************************************************************************/
3649 static int32_t
3650 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3651 {
3652         int32_t ret_val;
3653         uint16_t mii_status_reg;
3654         uint16_t mii_nway_adv_reg;
3655         uint16_t mii_nway_lp_ability_reg;
3656         uint16_t speed;
3657         uint16_t duplex;
3658
3659         DEBUGFUNC();
3660
3661         /* Check for the case where we have fiber media and auto-neg failed
3662          * so we had to force link.  In this case, we need to force the
3663          * configuration of the MAC to match the "fc" parameter.
3664          */
3665         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3666                 || ((hw->media_type == e1000_media_type_internal_serdes)
3667                 && (hw->autoneg_failed))
3668                 || ((hw->media_type == e1000_media_type_copper)
3669                 && (!hw->autoneg))) {
3670                 ret_val = e1000_force_mac_fc(hw);
3671                 if (ret_val < 0) {
3672                         DEBUGOUT("Error forcing flow control settings\n");
3673                         return ret_val;
3674                 }
3675         }
3676
3677         /* Check for the case where we have copper media and auto-neg is
3678          * enabled.  In this case, we need to check and see if Auto-Neg
3679          * has completed, and if so, how the PHY and link partner has
3680          * flow control configured.
3681          */
3682         if (hw->media_type == e1000_media_type_copper) {
3683                 /* Read the MII Status Register and check to see if AutoNeg
3684                  * has completed.  We read this twice because this reg has
3685                  * some "sticky" (latched) bits.
3686                  */
3687                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3688                         DEBUGOUT("PHY Read Error\n");
3689                         return -E1000_ERR_PHY;
3690                 }
3691                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3692                         DEBUGOUT("PHY Read Error\n");
3693                         return -E1000_ERR_PHY;
3694                 }
3695
3696                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3697                         /* The AutoNeg process has completed, so we now need to
3698                          * read both the Auto Negotiation Advertisement Register
3699                          * (Address 4) and the Auto_Negotiation Base Page Ability
3700                          * Register (Address 5) to determine how flow control was
3701                          * negotiated.
3702                          */
3703                         if (e1000_read_phy_reg
3704                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3705                                 DEBUGOUT("PHY Read Error\n");
3706                                 return -E1000_ERR_PHY;
3707                         }
3708                         if (e1000_read_phy_reg
3709                             (hw, PHY_LP_ABILITY,
3710                              &mii_nway_lp_ability_reg) < 0) {
3711                                 DEBUGOUT("PHY Read Error\n");
3712                                 return -E1000_ERR_PHY;
3713                         }
3714
3715                         /* Two bits in the Auto Negotiation Advertisement Register
3716                          * (Address 4) and two bits in the Auto Negotiation Base
3717                          * Page Ability Register (Address 5) determine flow control
3718                          * for both the PHY and the link partner.  The following
3719                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3720                          * 1999, describes these PAUSE resolution bits and how flow
3721                          * control is determined based upon these settings.
3722                          * NOTE:  DC = Don't Care
3723                          *
3724                          *   LOCAL DEVICE  |   LINK PARTNER
3725                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3726                          *-------|---------|-------|---------|--------------------
3727                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3728                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3729                          *   0   |    1    |   1   |    0    | e1000_fc_none
3730                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3731                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3732                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3733                          *   1   |    1    |   0   |    0    | e1000_fc_none
3734                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3735                          *
3736                          */
3737                         /* Are both PAUSE bits set to 1?  If so, this implies
3738                          * Symmetric Flow Control is enabled at both ends.  The
3739                          * ASM_DIR bits are irrelevant per the spec.
3740                          *
3741                          * For Symmetric Flow Control:
3742                          *
3743                          *   LOCAL DEVICE  |   LINK PARTNER
3744                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3745                          *-------|---------|-------|---------|--------------------
3746                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3747                          *
3748                          */
3749                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3750                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3751                                 /* Now we need to check if the user selected RX ONLY
3752                                  * of pause frames.  In this case, we had to advertise
3753                                  * FULL flow control because we could not advertise RX
3754                                  * ONLY. Hence, we must now check to see if we need to
3755                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3756                                  */
3757                                 if (hw->original_fc == e1000_fc_full) {
3758                                         hw->fc = e1000_fc_full;
3759                                         DEBUGOUT("Flow Control = FULL.\r\n");
3760                                 } else {
3761                                         hw->fc = e1000_fc_rx_pause;
3762                                         DEBUGOUT
3763                                             ("Flow Control = RX PAUSE frames only.\r\n");
3764                                 }
3765                         }
3766                         /* For receiving PAUSE frames ONLY.
3767                          *
3768                          *   LOCAL DEVICE  |   LINK PARTNER
3769                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3770                          *-------|---------|-------|---------|--------------------
3771                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3772                          *
3773                          */
3774                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3775                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3776                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3777                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3778                         {
3779                                 hw->fc = e1000_fc_tx_pause;
3780                                 DEBUGOUT
3781                                     ("Flow Control = TX PAUSE frames only.\r\n");
3782                         }
3783                         /* For transmitting PAUSE frames ONLY.
3784                          *
3785                          *   LOCAL DEVICE  |   LINK PARTNER
3786                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3787                          *-------|---------|-------|---------|--------------------
3788                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3789                          *
3790                          */
3791                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3792                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3793                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3794                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3795                         {
3796                                 hw->fc = e1000_fc_rx_pause;
3797                                 DEBUGOUT
3798                                     ("Flow Control = RX PAUSE frames only.\r\n");
3799                         }
3800                         /* Per the IEEE spec, at this point flow control should be
3801                          * disabled.  However, we want to consider that we could
3802                          * be connected to a legacy switch that doesn't advertise
3803                          * desired flow control, but can be forced on the link
3804                          * partner.  So if we advertised no flow control, that is
3805                          * what we will resolve to.  If we advertised some kind of
3806                          * receive capability (Rx Pause Only or Full Flow Control)
3807                          * and the link partner advertised none, we will configure
3808                          * ourselves to enable Rx Flow Control only.  We can do
3809                          * this safely for two reasons:  If the link partner really
3810                          * didn't want flow control enabled, and we enable Rx, no
3811                          * harm done since we won't be receiving any PAUSE frames
3812                          * anyway.  If the intent on the link partner was to have
3813                          * flow control enabled, then by us enabling RX only, we
3814                          * can at least receive pause frames and process them.
3815                          * This is a good idea because in most cases, since we are
3816                          * predominantly a server NIC, more times than not we will
3817                          * be asked to delay transmission of packets than asking
3818                          * our link partner to pause transmission of frames.
3819                          */
3820                         else if (hw->original_fc == e1000_fc_none ||
3821                                  hw->original_fc == e1000_fc_tx_pause) {
3822                                 hw->fc = e1000_fc_none;
3823                                 DEBUGOUT("Flow Control = NONE.\r\n");
3824                         } else {
3825                                 hw->fc = e1000_fc_rx_pause;
3826                                 DEBUGOUT
3827                                     ("Flow Control = RX PAUSE frames only.\r\n");
3828                         }
3829
3830                         /* Now we need to do one last check...  If we auto-
3831                          * negotiated to HALF DUPLEX, flow control should not be
3832                          * enabled per IEEE 802.3 spec.
3833                          */
3834                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3835
3836                         if (duplex == HALF_DUPLEX)
3837                                 hw->fc = e1000_fc_none;
3838
3839                         /* Now we call a subroutine to actually force the MAC
3840                          * controller to use the correct flow control settings.
3841                          */
3842                         ret_val = e1000_force_mac_fc(hw);
3843                         if (ret_val < 0) {
3844                                 DEBUGOUT
3845                                     ("Error forcing flow control settings\n");
3846                                 return ret_val;
3847                         }
3848                 } else {
3849                         DEBUGOUT
3850                             ("Copper PHY and Auto Neg has not completed.\r\n");
3851                 }
3852         }
3853         return E1000_SUCCESS;
3854 }
3855
3856 /******************************************************************************
3857  * Checks to see if the link status of the hardware has changed.
3858  *
3859  * hw - Struct containing variables accessed by shared code
3860  *
3861  * Called by any function that needs to check the link status of the adapter.
3862  *****************************************************************************/
3863 static int
3864 e1000_check_for_link(struct e1000_hw *hw)
3865 {
3866         uint32_t rxcw;
3867         uint32_t ctrl;
3868         uint32_t status;
3869         uint32_t rctl;
3870         uint32_t signal;
3871         int32_t ret_val;
3872         uint16_t phy_data;
3873         uint16_t lp_capability;
3874
3875         DEBUGFUNC();
3876
3877         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3878          * set when the optics detect a signal. On older adapters, it will be
3879          * cleared when there is a signal
3880          */
3881         ctrl = E1000_READ_REG(hw, CTRL);
3882         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3883                 signal = E1000_CTRL_SWDPIN1;
3884         else
3885                 signal = 0;
3886
3887         status = E1000_READ_REG(hw, STATUS);
3888         rxcw = E1000_READ_REG(hw, RXCW);
3889         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3890
3891         /* If we have a copper PHY then we only want to go out to the PHY
3892          * registers to see if Auto-Neg has completed and/or if our link
3893          * status has changed.  The get_link_status flag will be set if we
3894          * receive a Link Status Change interrupt or we have Rx Sequence
3895          * Errors.
3896          */
3897         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3898                 /* First we want to see if the MII Status Register reports
3899                  * link.  If so, then we want to get the current speed/duplex
3900                  * of the PHY.
3901                  * Read the register twice since the link bit is sticky.
3902                  */
3903                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3904                         DEBUGOUT("PHY Read Error\n");
3905                         return -E1000_ERR_PHY;
3906                 }
3907                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3908                         DEBUGOUT("PHY Read Error\n");
3909                         return -E1000_ERR_PHY;
3910                 }
3911
3912                 if (phy_data & MII_SR_LINK_STATUS) {
3913                         hw->get_link_status = false;
3914                 } else {
3915                         /* No link detected */
3916                         return -E1000_ERR_NOLINK;
3917                 }
3918
3919                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3920                  * have Si on board that is 82544 or newer, Auto
3921                  * Speed Detection takes care of MAC speed/duplex
3922                  * configuration.  So we only need to configure Collision
3923                  * Distance in the MAC.  Otherwise, we need to force
3924                  * speed/duplex on the MAC to the current PHY speed/duplex
3925                  * settings.
3926                  */
3927                 if (hw->mac_type >= e1000_82544)
3928                         e1000_config_collision_dist(hw);
3929                 else {
3930                         ret_val = e1000_config_mac_to_phy(hw);
3931                         if (ret_val < 0) {
3932                                 DEBUGOUT
3933                                     ("Error configuring MAC to PHY settings\n");
3934                                 return ret_val;
3935                         }
3936                 }
3937
3938                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3939                  * need to restore the desired flow control settings because we may
3940                  * have had to re-autoneg with a different link partner.
3941                  */
3942                 ret_val = e1000_config_fc_after_link_up(hw);
3943                 if (ret_val < 0) {
3944                         DEBUGOUT("Error configuring flow control\n");
3945                         return ret_val;
3946                 }
3947
3948                 /* At this point we know that we are on copper and we have
3949                  * auto-negotiated link.  These are conditions for checking the link
3950                  * parter capability register.  We use the link partner capability to
3951                  * determine if TBI Compatibility needs to be turned on or off.  If
3952                  * the link partner advertises any speed in addition to Gigabit, then
3953                  * we assume that they are GMII-based, and TBI compatibility is not
3954                  * needed. If no other speeds are advertised, we assume the link
3955                  * partner is TBI-based, and we turn on TBI Compatibility.
3956                  */
3957                 if (hw->tbi_compatibility_en) {
3958                         if (e1000_read_phy_reg
3959                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3960                                 DEBUGOUT("PHY Read Error\n");
3961                                 return -E1000_ERR_PHY;
3962                         }
3963                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3964                                              NWAY_LPAR_10T_FD_CAPS |
3965                                              NWAY_LPAR_100TX_HD_CAPS |
3966                                              NWAY_LPAR_100TX_FD_CAPS |
3967                                              NWAY_LPAR_100T4_CAPS)) {
3968                                 /* If our link partner advertises anything in addition to
3969                                  * gigabit, we do not need to enable TBI compatibility.
3970                                  */
3971                                 if (hw->tbi_compatibility_on) {
3972                                         /* If we previously were in the mode, turn it off. */
3973                                         rctl = E1000_READ_REG(hw, RCTL);
3974                                         rctl &= ~E1000_RCTL_SBP;
3975                                         E1000_WRITE_REG(hw, RCTL, rctl);
3976                                         hw->tbi_compatibility_on = false;
3977                                 }
3978                         } else {
3979                                 /* If TBI compatibility is was previously off, turn it on. For
3980                                  * compatibility with a TBI link partner, we will store bad
3981                                  * packets. Some frames have an additional byte on the end and
3982                                  * will look like CRC errors to to the hardware.
3983                                  */
3984                                 if (!hw->tbi_compatibility_on) {
3985                                         hw->tbi_compatibility_on = true;
3986                                         rctl = E1000_READ_REG(hw, RCTL);
3987                                         rctl |= E1000_RCTL_SBP;
3988                                         E1000_WRITE_REG(hw, RCTL, rctl);
3989                                 }
3990                         }
3991                 }
3992         }
3993         /* If we don't have link (auto-negotiation failed or link partner cannot
3994          * auto-negotiate), the cable is plugged in (we have signal), and our
3995          * link partner is not trying to auto-negotiate with us (we are receiving
3996          * idles or data), we need to force link up. We also need to give
3997          * auto-negotiation time to complete, in case the cable was just plugged
3998          * in. The autoneg_failed flag does this.
3999          */
4000         else if ((hw->media_type == e1000_media_type_fiber) &&
4001                  (!(status & E1000_STATUS_LU)) &&
4002                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
4003                  (!(rxcw & E1000_RXCW_C))) {
4004                 if (hw->autoneg_failed == 0) {
4005                         hw->autoneg_failed = 1;
4006                         return 0;
4007                 }
4008                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
4009
4010                 /* Disable auto-negotiation in the TXCW register */
4011                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
4012
4013                 /* Force link-up and also force full-duplex. */
4014                 ctrl = E1000_READ_REG(hw, CTRL);
4015                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4016                 E1000_WRITE_REG(hw, CTRL, ctrl);
4017
4018                 /* Configure Flow Control after forcing link up. */
4019                 ret_val = e1000_config_fc_after_link_up(hw);
4020                 if (ret_val < 0) {
4021                         DEBUGOUT("Error configuring flow control\n");
4022                         return ret_val;
4023                 }
4024         }
4025         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
4026          * auto-negotiation in the TXCW register and disable forced link in the
4027          * Device Control register in an attempt to auto-negotiate with our link
4028          * partner.
4029          */
4030         else if ((hw->media_type == e1000_media_type_fiber) &&
4031                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4032                 DEBUGOUT
4033                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
4034                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
4035                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4036         }
4037         return 0;
4038 }
4039
4040 /******************************************************************************
4041 * Configure the MAC-to-PHY interface for 10/100Mbps
4042 *
4043 * hw - Struct containing variables accessed by shared code
4044 ******************************************************************************/
4045 static int32_t
4046 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
4047 {
4048         int32_t ret_val = E1000_SUCCESS;
4049         uint32_t tipg;
4050         uint16_t reg_data;
4051
4052         DEBUGFUNC();
4053
4054         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4055         ret_val = e1000_write_kmrn_reg(hw,
4056                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4057         if (ret_val)
4058                 return ret_val;
4059
4060         /* Configure Transmit Inter-Packet Gap */
4061         tipg = E1000_READ_REG(hw, TIPG);
4062         tipg &= ~E1000_TIPG_IPGT_MASK;
4063         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4064         E1000_WRITE_REG(hw, TIPG, tipg);
4065
4066         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4067
4068         if (ret_val)
4069                 return ret_val;
4070
4071         if (duplex == HALF_DUPLEX)
4072                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4073         else
4074                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4075
4076         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4077
4078         return ret_val;
4079 }
4080
4081 static int32_t
4082 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4083 {
4084         int32_t ret_val = E1000_SUCCESS;
4085         uint16_t reg_data;
4086         uint32_t tipg;
4087
4088         DEBUGFUNC();
4089
4090         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4091         ret_val = e1000_write_kmrn_reg(hw,
4092                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4093         if (ret_val)
4094                 return ret_val;
4095
4096         /* Configure Transmit Inter-Packet Gap */
4097         tipg = E1000_READ_REG(hw, TIPG);
4098         tipg &= ~E1000_TIPG_IPGT_MASK;
4099         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4100         E1000_WRITE_REG(hw, TIPG, tipg);
4101
4102         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4103
4104         if (ret_val)
4105                 return ret_val;
4106
4107         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4108         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4109
4110         return ret_val;
4111 }
4112
4113 /******************************************************************************
4114  * Detects the current speed and duplex settings of the hardware.
4115  *
4116  * hw - Struct containing variables accessed by shared code
4117  * speed - Speed of the connection
4118  * duplex - Duplex setting of the connection
4119  *****************************************************************************/
4120 static int
4121 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4122                 uint16_t *duplex)
4123 {
4124         uint32_t status;
4125         int32_t ret_val;
4126         uint16_t phy_data;
4127
4128         DEBUGFUNC();
4129
4130         if (hw->mac_type >= e1000_82543) {
4131                 status = E1000_READ_REG(hw, STATUS);
4132                 if (status & E1000_STATUS_SPEED_1000) {
4133                         *speed = SPEED_1000;
4134                         DEBUGOUT("1000 Mbs, ");
4135                 } else if (status & E1000_STATUS_SPEED_100) {
4136                         *speed = SPEED_100;
4137                         DEBUGOUT("100 Mbs, ");
4138                 } else {
4139                         *speed = SPEED_10;
4140                         DEBUGOUT("10 Mbs, ");
4141                 }
4142
4143                 if (status & E1000_STATUS_FD) {
4144                         *duplex = FULL_DUPLEX;
4145                         DEBUGOUT("Full Duplex\r\n");
4146                 } else {
4147                         *duplex = HALF_DUPLEX;
4148                         DEBUGOUT(" Half Duplex\r\n");
4149                 }
4150         } else {
4151                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4152                 *speed = SPEED_1000;
4153                 *duplex = FULL_DUPLEX;
4154         }
4155
4156         /* IGP01 PHY may advertise full duplex operation after speed downgrade
4157          * even if it is operating at half duplex.  Here we set the duplex
4158          * settings to match the duplex in the link partner's capabilities.
4159          */
4160         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4161                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4162                 if (ret_val)
4163                         return ret_val;
4164
4165                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4166                         *duplex = HALF_DUPLEX;
4167                 else {
4168                         ret_val = e1000_read_phy_reg(hw,
4169                                         PHY_LP_ABILITY, &phy_data);
4170                         if (ret_val)
4171                                 return ret_val;
4172                         if ((*speed == SPEED_100 &&
4173                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4174                                 || (*speed == SPEED_10
4175                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4176                                 *duplex = HALF_DUPLEX;
4177                 }
4178         }
4179
4180         if ((hw->mac_type == e1000_80003es2lan) &&
4181                 (hw->media_type == e1000_media_type_copper)) {
4182                 if (*speed == SPEED_1000)
4183                         ret_val = e1000_configure_kmrn_for_1000(hw);
4184                 else
4185                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4186                 if (ret_val)
4187                         return ret_val;
4188         }
4189         return E1000_SUCCESS;
4190 }
4191
4192 /******************************************************************************
4193 * Blocks until autoneg completes or times out (~4.5 seconds)
4194 *
4195 * hw - Struct containing variables accessed by shared code
4196 ******************************************************************************/
4197 static int
4198 e1000_wait_autoneg(struct e1000_hw *hw)
4199 {
4200         uint16_t i;
4201         uint16_t phy_data;
4202
4203         DEBUGFUNC();
4204         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4205
4206         /* We will wait for autoneg to complete or timeout to expire. */
4207         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4208                 /* Read the MII Status Register and wait for Auto-Neg
4209                  * Complete bit to be set.
4210                  */
4211                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4212                         DEBUGOUT("PHY Read Error\n");
4213                         return -E1000_ERR_PHY;
4214                 }
4215                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4216                         DEBUGOUT("PHY Read Error\n");
4217                         return -E1000_ERR_PHY;
4218                 }
4219                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4220                         DEBUGOUT("Auto-Neg complete.\n");
4221                         return 0;
4222                 }
4223                 mdelay(100);
4224         }
4225         DEBUGOUT("Auto-Neg timedout.\n");
4226         return -E1000_ERR_TIMEOUT;
4227 }
4228
4229 /******************************************************************************
4230 * Raises the Management Data Clock
4231 *
4232 * hw - Struct containing variables accessed by shared code
4233 * ctrl - Device control register's current value
4234 ******************************************************************************/
4235 static void
4236 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4237 {
4238         /* Raise the clock input to the Management Data Clock (by setting the MDC
4239          * bit), and then delay 2 microseconds.
4240          */
4241         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4242         E1000_WRITE_FLUSH(hw);
4243         udelay(2);
4244 }
4245
4246 /******************************************************************************
4247 * Lowers the Management Data Clock
4248 *
4249 * hw - Struct containing variables accessed by shared code
4250 * ctrl - Device control register's current value
4251 ******************************************************************************/
4252 static void
4253 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4254 {
4255         /* Lower the clock input to the Management Data Clock (by clearing the MDC
4256          * bit), and then delay 2 microseconds.
4257          */
4258         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4259         E1000_WRITE_FLUSH(hw);
4260         udelay(2);
4261 }
4262
4263 /******************************************************************************
4264 * Shifts data bits out to the PHY
4265 *
4266 * hw - Struct containing variables accessed by shared code
4267 * data - Data to send out to the PHY
4268 * count - Number of bits to shift out
4269 *
4270 * Bits are shifted out in MSB to LSB order.
4271 ******************************************************************************/
4272 static void
4273 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4274 {
4275         uint32_t ctrl;
4276         uint32_t mask;
4277
4278         /* We need to shift "count" number of bits out to the PHY. So, the value
4279          * in the "data" parameter will be shifted out to the PHY one bit at a
4280          * time. In order to do this, "data" must be broken down into bits.
4281          */
4282         mask = 0x01;
4283         mask <<= (count - 1);
4284
4285         ctrl = E1000_READ_REG(hw, CTRL);
4286
4287         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4288         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4289
4290         while (mask) {
4291                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4292                  * then raising and lowering the Management Data Clock. A "0" is
4293                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4294                  * raising and lowering the clock.
4295                  */
4296                 if (data & mask)
4297                         ctrl |= E1000_CTRL_MDIO;
4298                 else
4299                         ctrl &= ~E1000_CTRL_MDIO;
4300
4301                 E1000_WRITE_REG(hw, CTRL, ctrl);
4302                 E1000_WRITE_FLUSH(hw);
4303
4304                 udelay(2);
4305
4306                 e1000_raise_mdi_clk(hw, &ctrl);
4307                 e1000_lower_mdi_clk(hw, &ctrl);
4308
4309                 mask = mask >> 1;
4310         }
4311 }
4312
4313 /******************************************************************************
4314 * Shifts data bits in from the PHY
4315 *
4316 * hw - Struct containing variables accessed by shared code
4317 *
4318 * Bits are shifted in in MSB to LSB order.
4319 ******************************************************************************/
4320 static uint16_t
4321 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4322 {
4323         uint32_t ctrl;
4324         uint16_t data = 0;
4325         uint8_t i;
4326
4327         /* In order to read a register from the PHY, we need to shift in a total
4328          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4329          * to avoid contention on the MDIO pin when a read operation is performed.
4330          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4331          * by raising the input to the Management Data Clock (setting the MDC bit),
4332          * and then reading the value of the MDIO bit.
4333          */
4334         ctrl = E1000_READ_REG(hw, CTRL);
4335
4336         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4337         ctrl &= ~E1000_CTRL_MDIO_DIR;
4338         ctrl &= ~E1000_CTRL_MDIO;
4339
4340         E1000_WRITE_REG(hw, CTRL, ctrl);
4341         E1000_WRITE_FLUSH(hw);
4342
4343         /* Raise and Lower the clock before reading in the data. This accounts for
4344          * the turnaround bits. The first clock occurred when we clocked out the
4345          * last bit of the Register Address.
4346          */
4347         e1000_raise_mdi_clk(hw, &ctrl);
4348         e1000_lower_mdi_clk(hw, &ctrl);
4349
4350         for (data = 0, i = 0; i < 16; i++) {
4351                 data = data << 1;
4352                 e1000_raise_mdi_clk(hw, &ctrl);
4353                 ctrl = E1000_READ_REG(hw, CTRL);
4354                 /* Check to see if we shifted in a "1". */
4355                 if (ctrl & E1000_CTRL_MDIO)
4356                         data |= 1;
4357                 e1000_lower_mdi_clk(hw, &ctrl);
4358         }
4359
4360         e1000_raise_mdi_clk(hw, &ctrl);
4361         e1000_lower_mdi_clk(hw, &ctrl);
4362
4363         return data;
4364 }
4365
4366 /*****************************************************************************
4367 * Reads the value from a PHY register
4368 *
4369 * hw - Struct containing variables accessed by shared code
4370 * reg_addr - address of the PHY register to read
4371 ******************************************************************************/
4372 static int
4373 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4374 {
4375         uint32_t i;
4376         uint32_t mdic = 0;
4377         const uint32_t phy_addr = 1;
4378
4379         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4380                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4381                 return -E1000_ERR_PARAM;
4382         }
4383
4384         if (hw->mac_type > e1000_82543) {
4385                 /* Set up Op-code, Phy Address, and register address in the MDI
4386                  * Control register.  The MAC will take care of interfacing with the
4387                  * PHY to retrieve the desired data.
4388                  */
4389                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4390                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4391                         (E1000_MDIC_OP_READ));
4392
4393                 E1000_WRITE_REG(hw, MDIC, mdic);
4394
4395                 /* Poll the ready bit to see if the MDI read completed */
4396                 for (i = 0; i < 64; i++) {
4397                         udelay(10);
4398                         mdic = E1000_READ_REG(hw, MDIC);
4399                         if (mdic & E1000_MDIC_READY)
4400                                 break;
4401                 }
4402                 if (!(mdic & E1000_MDIC_READY)) {
4403                         DEBUGOUT("MDI Read did not complete\n");
4404                         return -E1000_ERR_PHY;
4405                 }
4406                 if (mdic & E1000_MDIC_ERROR) {
4407                         DEBUGOUT("MDI Error\n");
4408                         return -E1000_ERR_PHY;
4409                 }
4410                 *phy_data = (uint16_t) mdic;
4411         } else {
4412                 /* We must first send a preamble through the MDIO pin to signal the
4413                  * beginning of an MII instruction.  This is done by sending 32
4414                  * consecutive "1" bits.
4415                  */
4416                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4417
4418                 /* Now combine the next few fields that are required for a read
4419                  * operation.  We use this method instead of calling the
4420                  * e1000_shift_out_mdi_bits routine five different times. The format of
4421                  * a MII read instruction consists of a shift out of 14 bits and is
4422                  * defined as follows:
4423                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4424                  * followed by a shift in of 18 bits.  This first two bits shifted in
4425                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4426                  * READ operation is performed.  These two bits are thrown away
4427                  * followed by a shift in of 16 bits which contains the desired data.
4428                  */
4429                 mdic = ((reg_addr) | (phy_addr << 5) |
4430                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4431
4432                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4433
4434                 /* Now that we've shifted out the read command to the MII, we need to
4435                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4436                  * register address.
4437                  */
4438                 *phy_data = e1000_shift_in_mdi_bits(hw);
4439         }
4440         return 0;
4441 }
4442
4443 /******************************************************************************
4444 * Writes a value to a PHY register
4445 *
4446 * hw - Struct containing variables accessed by shared code
4447 * reg_addr - address of the PHY register to write
4448 * data - data to write to the PHY
4449 ******************************************************************************/
4450 static int
4451 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4452 {
4453         uint32_t i;
4454         uint32_t mdic = 0;
4455         const uint32_t phy_addr = 1;
4456
4457         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4458                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4459                 return -E1000_ERR_PARAM;
4460         }
4461
4462         if (hw->mac_type > e1000_82543) {
4463                 /* Set up Op-code, Phy Address, register address, and data intended
4464                  * for the PHY register in the MDI Control register.  The MAC will take
4465                  * care of interfacing with the PHY to send the desired data.
4466                  */
4467                 mdic = (((uint32_t) phy_data) |
4468                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4469                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4470                         (E1000_MDIC_OP_WRITE));
4471
4472                 E1000_WRITE_REG(hw, MDIC, mdic);
4473
4474                 /* Poll the ready bit to see if the MDI read completed */
4475                 for (i = 0; i < 64; i++) {
4476                         udelay(10);
4477                         mdic = E1000_READ_REG(hw, MDIC);
4478                         if (mdic & E1000_MDIC_READY)
4479                                 break;
4480                 }
4481                 if (!(mdic & E1000_MDIC_READY)) {
4482                         DEBUGOUT("MDI Write did not complete\n");
4483                         return -E1000_ERR_PHY;
4484                 }
4485         } else {
4486                 /* We'll need to use the SW defined pins to shift the write command
4487                  * out to the PHY. We first send a preamble to the PHY to signal the
4488                  * beginning of the MII instruction.  This is done by sending 32
4489                  * consecutive "1" bits.
4490                  */
4491                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4492
4493                 /* Now combine the remaining required fields that will indicate a
4494                  * write operation. We use this method instead of calling the
4495                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4496                  * format of a MII write instruction is as follows:
4497                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4498                  */
4499                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4500                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4501                 mdic <<= 16;
4502                 mdic |= (uint32_t) phy_data;
4503
4504                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4505         }
4506         return 0;
4507 }
4508
4509 /******************************************************************************
4510  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4511  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4512  * the caller to figure out how to deal with it.
4513  *
4514  * hw - Struct containing variables accessed by shared code
4515  *
4516  * returns: - E1000_BLK_PHY_RESET
4517  *            E1000_SUCCESS
4518  *
4519  *****************************************************************************/
4520 int32_t
4521 e1000_check_phy_reset_block(struct e1000_hw *hw)
4522 {
4523         uint32_t manc = 0;
4524         uint32_t fwsm = 0;
4525
4526         if (hw->mac_type == e1000_ich8lan) {
4527                 fwsm = E1000_READ_REG(hw, FWSM);
4528                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4529                                                 : E1000_BLK_PHY_RESET;
4530         }
4531
4532         if (hw->mac_type > e1000_82547_rev_2)
4533                 manc = E1000_READ_REG(hw, MANC);
4534         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4535                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4536 }
4537
4538 /***************************************************************************
4539  * Checks if the PHY configuration is done
4540  *
4541  * hw: Struct containing variables accessed by shared code
4542  *
4543  * returns: - E1000_ERR_RESET if fail to reset MAC
4544  *            E1000_SUCCESS at any other case.
4545  *
4546  ***************************************************************************/
4547 static int32_t
4548 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4549 {
4550         int32_t timeout = PHY_CFG_TIMEOUT;
4551         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4552
4553         DEBUGFUNC();
4554
4555         switch (hw->mac_type) {
4556         default:
4557                 mdelay(10);
4558                 break;
4559
4560         case e1000_80003es2lan:
4561                 /* Separate *_CFG_DONE_* bit for each port */
4562                 if (e1000_is_second_port(hw))
4563                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4564                 /* Fall Through */
4565
4566         case e1000_82571:
4567         case e1000_82572:
4568         case e1000_igb:
4569                 while (timeout) {
4570                         if (hw->mac_type == e1000_igb) {
4571                                 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4572                                         break;
4573                         } else {
4574                                 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4575                                         break;
4576                         }
4577                         mdelay(1);
4578                         timeout--;
4579                 }
4580                 if (!timeout) {
4581                         DEBUGOUT("MNG configuration cycle has not "
4582                                         "completed.\n");
4583                         return -E1000_ERR_RESET;
4584                 }
4585                 break;
4586         }
4587
4588         return E1000_SUCCESS;
4589 }
4590
4591 /******************************************************************************
4592 * Returns the PHY to the power-on reset state
4593 *
4594 * hw - Struct containing variables accessed by shared code
4595 ******************************************************************************/
4596 int32_t
4597 e1000_phy_hw_reset(struct e1000_hw *hw)
4598 {
4599         uint16_t swfw = E1000_SWFW_PHY0_SM;
4600         uint32_t ctrl, ctrl_ext;
4601         uint32_t led_ctrl;
4602         int32_t ret_val;
4603
4604         DEBUGFUNC();
4605
4606         /* In the case of the phy reset being blocked, it's not an error, we
4607          * simply return success without performing the reset. */
4608         ret_val = e1000_check_phy_reset_block(hw);
4609         if (ret_val)
4610                 return E1000_SUCCESS;
4611
4612         DEBUGOUT("Resetting Phy...\n");
4613
4614         if (hw->mac_type > e1000_82543) {
4615                 if (e1000_is_second_port(hw))
4616                         swfw = E1000_SWFW_PHY1_SM;
4617
4618                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4619                         DEBUGOUT("Unable to acquire swfw sync\n");
4620                         return -E1000_ERR_SWFW_SYNC;
4621                 }
4622
4623                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4624                  * bit. Then, take it out of reset.
4625                  */
4626                 ctrl = E1000_READ_REG(hw, CTRL);
4627                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4628                 E1000_WRITE_FLUSH(hw);
4629
4630                 if (hw->mac_type < e1000_82571)
4631                         udelay(10);
4632                 else
4633                         udelay(100);
4634
4635                 E1000_WRITE_REG(hw, CTRL, ctrl);
4636                 E1000_WRITE_FLUSH(hw);
4637
4638                 if (hw->mac_type >= e1000_82571)
4639                         mdelay(10);
4640
4641         } else {
4642                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4643                  * bit to put the PHY into reset. Then, take it out of reset.
4644                  */
4645                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4646                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4647                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4648                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4649                 E1000_WRITE_FLUSH(hw);
4650                 mdelay(10);
4651                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4652                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4653                 E1000_WRITE_FLUSH(hw);
4654         }
4655         udelay(150);
4656
4657         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4658                 /* Configure activity LED after PHY reset */
4659                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4660                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4661                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4662                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4663         }
4664
4665         e1000_swfw_sync_release(hw, swfw);
4666
4667         /* Wait for FW to finish PHY configuration. */
4668         ret_val = e1000_get_phy_cfg_done(hw);
4669         if (ret_val != E1000_SUCCESS)
4670                 return ret_val;
4671
4672         return ret_val;
4673 }
4674
4675 /******************************************************************************
4676  * IGP phy init script - initializes the GbE PHY
4677  *
4678  * hw - Struct containing variables accessed by shared code
4679  *****************************************************************************/
4680 static void
4681 e1000_phy_init_script(struct e1000_hw *hw)
4682 {
4683         uint32_t ret_val;
4684         uint16_t phy_saved_data;
4685         DEBUGFUNC();
4686
4687         if (hw->phy_init_script) {
4688                 mdelay(20);
4689
4690                 /* Save off the current value of register 0x2F5B to be
4691                  * restored at the end of this routine. */
4692                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4693
4694                 /* Disabled the PHY transmitter */
4695                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4696
4697                 mdelay(20);
4698
4699                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4700
4701                 mdelay(5);
4702
4703                 switch (hw->mac_type) {
4704                 case e1000_82541:
4705                 case e1000_82547:
4706                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4707
4708                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4709
4710                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4711
4712                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4713
4714                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4715
4716                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4717
4718                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4719
4720                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4721
4722                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4723                         break;
4724
4725                 case e1000_82541_rev_2:
4726                 case e1000_82547_rev_2:
4727                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4728                         break;
4729                 default:
4730                         break;
4731                 }
4732
4733                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4734
4735                 mdelay(20);
4736
4737                 /* Now enable the transmitter */
4738                 if (!ret_val)
4739                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4740
4741                 if (hw->mac_type == e1000_82547) {
4742                         uint16_t fused, fine, coarse;
4743
4744                         /* Move to analog registers page */
4745                         e1000_read_phy_reg(hw,
4746                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4747
4748                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4749                                 e1000_read_phy_reg(hw,
4750                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4751
4752                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4753                                 coarse = fused
4754                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4755
4756                                 if (coarse >
4757                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4758                                         coarse -=
4759                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4760                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4761                                 } else if (coarse
4762                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4763                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4764
4765                                 fused = (fused
4766                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4767                                         (fine
4768                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4769                                         (coarse
4770                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4771
4772                                 e1000_write_phy_reg(hw,
4773                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4774                                 e1000_write_phy_reg(hw,
4775                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4776                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4777                         }
4778                 }
4779         }
4780 }
4781
4782 /******************************************************************************
4783 * Resets the PHY
4784 *
4785 * hw - Struct containing variables accessed by shared code
4786 *
4787 * Sets bit 15 of the MII Control register
4788 ******************************************************************************/
4789 int32_t
4790 e1000_phy_reset(struct e1000_hw *hw)
4791 {
4792         int32_t ret_val;
4793         uint16_t phy_data;
4794
4795         DEBUGFUNC();
4796
4797         /* In the case of the phy reset being blocked, it's not an error, we
4798          * simply return success without performing the reset. */
4799         ret_val = e1000_check_phy_reset_block(hw);
4800         if (ret_val)
4801                 return E1000_SUCCESS;
4802
4803         switch (hw->phy_type) {
4804         case e1000_phy_igp:
4805         case e1000_phy_igp_2:
4806         case e1000_phy_igp_3:
4807         case e1000_phy_ife:
4808         case e1000_phy_igb:
4809                 ret_val = e1000_phy_hw_reset(hw);
4810                 if (ret_val)
4811                         return ret_val;
4812                 break;
4813         default:
4814                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4815                 if (ret_val)
4816                         return ret_val;
4817
4818                 phy_data |= MII_CR_RESET;
4819                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4820                 if (ret_val)
4821                         return ret_val;
4822
4823                 udelay(1);
4824                 break;
4825         }
4826
4827         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4828                 e1000_phy_init_script(hw);
4829
4830         return E1000_SUCCESS;
4831 }
4832
4833 static int e1000_set_phy_type (struct e1000_hw *hw)
4834 {
4835         DEBUGFUNC ();
4836
4837         if (hw->mac_type == e1000_undefined)
4838                 return -E1000_ERR_PHY_TYPE;
4839
4840         switch (hw->phy_id) {
4841         case M88E1000_E_PHY_ID:
4842         case M88E1000_I_PHY_ID:
4843         case M88E1011_I_PHY_ID:
4844         case M88E1111_I_PHY_ID:
4845                 hw->phy_type = e1000_phy_m88;
4846                 break;
4847         case IGP01E1000_I_PHY_ID:
4848                 if (hw->mac_type == e1000_82541 ||
4849                         hw->mac_type == e1000_82541_rev_2 ||
4850                         hw->mac_type == e1000_82547 ||
4851                         hw->mac_type == e1000_82547_rev_2) {
4852                         hw->phy_type = e1000_phy_igp;
4853                         break;
4854                 }
4855         case IGP03E1000_E_PHY_ID:
4856                 hw->phy_type = e1000_phy_igp_3;
4857                 break;
4858         case IFE_E_PHY_ID:
4859         case IFE_PLUS_E_PHY_ID:
4860         case IFE_C_E_PHY_ID:
4861                 hw->phy_type = e1000_phy_ife;
4862                 break;
4863         case GG82563_E_PHY_ID:
4864                 if (hw->mac_type == e1000_80003es2lan) {
4865                         hw->phy_type = e1000_phy_gg82563;
4866                         break;
4867                 }
4868         case BME1000_E_PHY_ID:
4869                 hw->phy_type = e1000_phy_bm;
4870                 break;
4871         case I210_I_PHY_ID:
4872                 hw->phy_type = e1000_phy_igb;
4873                 break;
4874                 /* Fall Through */
4875         default:
4876                 /* Should never have loaded on this device */
4877                 hw->phy_type = e1000_phy_undefined;
4878                 return -E1000_ERR_PHY_TYPE;
4879         }
4880
4881         return E1000_SUCCESS;
4882 }
4883
4884 /******************************************************************************
4885 * Probes the expected PHY address for known PHY IDs
4886 *
4887 * hw - Struct containing variables accessed by shared code
4888 ******************************************************************************/
4889 static int32_t
4890 e1000_detect_gig_phy(struct e1000_hw *hw)
4891 {
4892         int32_t phy_init_status, ret_val;
4893         uint16_t phy_id_high, phy_id_low;
4894         bool match = false;
4895
4896         DEBUGFUNC();
4897
4898         /* The 82571 firmware may still be configuring the PHY.  In this
4899          * case, we cannot access the PHY until the configuration is done.  So
4900          * we explicitly set the PHY values. */
4901         if (hw->mac_type == e1000_82571 ||
4902                 hw->mac_type == e1000_82572) {
4903                 hw->phy_id = IGP01E1000_I_PHY_ID;
4904                 hw->phy_type = e1000_phy_igp_2;
4905                 return E1000_SUCCESS;
4906         }
4907
4908         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4909          * work- around that forces PHY page 0 to be set or the reads fail.
4910          * The rest of the code in this routine uses e1000_read_phy_reg to
4911          * read the PHY ID.  So for ESB-2 we need to have this set so our
4912          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4913          * the routines below will figure this out as well. */
4914         if (hw->mac_type == e1000_80003es2lan)
4915                 hw->phy_type = e1000_phy_gg82563;
4916
4917         /* Read the PHY ID Registers to identify which PHY is onboard. */
4918         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4919         if (ret_val)
4920                 return ret_val;
4921
4922         hw->phy_id = (uint32_t) (phy_id_high << 16);
4923         udelay(20);
4924         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4925         if (ret_val)
4926                 return ret_val;
4927
4928         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4929         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4930
4931         switch (hw->mac_type) {
4932         case e1000_82543:
4933                 if (hw->phy_id == M88E1000_E_PHY_ID)
4934                         match = true;
4935                 break;
4936         case e1000_82544:
4937                 if (hw->phy_id == M88E1000_I_PHY_ID)
4938                         match = true;
4939                 break;
4940         case e1000_82540:
4941         case e1000_82545:
4942         case e1000_82545_rev_3:
4943         case e1000_82546:
4944         case e1000_82546_rev_3:
4945                 if (hw->phy_id == M88E1011_I_PHY_ID)
4946                         match = true;
4947                 break;
4948         case e1000_82541:
4949         case e1000_82541_rev_2:
4950         case e1000_82547:
4951         case e1000_82547_rev_2:
4952                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4953                         match = true;
4954
4955                 break;
4956         case e1000_82573:
4957                 if (hw->phy_id == M88E1111_I_PHY_ID)
4958                         match = true;
4959                 break;
4960         case e1000_82574:
4961                 if (hw->phy_id == BME1000_E_PHY_ID)
4962                         match = true;
4963                 break;
4964         case e1000_80003es2lan:
4965                 if (hw->phy_id == GG82563_E_PHY_ID)
4966                         match = true;
4967                 break;
4968         case e1000_ich8lan:
4969                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4970                         match = true;
4971                 if (hw->phy_id == IFE_E_PHY_ID)
4972                         match = true;
4973                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4974                         match = true;
4975                 if (hw->phy_id == IFE_C_E_PHY_ID)
4976                         match = true;
4977                 break;
4978         case e1000_igb:
4979                 if (hw->phy_id == I210_I_PHY_ID)
4980                         match = true;
4981                 break;
4982         default:
4983                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4984                 return -E1000_ERR_CONFIG;
4985         }
4986
4987         phy_init_status = e1000_set_phy_type(hw);
4988
4989         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4990                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4991                 return 0;
4992         }
4993         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4994         return -E1000_ERR_PHY;
4995 }
4996
4997 /*****************************************************************************
4998  * Set media type and TBI compatibility.
4999  *
5000  * hw - Struct containing variables accessed by shared code
5001  * **************************************************************************/
5002 void
5003 e1000_set_media_type(struct e1000_hw *hw)
5004 {
5005         uint32_t status;
5006
5007         DEBUGFUNC();
5008
5009         if (hw->mac_type != e1000_82543) {
5010                 /* tbi_compatibility is only valid on 82543 */
5011                 hw->tbi_compatibility_en = false;
5012         }
5013
5014         switch (hw->device_id) {
5015         case E1000_DEV_ID_82545GM_SERDES:
5016         case E1000_DEV_ID_82546GB_SERDES:
5017         case E1000_DEV_ID_82571EB_SERDES:
5018         case E1000_DEV_ID_82571EB_SERDES_DUAL:
5019         case E1000_DEV_ID_82571EB_SERDES_QUAD:
5020         case E1000_DEV_ID_82572EI_SERDES:
5021         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
5022                 hw->media_type = e1000_media_type_internal_serdes;
5023                 break;
5024         default:
5025                 switch (hw->mac_type) {
5026                 case e1000_82542_rev2_0:
5027                 case e1000_82542_rev2_1:
5028                         hw->media_type = e1000_media_type_fiber;
5029                         break;
5030                 case e1000_ich8lan:
5031                 case e1000_82573:
5032                 case e1000_82574:
5033                 case e1000_igb:
5034                         /* The STATUS_TBIMODE bit is reserved or reused
5035                          * for the this device.
5036                          */
5037                         hw->media_type = e1000_media_type_copper;
5038                         break;
5039                 default:
5040                         status = E1000_READ_REG(hw, STATUS);
5041                         if (status & E1000_STATUS_TBIMODE) {
5042                                 hw->media_type = e1000_media_type_fiber;
5043                                 /* tbi_compatibility not valid on fiber */
5044                                 hw->tbi_compatibility_en = false;
5045                         } else {
5046                                 hw->media_type = e1000_media_type_copper;
5047                         }
5048                         break;
5049                 }
5050         }
5051 }
5052
5053 /**
5054  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5055  *
5056  * e1000_sw_init initializes the Adapter private data structure.
5057  * Fields are initialized based on PCI device information and
5058  * OS network device settings (MTU size).
5059  **/
5060
5061 static int
5062 e1000_sw_init(struct e1000_hw *hw)
5063 {
5064         int result;
5065
5066         /* PCI config space info */
5067 #ifdef CONFIG_DM_ETH
5068         dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5069         dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5070         dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5071                              &hw->subsystem_vendor_id);
5072         dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5073
5074         dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5075         dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5076 #else
5077         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5078         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5079         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5080                              &hw->subsystem_vendor_id);
5081         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5082
5083         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5084         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5085 #endif
5086
5087         /* identify the MAC */
5088         result = e1000_set_mac_type(hw);
5089         if (result) {
5090                 E1000_ERR(hw, "Unknown MAC Type\n");
5091                 return result;
5092         }
5093
5094         switch (hw->mac_type) {
5095         default:
5096                 break;
5097         case e1000_82541:
5098         case e1000_82547:
5099         case e1000_82541_rev_2:
5100         case e1000_82547_rev_2:
5101                 hw->phy_init_script = 1;
5102                 break;
5103         }
5104
5105         /* flow control settings */
5106         hw->fc_high_water = E1000_FC_HIGH_THRESH;
5107         hw->fc_low_water = E1000_FC_LOW_THRESH;
5108         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5109         hw->fc_send_xon = 1;
5110
5111         /* Media type - copper or fiber */
5112         hw->tbi_compatibility_en = true;
5113         e1000_set_media_type(hw);
5114
5115         if (hw->mac_type >= e1000_82543) {
5116                 uint32_t status = E1000_READ_REG(hw, STATUS);
5117
5118                 if (status & E1000_STATUS_TBIMODE) {
5119                         DEBUGOUT("fiber interface\n");
5120                         hw->media_type = e1000_media_type_fiber;
5121                 } else {
5122                         DEBUGOUT("copper interface\n");
5123                         hw->media_type = e1000_media_type_copper;
5124                 }
5125         } else {
5126                 hw->media_type = e1000_media_type_fiber;
5127         }
5128
5129         hw->wait_autoneg_complete = true;
5130         if (hw->mac_type < e1000_82543)
5131                 hw->report_tx_early = 0;
5132         else
5133                 hw->report_tx_early = 1;
5134
5135         return E1000_SUCCESS;
5136 }
5137
5138 void
5139 fill_rx(struct e1000_hw *hw)
5140 {
5141         struct e1000_rx_desc *rd;
5142         unsigned long flush_start, flush_end;
5143
5144         rx_last = rx_tail;
5145         rd = rx_base + rx_tail;
5146         rx_tail = (rx_tail + 1) % 8;
5147         memset(rd, 0, 16);
5148         rd->buffer_addr = cpu_to_le64((unsigned long)packet);
5149
5150         /*
5151          * Make sure there are no stale data in WB over this area, which
5152          * might get written into the memory while the e1000 also writes
5153          * into the same memory area.
5154          */
5155         invalidate_dcache_range((unsigned long)packet,
5156                                 (unsigned long)packet + 4096);
5157         /* Dump the DMA descriptor into RAM. */
5158         flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5159         flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5160         flush_dcache_range(flush_start, flush_end);
5161
5162         E1000_WRITE_REG(hw, RDT, rx_tail);
5163 }
5164
5165 /**
5166  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5167  * @adapter: board private structure
5168  *
5169  * Configure the Tx unit of the MAC after a reset.
5170  **/
5171
5172 static void
5173 e1000_configure_tx(struct e1000_hw *hw)
5174 {
5175         unsigned long tctl;
5176         unsigned long tipg, tarc;
5177         uint32_t ipgr1, ipgr2;
5178
5179         E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
5180         E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
5181
5182         E1000_WRITE_REG(hw, TDLEN, 128);
5183
5184         /* Setup the HW Tx Head and Tail descriptor pointers */
5185         E1000_WRITE_REG(hw, TDH, 0);
5186         E1000_WRITE_REG(hw, TDT, 0);
5187         tx_tail = 0;
5188
5189         /* Set the default values for the Tx Inter Packet Gap timer */
5190         if (hw->mac_type <= e1000_82547_rev_2 &&
5191             (hw->media_type == e1000_media_type_fiber ||
5192              hw->media_type == e1000_media_type_internal_serdes))
5193                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5194         else
5195                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5196
5197         /* Set the default values for the Tx Inter Packet Gap timer */
5198         switch (hw->mac_type) {
5199         case e1000_82542_rev2_0:
5200         case e1000_82542_rev2_1:
5201                 tipg = DEFAULT_82542_TIPG_IPGT;
5202                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5203                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5204                 break;
5205         case e1000_80003es2lan:
5206                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5207                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5208                 break;
5209         default:
5210                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5211                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5212                 break;
5213         }
5214         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5215         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5216         E1000_WRITE_REG(hw, TIPG, tipg);
5217         /* Program the Transmit Control Register */
5218         tctl = E1000_READ_REG(hw, TCTL);
5219         tctl &= ~E1000_TCTL_CT;
5220         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5221             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5222
5223         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5224                 tarc = E1000_READ_REG(hw, TARC0);
5225                 /* set the speed mode bit, we'll clear it if we're not at
5226                  * gigabit link later */
5227                 /* git bit can be set to 1*/
5228         } else if (hw->mac_type == e1000_80003es2lan) {
5229                 tarc = E1000_READ_REG(hw, TARC0);
5230                 tarc |= 1;
5231                 E1000_WRITE_REG(hw, TARC0, tarc);
5232                 tarc = E1000_READ_REG(hw, TARC1);
5233                 tarc |= 1;
5234                 E1000_WRITE_REG(hw, TARC1, tarc);
5235         }
5236
5237
5238         e1000_config_collision_dist(hw);
5239         /* Setup Transmit Descriptor Settings for eop descriptor */
5240         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5241
5242         /* Need to set up RS bit */
5243         if (hw->mac_type < e1000_82543)
5244                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5245         else
5246                 hw->txd_cmd |= E1000_TXD_CMD_RS;
5247
5248
5249         if (hw->mac_type == e1000_igb) {
5250                 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5251
5252                 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5253                 reg_txdctl |= 1 << 25;
5254                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5255                 mdelay(20);
5256         }
5257
5258
5259
5260         E1000_WRITE_REG(hw, TCTL, tctl);
5261
5262
5263 }
5264
5265 /**
5266  * e1000_setup_rctl - configure the receive control register
5267  * @adapter: Board private structure
5268  **/
5269 static void
5270 e1000_setup_rctl(struct e1000_hw *hw)
5271 {
5272         uint32_t rctl;
5273
5274         rctl = E1000_READ_REG(hw, RCTL);
5275
5276         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5277
5278         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5279                 | E1000_RCTL_RDMTS_HALF;        /* |
5280                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5281
5282         if (hw->tbi_compatibility_on == 1)
5283                 rctl |= E1000_RCTL_SBP;
5284         else
5285                 rctl &= ~E1000_RCTL_SBP;
5286
5287         rctl &= ~(E1000_RCTL_SZ_4096);
5288                 rctl |= E1000_RCTL_SZ_2048;
5289                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5290         E1000_WRITE_REG(hw, RCTL, rctl);
5291 }
5292
5293 /**
5294  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5295  * @adapter: board private structure
5296  *
5297  * Configure the Rx unit of the MAC after a reset.
5298  **/
5299 static void
5300 e1000_configure_rx(struct e1000_hw *hw)
5301 {
5302         unsigned long rctl, ctrl_ext;
5303         rx_tail = 0;
5304
5305         /* make sure receives are disabled while setting up the descriptors */
5306         rctl = E1000_READ_REG(hw, RCTL);
5307         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5308         if (hw->mac_type >= e1000_82540) {
5309                 /* Set the interrupt throttling rate.  Value is calculated
5310                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5311 #define MAX_INTS_PER_SEC        8000
5312 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
5313                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5314         }
5315
5316         if (hw->mac_type >= e1000_82571) {
5317                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5318                 /* Reset delay timers after every interrupt */
5319                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5320                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5321                 E1000_WRITE_FLUSH(hw);
5322         }
5323         /* Setup the Base and Length of the Rx Descriptor Ring */
5324         E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5325         E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
5326
5327         E1000_WRITE_REG(hw, RDLEN, 128);
5328
5329         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5330         E1000_WRITE_REG(hw, RDH, 0);
5331         E1000_WRITE_REG(hw, RDT, 0);
5332         /* Enable Receives */
5333
5334         if (hw->mac_type == e1000_igb) {
5335
5336                 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5337                 reg_rxdctl |= 1 << 25;
5338                 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5339                 mdelay(20);
5340         }
5341
5342         E1000_WRITE_REG(hw, RCTL, rctl);
5343
5344         fill_rx(hw);
5345 }
5346
5347 /**************************************************************************
5348 POLL - Wait for a frame
5349 ***************************************************************************/
5350 static int
5351 _e1000_poll(struct e1000_hw *hw)
5352 {
5353         struct e1000_rx_desc *rd;
5354         unsigned long inval_start, inval_end;
5355         uint32_t len;
5356
5357         /* return true if there's an ethernet packet ready to read */
5358         rd = rx_base + rx_last;
5359
5360         /* Re-load the descriptor from RAM. */
5361         inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5362         inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5363         invalidate_dcache_range(inval_start, inval_end);
5364
5365         if (!(rd->status & E1000_RXD_STAT_DD))
5366                 return 0;
5367         /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5368         /* Packet received, make sure the data are re-loaded from RAM. */
5369         len = le16_to_cpu(rd->length);
5370         invalidate_dcache_range((unsigned long)packet,
5371                                 (unsigned long)packet +
5372                                 roundup(len, ARCH_DMA_MINALIGN));
5373         return len;
5374 }
5375
5376 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5377 {
5378         void *nv_packet = (void *)txpacket;
5379         struct e1000_tx_desc *txp;
5380         int i = 0;
5381         unsigned long flush_start, flush_end;
5382
5383         txp = tx_base + tx_tail;
5384         tx_tail = (tx_tail + 1) % 8;
5385
5386         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5387         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5388         txp->upper.data = 0;
5389
5390         /* Dump the packet into RAM so e1000 can pick them. */
5391         flush_dcache_range((unsigned long)nv_packet,
5392                            (unsigned long)nv_packet +
5393                            roundup(length, ARCH_DMA_MINALIGN));
5394         /* Dump the descriptor into RAM as well. */
5395         flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5396         flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5397         flush_dcache_range(flush_start, flush_end);
5398
5399         E1000_WRITE_REG(hw, TDT, tx_tail);
5400
5401         E1000_WRITE_FLUSH(hw);
5402         while (1) {
5403                 invalidate_dcache_range(flush_start, flush_end);
5404                 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5405                         break;
5406                 if (i++ > TOUT_LOOP) {
5407                         DEBUGOUT("e1000: tx timeout\n");
5408                         return 0;
5409                 }
5410                 udelay(10);     /* give the nic a chance to write to the register */
5411         }
5412         return 1;
5413 }
5414
5415 static void
5416 _e1000_disable(struct e1000_hw *hw)
5417 {
5418         /* Turn off the ethernet interface */
5419         E1000_WRITE_REG(hw, RCTL, 0);
5420         E1000_WRITE_REG(hw, TCTL, 0);
5421
5422         /* Clear the transmit ring */
5423         E1000_WRITE_REG(hw, TDH, 0);
5424         E1000_WRITE_REG(hw, TDT, 0);
5425
5426         /* Clear the receive ring */
5427         E1000_WRITE_REG(hw, RDH, 0);
5428         E1000_WRITE_REG(hw, RDT, 0);
5429
5430         mdelay(10);
5431 }
5432
5433 /*reset function*/
5434 static inline int
5435 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5436 {
5437         e1000_reset_hw(hw);
5438         if (hw->mac_type >= e1000_82544)
5439                 E1000_WRITE_REG(hw, WUC, 0);
5440
5441         return e1000_init_hw(hw, enetaddr);
5442 }
5443
5444 static int
5445 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5446 {
5447         int ret_val = 0;
5448
5449         ret_val = e1000_reset(hw, enetaddr);
5450         if (ret_val < 0) {
5451                 if ((ret_val == -E1000_ERR_NOLINK) ||
5452                     (ret_val == -E1000_ERR_TIMEOUT)) {
5453                         E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5454                 } else {
5455                         E1000_ERR(hw, "Hardware Initialization Failed\n");
5456                 }
5457                 return ret_val;
5458         }
5459         e1000_configure_tx(hw);
5460         e1000_setup_rctl(hw);
5461         e1000_configure_rx(hw);
5462         return 0;
5463 }
5464
5465 /******************************************************************************
5466  * Gets the current PCI bus type of hardware
5467  *
5468  * hw - Struct containing variables accessed by shared code
5469  *****************************************************************************/
5470 void e1000_get_bus_type(struct e1000_hw *hw)
5471 {
5472         uint32_t status;
5473
5474         switch (hw->mac_type) {
5475         case e1000_82542_rev2_0:
5476         case e1000_82542_rev2_1:
5477                 hw->bus_type = e1000_bus_type_pci;
5478                 break;
5479         case e1000_82571:
5480         case e1000_82572:
5481         case e1000_82573:
5482         case e1000_82574:
5483         case e1000_80003es2lan:
5484         case e1000_ich8lan:
5485         case e1000_igb:
5486                 hw->bus_type = e1000_bus_type_pci_express;
5487                 break;
5488         default:
5489                 status = E1000_READ_REG(hw, STATUS);
5490                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5491                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5492                 break;
5493         }
5494 }
5495
5496 #ifndef CONFIG_DM_ETH
5497 /* A list of all registered e1000 devices */
5498 static LIST_HEAD(e1000_hw_list);
5499 #endif
5500
5501 #ifdef CONFIG_DM_ETH
5502 static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5503                           struct udevice *devno, unsigned char enetaddr[6])
5504 #else
5505 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5506                           unsigned char enetaddr[6])
5507 #endif
5508 {
5509         u32 val;
5510
5511         /* Assign the passed-in values */
5512 #ifdef CONFIG_DM_ETH
5513         hw->pdev = devno;
5514 #else
5515         hw->pdev = devno;
5516 #endif
5517         hw->cardnum = cardnum;
5518
5519         /* Print a debug message with the IO base address */
5520 #ifdef CONFIG_DM_ETH
5521         dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5522 #else
5523         pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5524 #endif
5525         E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5526
5527         /* Try to enable I/O accesses and bus-mastering */
5528         val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5529 #ifdef CONFIG_DM_ETH
5530         dm_pci_write_config32(devno, PCI_COMMAND, val);
5531 #else
5532         pci_write_config_dword(devno, PCI_COMMAND, val);
5533 #endif
5534
5535         /* Make sure it worked */
5536 #ifdef CONFIG_DM_ETH
5537         dm_pci_read_config32(devno, PCI_COMMAND, &val);
5538 #else
5539         pci_read_config_dword(devno, PCI_COMMAND, &val);
5540 #endif
5541         if (!(val & PCI_COMMAND_MEMORY)) {
5542                 E1000_ERR(hw, "Can't enable I/O memory\n");
5543                 return -ENOSPC;
5544         }
5545         if (!(val & PCI_COMMAND_MASTER)) {
5546                 E1000_ERR(hw, "Can't enable bus-mastering\n");
5547                 return -EPERM;
5548         }
5549
5550         /* Are these variables needed? */
5551         hw->fc = e1000_fc_default;
5552         hw->original_fc = e1000_fc_default;
5553         hw->autoneg_failed = 0;
5554         hw->autoneg = 1;
5555         hw->get_link_status = true;
5556 #ifndef CONFIG_E1000_NO_NVM
5557         hw->eeprom_semaphore_present = true;
5558 #endif
5559 #ifdef CONFIG_DM_ETH
5560         hw->hw_addr = dm_pci_map_bar(devno,     PCI_BASE_ADDRESS_0,
5561                                                 PCI_REGION_MEM);
5562 #else
5563         hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5564                                                 PCI_REGION_MEM);
5565 #endif
5566         hw->mac_type = e1000_undefined;
5567
5568         /* MAC and Phy settings */
5569         if (e1000_sw_init(hw) < 0) {
5570                 E1000_ERR(hw, "Software init failed\n");
5571                 return -EIO;
5572         }
5573         if (e1000_check_phy_reset_block(hw))
5574                 E1000_ERR(hw, "PHY Reset is blocked!\n");
5575
5576         /* Basic init was OK, reset the hardware and allow SPI access */
5577         e1000_reset_hw(hw);
5578
5579 #ifndef CONFIG_E1000_NO_NVM
5580         /* Validate the EEPROM and get chipset information */
5581         if (e1000_init_eeprom_params(hw)) {
5582                 E1000_ERR(hw, "EEPROM is invalid!\n");
5583                 return -EINVAL;
5584         }
5585         if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5586             e1000_validate_eeprom_checksum(hw))
5587                 return -ENXIO;
5588         e1000_read_mac_addr(hw, enetaddr);
5589 #endif
5590         e1000_get_bus_type(hw);
5591
5592 #ifndef CONFIG_E1000_NO_NVM
5593         printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5594                enetaddr[0], enetaddr[1], enetaddr[2],
5595                enetaddr[3], enetaddr[4], enetaddr[5]);
5596 #else
5597         memset(enetaddr, 0, 6);
5598         printf("e1000: no NVM\n");
5599 #endif
5600
5601         return 0;
5602 }
5603
5604 /* Put the name of a device in a string */
5605 static void e1000_name(char *str, int cardnum)
5606 {
5607         sprintf(str, "e1000#%u", cardnum);
5608 }
5609
5610 #ifndef CONFIG_DM_ETH
5611 /**************************************************************************
5612 TRANSMIT - Transmit a frame
5613 ***************************************************************************/
5614 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5615 {
5616         struct e1000_hw *hw = nic->priv;
5617
5618         return _e1000_transmit(hw, txpacket, length);
5619 }
5620
5621 /**************************************************************************
5622 DISABLE - Turn off ethernet interface
5623 ***************************************************************************/
5624 static void
5625 e1000_disable(struct eth_device *nic)
5626 {
5627         struct e1000_hw *hw = nic->priv;
5628
5629         _e1000_disable(hw);
5630 }
5631
5632 /**************************************************************************
5633 INIT - set up ethernet interface(s)
5634 ***************************************************************************/
5635 static int
5636 e1000_init(struct eth_device *nic, bd_t *bis)
5637 {
5638         struct e1000_hw *hw = nic->priv;
5639
5640         return _e1000_init(hw, nic->enetaddr);
5641 }
5642
5643 static int
5644 e1000_poll(struct eth_device *nic)
5645 {
5646         struct e1000_hw *hw = nic->priv;
5647         int len;
5648
5649         len = _e1000_poll(hw);
5650         if (len) {
5651                 net_process_received_packet((uchar *)packet, len);
5652                 fill_rx(hw);
5653         }
5654
5655         return len ? 1 : 0;
5656 }
5657
5658 static int e1000_write_hwaddr(struct eth_device *dev)
5659 {
5660 #ifndef CONFIG_E1000_NO_NVM
5661         unsigned char *mac = dev->enetaddr;
5662         unsigned char current_mac[6];
5663         struct e1000_hw *hw = dev->priv;
5664         uint16_t data[3];
5665         int ret_val, i;
5666
5667         DEBUGOUT("%s: mac=%pM\n", __func__, mac);
5668
5669         memset(current_mac, 0, 6);
5670
5671         /* Read from EEPROM, not from registers, to make sure
5672          * the address is persistently configured
5673          */
5674         ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5675         DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
5676
5677         /* Only write to EEPROM if the given address is different or
5678          * reading the current address failed
5679          */
5680         if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5681                 return 0;
5682
5683         for (i = 0; i < 3; ++i)
5684                 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
5685
5686         ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5687
5688         if (!ret_val)
5689                 ret_val = e1000_update_eeprom_checksum_i210(hw);
5690
5691         return ret_val;
5692 #else
5693         return 0;
5694 #endif
5695 }
5696
5697 /**************************************************************************
5698 PROBE - Look for an adapter, this routine's visible to the outside
5699 You should omit the last argument struct pci_device * for a non-PCI NIC
5700 ***************************************************************************/
5701 int
5702 e1000_initialize(bd_t * bis)
5703 {
5704         unsigned int i;
5705         pci_dev_t devno;
5706         int ret;
5707
5708         DEBUGFUNC();
5709
5710         /* Find and probe all the matching PCI devices */
5711         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5712                 /*
5713                  * These will never get freed due to errors, this allows us to
5714                  * perform SPI EEPROM programming from U-Boot, for example.
5715                  */
5716                 struct eth_device *nic = malloc(sizeof(*nic));
5717                 struct e1000_hw *hw = malloc(sizeof(*hw));
5718                 if (!nic || !hw) {
5719                         printf("e1000#%u: Out of Memory!\n", i);
5720                         free(nic);
5721                         free(hw);
5722                         continue;
5723                 }
5724
5725                 /* Make sure all of the fields are initially zeroed */
5726                 memset(nic, 0, sizeof(*nic));
5727                 memset(hw, 0, sizeof(*hw));
5728                 nic->priv = hw;
5729
5730                 /* Generate a card name */
5731                 e1000_name(nic->name, i);
5732                 hw->name = nic->name;
5733
5734                 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5735                 if (ret)
5736                         continue;
5737                 list_add_tail(&hw->list_node, &e1000_hw_list);
5738
5739                 hw->nic = nic;
5740
5741                 /* Set up the function pointers and register the device */
5742                 nic->init = e1000_init;
5743                 nic->recv = e1000_poll;
5744                 nic->send = e1000_transmit;
5745                 nic->halt = e1000_disable;
5746                 nic->write_hwaddr = e1000_write_hwaddr;
5747                 eth_register(nic);
5748         }
5749
5750         return i;
5751 }
5752
5753 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5754 {
5755         struct e1000_hw *hw;
5756
5757         list_for_each_entry(hw, &e1000_hw_list, list_node)
5758                 if (hw->cardnum == cardnum)
5759                         return hw;
5760
5761         return NULL;
5762 }
5763 #endif /* !CONFIG_DM_ETH */
5764
5765 #ifdef CONFIG_CMD_E1000
5766 static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
5767                     char *const argv[])
5768 {
5769         unsigned char *mac = NULL;
5770 #ifdef CONFIG_DM_ETH
5771         struct eth_pdata *plat;
5772         struct udevice *dev;
5773         char name[30];
5774         int ret;
5775 #endif
5776 #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
5777         struct e1000_hw *hw;
5778 #endif
5779         int cardnum;
5780
5781         if (argc < 3) {
5782                 cmd_usage(cmdtp);
5783                 return 1;
5784         }
5785
5786         /* Make sure we can find the requested e1000 card */
5787         cardnum = simple_strtoul(argv[1], NULL, 10);
5788 #ifdef CONFIG_DM_ETH
5789         e1000_name(name, cardnum);
5790         ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5791         if (!ret) {
5792                 plat = dev_get_platdata(dev);
5793                 mac = plat->enetaddr;
5794         }
5795 #else
5796         hw = e1000_find_card(cardnum);
5797         if (hw)
5798                 mac = hw->nic->enetaddr;
5799 #endif
5800         if (!mac) {
5801                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5802                 return 1;
5803         }
5804
5805         if (!strcmp(argv[2], "print-mac-address")) {
5806                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5807                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5808                 return 0;
5809         }
5810
5811 #ifdef CONFIG_E1000_SPI
5812 #ifdef CONFIG_DM_ETH
5813         hw = dev_get_priv(dev);
5814 #endif
5815         /* Handle the "SPI" subcommand */
5816         if (!strcmp(argv[2], "spi"))
5817                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5818 #endif
5819
5820         cmd_usage(cmdtp);
5821         return 1;
5822 }
5823
5824 U_BOOT_CMD(
5825         e1000, 7, 0, do_e1000,
5826         "Intel e1000 controller management",
5827         /*  */"<card#> print-mac-address\n"
5828 #ifdef CONFIG_E1000_SPI
5829         "e1000 <card#> spi show [<offset> [<length>]]\n"
5830         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5831         "e1000 <card#> spi program <addr> <offset> <length>\n"
5832         "e1000 <card#> spi checksum [update]\n"
5833 #endif
5834         "       - Manage the Intel E1000 PCI device"
5835 );
5836 #endif /* not CONFIG_CMD_E1000 */
5837
5838 #ifdef CONFIG_DM_ETH
5839 static int e1000_eth_start(struct udevice *dev)
5840 {
5841         struct eth_pdata *plat = dev_get_platdata(dev);
5842         struct e1000_hw *hw = dev_get_priv(dev);
5843
5844         return _e1000_init(hw, plat->enetaddr);
5845 }
5846
5847 static void e1000_eth_stop(struct udevice *dev)
5848 {
5849         struct e1000_hw *hw = dev_get_priv(dev);
5850
5851         _e1000_disable(hw);
5852 }
5853
5854 static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5855 {
5856         struct e1000_hw *hw = dev_get_priv(dev);
5857         int ret;
5858
5859         ret = _e1000_transmit(hw, packet, length);
5860
5861         return ret ? 0 : -ETIMEDOUT;
5862 }
5863
5864 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5865 {
5866         struct e1000_hw *hw = dev_get_priv(dev);
5867         int len;
5868
5869         len = _e1000_poll(hw);
5870         if (len)
5871                 *packetp = packet;
5872
5873         return len ? len : -EAGAIN;
5874 }
5875
5876 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5877 {
5878         struct e1000_hw *hw = dev_get_priv(dev);
5879
5880         fill_rx(hw);
5881
5882         return 0;
5883 }
5884
5885 static int e1000_eth_probe(struct udevice *dev)
5886 {
5887         struct eth_pdata *plat = dev_get_platdata(dev);
5888         struct e1000_hw *hw = dev_get_priv(dev);
5889         int ret;
5890
5891         hw->name = dev->name;
5892         ret = e1000_init_one(hw, trailing_strtol(dev->name),
5893                              dev, plat->enetaddr);
5894         if (ret < 0) {
5895                 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5896                 return ret;
5897         }
5898
5899         return 0;
5900 }
5901
5902 static int e1000_eth_bind(struct udevice *dev)
5903 {
5904         char name[20];
5905
5906         /*
5907          * A simple way to number the devices. When device tree is used this
5908          * is unnecessary, but when the device is just discovered on the PCI
5909          * bus we need a name. We could instead have the uclass figure out
5910          * which devices are different and number them.
5911          */
5912         e1000_name(name, num_cards++);
5913
5914         return device_set_name(dev, name);
5915 }
5916
5917 static const struct eth_ops e1000_eth_ops = {
5918         .start  = e1000_eth_start,
5919         .send   = e1000_eth_send,
5920         .recv   = e1000_eth_recv,
5921         .stop   = e1000_eth_stop,
5922         .free_pkt = e1000_free_pkt,
5923 };
5924
5925 static const struct udevice_id e1000_eth_ids[] = {
5926         { .compatible = "intel,e1000" },
5927         { }
5928 };
5929
5930 U_BOOT_DRIVER(eth_e1000) = {
5931         .name   = "eth_e1000",
5932         .id     = UCLASS_ETH,
5933         .of_match = e1000_eth_ids,
5934         .bind   = e1000_eth_bind,
5935         .probe  = e1000_eth_probe,
5936         .ops    = &e1000_eth_ops,
5937         .priv_auto_alloc_size = sizeof(struct e1000_hw),
5938         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5939 };
5940
5941 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5942 #endif