drivers/net/bcmgenet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com>
   4  *
   5  * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4)
   6  * This driver is based on the Linux driver:
   7  *      drivers/net/ethernet/broadcom/genet/bcmgenet.c
   8  *      which is: Copyright (c) 2014-2017 Broadcom
   9  *
  10  * The hardware supports multiple queues (16 priority queues and one
  11  * default queue), both for RX and TX. There are 256 DMA descriptors (both
  12  * for TX and RX), and they live in MMIO registers. The hardware allows
  13  * assigning descriptor ranges to queues, but we choose the most simple setup:
  14  * All 256 descriptors are assigned to the default queue (#16).
  15  * Also the Linux driver supports multiple generations of the MAC, whereas
  16  * we only support v5, as used in the Raspberry Pi 4.
  17  */
  18
  19 #include <log.h>
  20 #include <asm/cache.h>
  21 #include <asm/io.h>
  22 #include <clk.h>
  23 #include <cpu_func.h>
  24 #include <dm.h>
  25 #include <fdt_support.h>
  26 #include <linux/delay.h>
  27 #include <linux/err.h>
  28 #include <malloc.h>
  29 #include <miiphy.h>
  30 #include <net.h>
  31 #include <dm/of_access.h>
  32 #include <dm/ofnode.h>
  33 #include <linux/iopoll.h>
  34 #include <linux/sizes.h>
  35 #include <asm/dma-mapping.h>
  36 #include <wait_bit.h>
  37
  38 /* Register definitions derived from Linux source */
  39 #define SYS_REV_CTRL                    0x00
  40
  41 #define SYS_PORT_CTRL                   0x04
  42 #define PORT_MODE_EXT_GPHY              3
  43
  44 #define GENET_SYS_OFF                   0x0000
  45 #define SYS_RBUF_FLUSH_CTRL             (GENET_SYS_OFF  + 0x08)
  46 #define SYS_TBUF_FLUSH_CTRL             (GENET_SYS_OFF  + 0x0c)
  47
  48 #define GENET_EXT_OFF                   0x0080
  49 #define EXT_RGMII_OOB_CTRL              (GENET_EXT_OFF + 0x0c)
  50 #define RGMII_LINK                      BIT(4)
  51 #define OOB_DISABLE                     BIT(5)
  52 #define RGMII_MODE_EN                   BIT(6)
  53 #define ID_MODE_DIS                     BIT(16)
  54
  55 #define GENET_RBUF_OFF                  0x0300
  56 #define RBUF_TBUF_SIZE_CTRL             (GENET_RBUF_OFF + 0xb4)
  57 #define RBUF_CTRL                       (GENET_RBUF_OFF + 0x00)
  58 #define RBUF_ALIGN_2B                   BIT(1)
  59
  60 #define GENET_UMAC_OFF                  0x0800
  61 #define UMAC_MIB_CTRL                   (GENET_UMAC_OFF + 0x580)
  62 #define UMAC_MAX_FRAME_LEN              (GENET_UMAC_OFF + 0x014)
  63 #define UMAC_MAC0                       (GENET_UMAC_OFF + 0x00c)
  64 #define UMAC_MAC1                       (GENET_UMAC_OFF + 0x010)
  65 #define UMAC_CMD                        (GENET_UMAC_OFF + 0x008)
  66 #define MDIO_CMD                        (GENET_UMAC_OFF + 0x614)
  67 #define UMAC_TX_FLUSH                   (GENET_UMAC_OFF + 0x334)
  68 #define MDIO_START_BUSY                 BIT(29)
  69 #define MDIO_READ_FAIL                  BIT(28)
  70 #define MDIO_RD                         (2 << 26)
  71 #define MDIO_WR                         BIT(26)
  72 #define MDIO_PMD_SHIFT                  21
  73 #define MDIO_PMD_MASK                   0x1f
  74 #define MDIO_REG_SHIFT                  16
  75 #define MDIO_REG_MASK                   0x1f
  76
  77 #define CMD_TX_EN                       BIT(0)
  78 #define CMD_RX_EN                       BIT(1)
  79 #define UMAC_SPEED_10                   0
  80 #define UMAC_SPEED_100                  1
  81 #define UMAC_SPEED_1000                 2
  82 #define UMAC_SPEED_2500                 3
  83 #define CMD_SPEED_SHIFT                 2
  84 #define CMD_SPEED_MASK                  3
  85 #define CMD_SW_RESET                    BIT(13)
  86 #define CMD_LCL_LOOP_EN                 BIT(15)
  87 #define CMD_TX_EN                       BIT(0)
  88 #define CMD_RX_EN                       BIT(1)
  89
  90 #define MIB_RESET_RX                    BIT(0)
  91 #define MIB_RESET_RUNT                  BIT(1)
  92 #define MIB_RESET_TX                    BIT(2)
  93
  94 /* total number of Buffer Descriptors, same for Rx/Tx */
  95 #define TOTAL_DESCS                     256
  96 #define RX_DESCS                        TOTAL_DESCS
  97 #define TX_DESCS                        TOTAL_DESCS
  98
  99 #define DEFAULT_Q                       0x10
 100
 101 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
 102  * 1536 is multiple of 256 bytes
 103  */
 104 #define ENET_BRCM_TAG_LEN               6
 105 #define ENET_PAD                        8
 106 #define ENET_MAX_MTU_SIZE               (ETH_DATA_LEN + ETH_HLEN +       \
 107                                          VLAN_HLEN + ENET_BRCM_TAG_LEN + \
 108                                          ETH_FCS_LEN + ENET_PAD)
 109
 110 /* Tx/Rx Dma Descriptor common bits */
 111 #define DMA_EN                          BIT(0)
 112 #define DMA_RING_BUF_EN_SHIFT           0x01
 113 #define DMA_RING_BUF_EN_MASK            0xffff
 114 #define DMA_BUFLENGTH_MASK              0x0fff
 115 #define DMA_BUFLENGTH_SHIFT             16
 116 #define DMA_RING_SIZE_SHIFT             16
 117 #define DMA_OWN                         0x8000
 118 #define DMA_EOP                         0x4000
 119 #define DMA_SOP                         0x2000
 120 #define DMA_WRAP                        0x1000
 121 #define DMA_MAX_BURST_LENGTH            0x8
 122 /* Tx specific DMA descriptor bits */
 123 #define DMA_TX_UNDERRUN                 0x0200
 124 #define DMA_TX_APPEND_CRC               0x0040
 125 #define DMA_TX_OW_CRC                   0x0020
 126 #define DMA_TX_DO_CSUM                  0x0010
 127 #define DMA_TX_QTAG_SHIFT               7
 128
 129 /* DMA rings size */
 130 #define DMA_RING_SIZE                   0x40
 131 #define DMA_RINGS_SIZE                  (DMA_RING_SIZE * (DEFAULT_Q + 1))
 132
 133 /* DMA descriptor */
 134 #define DMA_DESC_LENGTH_STATUS          0x00
 135 #define DMA_DESC_ADDRESS_LO             0x04
 136 #define DMA_DESC_ADDRESS_HI             0x08
 137 #define DMA_DESC_SIZE                   12
 138
 139 #define GENET_RX_OFF                    0x2000
 140 #define GENET_RDMA_REG_OFF                                      \
 141         (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
 142 #define GENET_TX_OFF                    0x4000
 143 #define GENET_TDMA_REG_OFF                                      \
 144         (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
 145
 146 #define DMA_FC_THRESH_HI                (RX_DESCS >> 4)
 147 #define DMA_FC_THRESH_LO                5
 148 #define DMA_FC_THRESH_VALUE             ((DMA_FC_THRESH_LO << 16) |     \
 149                                           DMA_FC_THRESH_HI)
 150
 151 #define DMA_XOFF_THRESHOLD_SHIFT        16
 152
 153 #define TDMA_RING_REG_BASE                                      \
 154         (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
 155 #define TDMA_READ_PTR                   (TDMA_RING_REG_BASE + 0x00)
 156 #define TDMA_CONS_INDEX                 (TDMA_RING_REG_BASE + 0x08)
 157 #define TDMA_PROD_INDEX                 (TDMA_RING_REG_BASE + 0x0c)
 158 #define DMA_RING_BUF_SIZE               0x10
 159 #define DMA_START_ADDR                  0x14
 160 #define DMA_END_ADDR                    0x1c
 161 #define DMA_MBUF_DONE_THRESH            0x24
 162 #define TDMA_FLOW_PERIOD                (TDMA_RING_REG_BASE + 0x28)
 163 #define TDMA_WRITE_PTR                  (TDMA_RING_REG_BASE + 0x2c)
 164
 165 #define RDMA_RING_REG_BASE                                      \
 166         (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
 167 #define RDMA_WRITE_PTR                  (RDMA_RING_REG_BASE + 0x00)
 168 #define RDMA_PROD_INDEX                 (RDMA_RING_REG_BASE + 0x08)
 169 #define RDMA_CONS_INDEX                 (RDMA_RING_REG_BASE + 0x0c)
 170 #define RDMA_XON_XOFF_THRESH            (RDMA_RING_REG_BASE + 0x28)
 171 #define RDMA_READ_PTR                   (RDMA_RING_REG_BASE + 0x2c)
 172
 173 #define TDMA_REG_BASE                   (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
 174 #define RDMA_REG_BASE                   (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
 175 #define DMA_RING_CFG                    0x00
 176 #define DMA_CTRL                        0x04
 177 #define DMA_SCB_BURST_SIZE              0x0c
 178
 179 #define RX_BUF_LENGTH                   2048
 180 #define RX_TOTAL_BUFSIZE                (RX_BUF_LENGTH * RX_DESCS)
 181 #define RX_BUF_OFFSET                   2
 182
 183 struct bcmgenet_eth_priv {
 184         char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 185         void *mac_reg;
 186         void *tx_desc_base;
 187         void *rx_desc_base;
 188         int tx_index;
 189         int rx_index;
 190         int c_index;
 191         int phyaddr;
 192         u32 interface;
 193         u32 speed;
 194         struct phy_device *phydev;
 195         struct mii_dev *bus;
 196 };
 197
 198 static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv)
 199 {
 200         u32 reg;
 201
 202         reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
 203         reg |= BIT(1);
 204         writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
 205         udelay(10);
 206
 207         reg &= ~BIT(1);
 208         writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
 209         udelay(10);
 210
 211         writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
 212         udelay(10);
 213
 214         writel(0, priv->mac_reg + UMAC_CMD);
 215
 216         writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
 217         udelay(2);
 218         writel(0, priv->mac_reg + UMAC_CMD);
 219
 220         /* clear tx/rx counter */
 221         writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
 222                priv->mac_reg + UMAC_MIB_CTRL);
 223         writel(0, priv->mac_reg + UMAC_MIB_CTRL);
 224
 225         writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN);
 226
 227         /* init rx registers, enable ip header optimization */
 228         reg = readl(priv->mac_reg + RBUF_CTRL);
 229         reg |= RBUF_ALIGN_2B;
 230         writel(reg, (priv->mac_reg + RBUF_CTRL));
 231
 232         writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL));
 233 }
 234
 235 static int bcmgenet_gmac_write_hwaddr(struct udevice *dev)
 236 {
 237         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 238         struct eth_pdata *pdata = dev_get_platdata(dev);
 239         uchar *addr = pdata->enetaddr;
 240         u32 reg;
 241
 242         reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
 243         writel_relaxed(reg, priv->mac_reg + UMAC_MAC0);
 244
 245         reg = addr[4] << 8 | addr[5];
 246         writel_relaxed(reg, priv->mac_reg + UMAC_MAC1);
 247
 248         return 0;
 249 }
 250
 251 static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv)
 252 {
 253         clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN);
 254         clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN);
 255
 256         writel(1, priv->mac_reg + UMAC_TX_FLUSH);
 257         udelay(10);
 258         writel(0, priv->mac_reg + UMAC_TX_FLUSH);
 259 }
 260
 261 static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv)
 262 {
 263         u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
 264
 265         writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL);
 266
 267         setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl);
 268 }
 269
 270 static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length)
 271 {
 272         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 273         void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE;
 274         u32 len_stat = length << DMA_BUFLENGTH_SHIFT;
 275         ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN);
 276         u32 prod_index, cons;
 277         u32 tries = 100;
 278
 279         prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX);
 280
 281         /* There is actually no reason for the rounding here, but the ARMv7
 282          * implementation of flush_dcache_range() checks for aligned
 283          * boundaries of the flushed range.
 284          * Adjust them here to pass that check and avoid misleading messages.
 285          */
 286         flush_dcache_range(packet_aligned,
 287                            packet_aligned + roundup(length, ARCH_DMA_MINALIGN));
 288
 289         len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
 290         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
 291
 292         /* Set-up packet for transmission */
 293         writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO));
 294         writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI));
 295         writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS));
 296
 297         /* Increment index and start transmission */
 298         if (++priv->tx_index >= TX_DESCS)
 299                 priv->tx_index = 0;
 300
 301         prod_index++;
 302
 303         /* Start Transmisson */
 304         writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX);
 305
 306         do {
 307                 cons = readl(priv->mac_reg + TDMA_CONS_INDEX);
 308         } while ((cons & 0xffff) < prod_index && --tries);
 309         if (!tries)
 310                 return -ETIMEDOUT;
 311
 312         return 0;
 313 }
 314
 315 /* Check whether all cache lines affected by an invalidate are within
 316  * the buffer, to make sure we don't accidentally lose unrelated dirty
 317  * data stored nearby.
 318  * Alignment of the buffer start address will be checked in the implementation
 319  * of invalidate_dcache_range().
 320  */
 321 static void invalidate_dcache_check(unsigned long addr, size_t size,
 322                                     size_t buffer_size)
 323 {
 324         size_t inval_size = roundup(size, ARCH_DMA_MINALIGN);
 325
 326         if (unlikely(inval_size > buffer_size))
 327                 printf("WARNING: Cache invalidate area exceeds buffer size\n");
 328
 329         invalidate_dcache_range(addr, addr + inval_size);
 330 }
 331
 332 static int bcmgenet_gmac_eth_recv(struct udevice *dev,
 333                                   int flags, uchar **packetp)
 334 {
 335         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 336         void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE;
 337         u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
 338         u32 length, addr;
 339
 340         if (prod_index == priv->c_index)
 341                 return -EAGAIN;
 342
 343         length = readl(desc_base + DMA_DESC_LENGTH_STATUS);
 344         length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
 345         addr = readl(desc_base + DMA_DESC_ADDRESS_LO);
 346
 347         invalidate_dcache_check(addr, length, RX_BUF_LENGTH);
 348
 349         /* To cater for the IP header alignment the hardware does.
 350          * This would actually not be needed if we don't program
 351          * RBUF_ALIGN_2B
 352          */
 353         *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET;
 354
 355         return length - RX_BUF_OFFSET;
 356 }
 357
 358 static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet,
 359                                   int length)
 360 {
 361         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 362
 363         /* Tell the MAC we have consumed that last receive buffer. */
 364         priv->c_index = (priv->c_index + 1) & 0xFFFF;
 365         writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
 366
 367         /* Forward our descriptor pointer, wrapping around if needed. */
 368         if (++priv->rx_index >= RX_DESCS)
 369                 priv->rx_index = 0;
 370
 371         return 0;
 372 }
 373
 374 static void rx_descs_init(struct bcmgenet_eth_priv *priv)
 375 {
 376         char *rxbuffs = &priv->rxbuffer[0];
 377         u32 len_stat, i;
 378         void *desc_base = priv->rx_desc_base;
 379
 380         priv->c_index = 0;
 381
 382         len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
 383
 384         for (i = 0; i < RX_DESCS; i++) {
 385                 writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
 386                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO);
 387                 writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
 388                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI);
 389                 writel(len_stat,
 390                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS);
 391         }
 392 }
 393
 394 static void rx_ring_init(struct bcmgenet_eth_priv *priv)
 395 {
 396         writel(DMA_MAX_BURST_LENGTH,
 397                priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE);
 398
 399         writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR);
 400         writel(0x0, priv->mac_reg + RDMA_READ_PTR);
 401         writel(0x0, priv->mac_reg + RDMA_WRITE_PTR);
 402         writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1,
 403                priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR);
 404
 405         writel(0x0, priv->mac_reg + RDMA_PROD_INDEX);
 406         writel(0x0, priv->mac_reg + RDMA_CONS_INDEX);
 407         writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
 408                priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
 409         writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH);
 410         writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG);
 411 }
 412
 413 static void tx_ring_init(struct bcmgenet_eth_priv *priv)
 414 {
 415         writel(DMA_MAX_BURST_LENGTH,
 416                priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE);
 417
 418         writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR);
 419         writel(0x0, priv->mac_reg + TDMA_READ_PTR);
 420         writel(0x0, priv->mac_reg + TDMA_WRITE_PTR);
 421         writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1,
 422                priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR);
 423         writel(0x0, priv->mac_reg + TDMA_PROD_INDEX);
 424         writel(0x0, priv->mac_reg + TDMA_CONS_INDEX);
 425         writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH);
 426         writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD);
 427         writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
 428                priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
 429
 430         writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG);
 431 }
 432
 433 static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv)
 434 {
 435         struct phy_device *phy_dev = priv->phydev;
 436         u32 speed;
 437
 438         switch (phy_dev->speed) {
 439         case SPEED_1000:
 440                 speed = UMAC_SPEED_1000;
 441                 break;
 442         case SPEED_100:
 443                 speed = UMAC_SPEED_100;
 444                 break;
 445         case SPEED_10:
 446                 speed = UMAC_SPEED_10;
 447                 break;
 448         default:
 449                 printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed);
 450                 return -EINVAL;
 451         }
 452
 453         clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
 454                         RGMII_LINK | RGMII_MODE_EN);
 455
 456         if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII)
 457                 setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS);
 458
 459         writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
 460
 461         return 0;
 462 }
 463
 464 static int bcmgenet_gmac_eth_start(struct udevice *dev)
 465 {
 466         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 467         int ret;
 468
 469         priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF;
 470         priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF;
 471         priv->tx_index = 0x0;
 472         priv->rx_index = 0x0;
 473
 474         bcmgenet_umac_reset(priv);
 475
 476         bcmgenet_gmac_write_hwaddr(dev);
 477
 478         /* Disable RX/TX DMA and flush TX queues */
 479         bcmgenet_disable_dma(priv);
 480
 481         rx_ring_init(priv);
 482         rx_descs_init(priv);
 483
 484         tx_ring_init(priv);
 485
 486         /* Enable RX/TX DMA */
 487         bcmgenet_enable_dma(priv);
 488
 489         /* read PHY properties over the wire from generic PHY set-up */
 490         ret = phy_startup(priv->phydev);
 491         if (ret) {
 492                 printf("bcmgenet: PHY startup failed: %d\n", ret);
 493                 return ret;
 494         }
 495
 496         /* Update MAC registers based on PHY property */
 497         ret = bcmgenet_adjust_link(priv);
 498         if (ret) {
 499                 printf("bcmgenet: adjust PHY link failed: %d\n", ret);
 500                 return ret;
 501         }
 502
 503         /* Enable Rx/Tx */
 504         setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
 505
 506         return 0;
 507 }
 508
 509 static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev)
 510 {
 511         struct phy_device *phydev;
 512         int ret;
 513
 514         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
 515         if (!phydev)
 516                 return -ENODEV;
 517
 518         phydev->supported &= PHY_GBIT_FEATURES;
 519         if (priv->speed) {
 520                 ret = phy_set_supported(priv->phydev, priv->speed);
 521                 if (ret)
 522                         return ret;
 523         }
 524         phydev->advertising = phydev->supported;
 525
 526         phy_connect_dev(phydev, dev);
 527
 528         priv->phydev = phydev;
 529         phy_config(priv->phydev);
 530
 531         return 0;
 532 }
 533
 534 static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv)
 535 {
 536         setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY);
 537 }
 538
 539 static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad,
 540                                int reg, u16 value)
 541 {
 542         struct udevice *dev = bus->priv;
 543         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 544         u32 val;
 545
 546         /* Prepare the read operation */
 547         val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |
 548                 (reg << MDIO_REG_SHIFT) | (0xffff & value);
 549         writel_relaxed(val,  priv->mac_reg + MDIO_CMD);
 550
 551         /* Start MDIO transaction */
 552         bcmgenet_mdio_start(priv);
 553
 554         return wait_for_bit_32(priv->mac_reg + MDIO_CMD,
 555                                MDIO_START_BUSY, false, 20, true);
 556 }
 557
 558 static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 559 {
 560         struct udevice *dev = bus->priv;
 561         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 562         u32 val;
 563         int ret;
 564
 565         /* Prepare the read operation */
 566         val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
 567         writel_relaxed(val, priv->mac_reg + MDIO_CMD);
 568
 569         /* Start MDIO transaction */
 570         bcmgenet_mdio_start(priv);
 571
 572         ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD,
 573                               MDIO_START_BUSY, false, 20, true);
 574         if (ret)
 575                 return ret;
 576
 577         val = readl_relaxed(priv->mac_reg + MDIO_CMD);
 578
 579         return val & 0xffff;
 580 }
 581
 582 static int bcmgenet_mdio_init(const char *name, struct udevice *priv)
 583 {
 584         struct mii_dev *bus = mdio_alloc();
 585
 586         if (!bus) {
 587                 debug("Failed to allocate MDIO bus\n");
 588                 return -ENOMEM;
 589         }
 590
 591         bus->read = bcmgenet_mdio_read;
 592         bus->write = bcmgenet_mdio_write;
 593         snprintf(bus->name, sizeof(bus->name), name);
 594         bus->priv = (void *)priv;
 595
 596         return mdio_register(bus);
 597 }
 598
 599 /* We only support RGMII (as used on the RPi4). */
 600 static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv)
 601 {
 602         phy_interface_t phy_mode = priv->interface;
 603
 604         switch (phy_mode) {
 605         case PHY_INTERFACE_MODE_RGMII:
 606         case PHY_INTERFACE_MODE_RGMII_RXID:
 607                 writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL);
 608                 break;
 609         default:
 610                 printf("unknown phy mode: %d\n", priv->interface);
 611                 return -EINVAL;
 612         }
 613
 614         return 0;
 615 }
 616
 617 static int bcmgenet_eth_probe(struct udevice *dev)
 618 {
 619         struct eth_pdata *pdata = dev_get_platdata(dev);
 620         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 621         ofnode mdio_node;
 622         const char *name;
 623         u32 reg;
 624         int ret;
 625         u8 major;
 626
 627         priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE);
 628         priv->interface = pdata->phy_interface;
 629         priv->speed = pdata->max_speed;
 630
 631         /* Read GENET HW version */
 632         reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL);
 633         major = (reg >> 24) & 0x0f;
 634         if (major != 6) {
 635                 if (major == 5)
 636                         major = 4;
 637                 else if (major == 0)
 638                         major = 1;
 639
 640                 printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f);
 641                 return -ENODEV;
 642         }
 643
 644         ret = bcmgenet_interface_set(priv);
 645         if (ret)
 646                 return ret;
 647
 648         writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
 649         udelay(10);
 650         /* disable MAC while updating its registers */
 651         writel(0, priv->mac_reg + UMAC_CMD);
 652         /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
 653         writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
 654
 655         mdio_node = dev_read_first_subnode(dev);
 656         name = ofnode_get_name(mdio_node);
 657
 658         ret = bcmgenet_mdio_init(name, dev);
 659         if (ret)
 660                 return ret;
 661
 662         priv->bus = miiphy_get_dev_by_name(name);
 663
 664         return bcmgenet_phy_init(priv, dev);
 665 }
 666
 667 static void bcmgenet_gmac_eth_stop(struct udevice *dev)
 668 {
 669         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 670
 671         clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
 672
 673         bcmgenet_disable_dma(priv);
 674 }
 675
 676 static const struct eth_ops bcmgenet_gmac_eth_ops = {
 677         .start                  = bcmgenet_gmac_eth_start,
 678         .write_hwaddr           = bcmgenet_gmac_write_hwaddr,
 679         .send                   = bcmgenet_gmac_eth_send,
 680         .recv                   = bcmgenet_gmac_eth_recv,
 681         .free_pkt               = bcmgenet_gmac_free_pkt,
 682         .stop                   = bcmgenet_gmac_eth_stop,
 683 };
 684
 685 static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev)
 686 {
 687         struct eth_pdata *pdata = dev_get_platdata(dev);
 688         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 689         struct ofnode_phandle_args phy_node;
 690         const char *phy_mode;
 691         int ret;
 692
 693         pdata->iobase = dev_read_addr(dev);
 694
 695         /* Get phy mode from DT */
 696         pdata->phy_interface = -1;
 697         phy_mode = dev_read_string(dev, "phy-mode");
 698         if (phy_mode)
 699                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 700         if (pdata->phy_interface == -1) {
 701                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 702                 return -EINVAL;
 703         }
 704
 705         ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
 706                                          &phy_node);
 707         if (!ret) {
 708                 ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr);
 709                 ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed);
 710         }
 711
 712         return 0;
 713 }
 714
 715 /* The BCM2711 implementation has a limited burst length compared to a generic
 716  * GENETv5 version, but we go with that shorter value (8) in both cases, for
 717  * the sake of simplicity.
 718  */
 719 static const struct udevice_id bcmgenet_eth_ids[] = {
 720         {.compatible = "brcm,genet-v5"},
 721         {.compatible = "brcm,bcm2711-genet-v5"},
 722         {}
 723 };
 724
 725 U_BOOT_DRIVER(eth_bcmgenet) = {
 726         .name   = "eth_bcmgenet",
 727         .id     = UCLASS_ETH,
 728         .of_match = bcmgenet_eth_ids,
 729         .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata,
 730         .probe  = bcmgenet_eth_probe,
 731         .ops    = &bcmgenet_gmac_eth_ops,
 732         .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv),
 733         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 734         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 735 };