1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/sizes.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/spi-nor.h>
24 #include "sf_internal.h"
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
33 #define HZ CONFIG_SYS_HZ
35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
40 if (op->data.dir == SPI_MEM_DATA_IN)
41 op->data.buf.in = buf;
43 op->data.buf.out = buf;
44 return spi_mem_exec_op(nor->spi, op);
47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
52 SPI_MEM_OP_DATA_IN(len, NULL, 1));
55 ret = spi_nor_read_write_reg(nor, &op, val);
57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
68 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
70 return spi_nor_read_write_reg(nor, &op, buf);
73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
76 struct spi_mem_op op =
77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
80 SPI_MEM_OP_DATA_IN(len, buf, 1));
81 size_t remaining = len;
84 /* get transfer protocols. */
85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
87 op.dummy.buswidth = op.addr.buswidth;
88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
90 /* convert the dummy cycles to the number of bytes */
91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
95 ret = spi_mem_adjust_op_size(nor->spi, &op);
99 ret = spi_mem_exec_op(nor->spi, &op);
103 op.addr.val += op.data.nbytes;
104 remaining -= op.data.nbytes;
105 op.data.buf.in += op.data.nbytes;
111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
114 struct spi_mem_op op =
115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
118 SPI_MEM_OP_DATA_OUT(len, buf, 1));
119 size_t remaining = len;
122 /* get transfer protocols. */
123 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
124 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
125 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
127 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
131 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
132 ret = spi_mem_adjust_op_size(nor->spi, &op);
136 ret = spi_mem_exec_op(nor->spi, &op);
140 op.addr.val += op.data.nbytes;
141 remaining -= op.data.nbytes;
142 op.data.buf.out += op.data.nbytes;
149 * Read the status register, returning its value in the location
150 * Return the status register value.
151 * Returns negative if error occurred.
153 static int read_sr(struct spi_nor *nor)
158 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
160 pr_debug("error %d reading SR\n", (int)ret);
168 * Read the flag status register, returning its value in the location
169 * Return the status register value.
170 * Returns negative if error occurred.
172 static int read_fsr(struct spi_nor *nor)
177 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
179 pr_debug("error %d reading FSR\n", ret);
187 * Read configuration register, returning its value in the
188 * location. Return the configuration register value.
189 * Returns negative if error occurred.
191 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
192 static int read_cr(struct spi_nor *nor)
197 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
199 dev_dbg(nor->dev, "error %d reading CR\n", ret);
208 * Write status register 1 byte
209 * Returns negative if error occurred.
211 static int write_sr(struct spi_nor *nor, u8 val)
213 nor->cmd_buf[0] = val;
214 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
218 * Set write enable latch with Write Enable command.
219 * Returns negative if error occurred.
221 static int write_enable(struct spi_nor *nor)
223 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
227 * Send write disable instruction to the chip.
229 static int write_disable(struct spi_nor *nor)
231 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
234 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
239 #ifndef CONFIG_SPI_FLASH_BAR
240 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
244 for (i = 0; i < size; i++)
245 if (table[i][0] == opcode)
248 /* No conversion found, keep input op code. */
252 static u8 spi_nor_convert_3to4_read(u8 opcode)
254 static const u8 spi_nor_3to4_read[][2] = {
255 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
256 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
257 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
258 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
259 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
260 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
262 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
263 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
264 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
267 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
268 ARRAY_SIZE(spi_nor_3to4_read));
271 static u8 spi_nor_convert_3to4_program(u8 opcode)
273 static const u8 spi_nor_3to4_program[][2] = {
274 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
275 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
276 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
279 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
280 ARRAY_SIZE(spi_nor_3to4_program));
283 static u8 spi_nor_convert_3to4_erase(u8 opcode)
285 static const u8 spi_nor_3to4_erase[][2] = {
286 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
287 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
288 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
291 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
292 ARRAY_SIZE(spi_nor_3to4_erase));
295 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
296 const struct flash_info *info)
298 /* Do some manufacturer fixups first */
299 switch (JEDEC_MFR(info)) {
300 case SNOR_MFR_SPANSION:
301 /* No small sector erase for 4-byte command set */
302 nor->erase_opcode = SPINOR_OP_SE;
303 nor->mtd.erasesize = info->sector_size;
310 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
311 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
312 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
314 #endif /* !CONFIG_SPI_FLASH_BAR */
316 /* Enable/disable 4-byte addressing mode. */
317 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
321 bool need_wren = false;
324 switch (JEDEC_MFR(info)) {
326 case SNOR_MFR_MICRON:
327 /* Some Micron need WREN command; all will accept it */
329 case SNOR_MFR_MACRONIX:
330 case SNOR_MFR_WINBOND:
334 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
335 status = nor->write_reg(nor, cmd, NULL, 0);
339 if (!status && !enable &&
340 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
342 * On Winbond W25Q256FV, leaving 4byte mode causes
343 * the Extended Address Register to be set to 1, so all
344 * 3-byte-address reads come from the second 16M.
345 * We must clear the register to enable normal behavior.
349 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
356 nor->cmd_buf[0] = enable << 7;
357 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
361 static int spi_nor_sr_ready(struct spi_nor *nor)
363 int sr = read_sr(nor);
368 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
370 dev_dbg(nor->dev, "Erase Error occurred\n");
372 dev_dbg(nor->dev, "Programming Error occurred\n");
374 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
378 return !(sr & SR_WIP);
381 static int spi_nor_fsr_ready(struct spi_nor *nor)
383 int fsr = read_fsr(nor);
388 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
390 dev_dbg(nor->dev, "Erase operation failed.\n");
392 dev_dbg(nor->dev, "Program operation failed.\n");
394 if (fsr & FSR_PT_ERR)
396 "Attempted to modify a protected sector.\n");
398 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
402 return fsr & FSR_READY;
405 static int spi_nor_ready(struct spi_nor *nor)
409 sr = spi_nor_sr_ready(nor);
412 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
419 * Service routine to read status register until ready, or timeout occurs.
420 * Returns non-zero if error.
422 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
423 unsigned long timeout)
425 unsigned long timebase;
428 timebase = get_timer(0);
430 while (get_timer(timebase) < timeout) {
431 ret = spi_nor_ready(nor);
438 dev_err(nor->dev, "flash operation timed out\n");
443 static int spi_nor_wait_till_ready(struct spi_nor *nor)
445 return spi_nor_wait_till_ready_with_timeout(nor,
446 DEFAULT_READY_WAIT_JIFFIES);
449 #ifdef CONFIG_SPI_FLASH_BAR
451 * This "clean_bar" is necessary in a situation when one was accessing
452 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
454 * After it the BA24 bit shall be cleared to allow access to correct
455 * memory region after SW reset (by calling "reset" command).
457 * Otherwise, the BA24 bit may be left set and then after reset, the
458 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
460 static int clean_bar(struct spi_nor *nor)
462 u8 cmd, bank_sel = 0;
464 if (nor->bank_curr == 0)
466 cmd = nor->bank_write_cmd;
470 return nor->write_reg(nor, cmd, &bank_sel, 1);
473 static int write_bar(struct spi_nor *nor, u32 offset)
478 bank_sel = offset / SZ_16M;
479 if (bank_sel == nor->bank_curr)
482 cmd = nor->bank_write_cmd;
484 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
486 debug("SF: fail to write bank register\n");
491 nor->bank_curr = bank_sel;
492 return nor->bank_curr;
495 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
500 switch (JEDEC_MFR(info)) {
501 case SNOR_MFR_SPANSION:
502 nor->bank_read_cmd = SPINOR_OP_BRRD;
503 nor->bank_write_cmd = SPINOR_OP_BRWR;
506 nor->bank_read_cmd = SPINOR_OP_RDEAR;
507 nor->bank_write_cmd = SPINOR_OP_WREAR;
510 ret = nor->read_reg(nor, nor->bank_read_cmd,
513 debug("SF: fail to read bank addr register\n");
516 nor->bank_curr = curr_bank;
523 * Initiate the erasure of a single sector
525 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
527 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
531 return nor->erase(nor, addr);
534 * Default implementation, if driver doesn't have a specialized HW
537 for (i = nor->addr_width - 1; i >= 0; i--) {
538 buf[i] = addr & 0xff;
542 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
546 * Erase an address range on the nor chip. The address range may extend
547 * one or more erase sectors. Return an error is there is a problem erasing.
549 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
551 struct spi_nor *nor = mtd_to_spi_nor(mtd);
555 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
556 (long long)instr->len);
558 div_u64_rem(instr->len, mtd->erasesize, &rem);
566 #ifdef CONFIG_SPI_FLASH_BAR
567 ret = write_bar(nor, addr);
573 ret = spi_nor_erase_sector(nor, addr);
577 addr += mtd->erasesize;
578 len -= mtd->erasesize;
580 ret = spi_nor_wait_till_ready(nor);
586 #ifdef CONFIG_SPI_FLASH_BAR
587 ret = clean_bar(nor);
594 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
595 /* Write status register and ensure bits in mask match written values */
596 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
601 ret = write_sr(nor, status_new);
605 ret = spi_nor_wait_till_ready(nor);
613 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
616 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
619 struct mtd_info *mtd = &nor->mtd;
620 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
621 int shift = ffs(mask) - 1;
629 pow = ((sr & mask) ^ mask) >> shift;
630 *len = mtd->size >> pow;
631 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
634 *ofs = mtd->size - *len;
639 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
640 * @locked is false); 0 otherwise
642 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
651 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
654 /* Requested range is a sub-range of locked range */
655 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
657 /* Requested range does not overlap with locked range */
658 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
661 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
664 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
667 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
670 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
674 * Lock a region of the flash. Compatible with ST Micro and similar flash.
675 * Supports the block protection bits BP{0,1,2} in the status register
676 * (SR). Does not support these features found in newer SR bitfields:
677 * - SEC: sector/block protect - only handle SEC=0 (block protect)
678 * - CMP: complement protect - only support CMP=0 (range is not complemented)
680 * Support for the following is provided conditionally for some flash:
681 * - TB: top/bottom protect
683 * Sample table portion for 8MB flash (Winbond w25q64fw):
685 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
686 * --------------------------------------------------------------------------
687 * X | X | 0 | 0 | 0 | NONE | NONE
688 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
689 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
690 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
691 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
692 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
693 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
694 * X | X | 1 | 1 | 1 | 8 MB | ALL
695 * ------|-------|-------|-------|-------|---------------|-------------------
696 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
697 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
698 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
699 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
700 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
701 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
703 * Returns negative on errors, 0 on success.
705 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
707 struct mtd_info *mtd = &nor->mtd;
708 int status_old, status_new;
709 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
710 u8 shift = ffs(mask) - 1, pow, val;
712 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
715 status_old = read_sr(nor);
719 /* If nothing in our range is unlocked, we don't need to do anything */
720 if (stm_is_locked_sr(nor, ofs, len, status_old))
723 /* If anything below us is unlocked, we can't use 'bottom' protection */
724 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
725 can_be_bottom = false;
727 /* If anything above us is unlocked, we can't use 'top' protection */
728 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
732 if (!can_be_bottom && !can_be_top)
735 /* Prefer top, if both are valid */
736 use_top = can_be_top;
738 /* lock_len: length of region that should end up locked */
740 lock_len = mtd->size - ofs;
742 lock_len = ofs + len;
745 * Need smallest pow such that:
747 * 1 / (2^pow) <= (len / size)
749 * so (assuming power-of-2 size) we do:
751 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
753 pow = ilog2(mtd->size) - ilog2(lock_len);
754 val = mask - (pow << shift);
757 /* Don't "lock" with no region! */
761 status_new = (status_old & ~mask & ~SR_TB) | val;
763 /* Disallow further writes if WP pin is asserted */
764 status_new |= SR_SRWD;
769 /* Don't bother if they're the same */
770 if (status_new == status_old)
773 /* Only modify protection if it will not unlock other areas */
774 if ((status_new & mask) < (status_old & mask))
777 return write_sr_and_check(nor, status_new, mask);
781 * Unlock a region of the flash. See stm_lock() for more info
783 * Returns negative on errors, 0 on success.
785 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
787 struct mtd_info *mtd = &nor->mtd;
788 int status_old, status_new;
789 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
790 u8 shift = ffs(mask) - 1, pow, val;
792 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
795 status_old = read_sr(nor);
799 /* If nothing in our range is locked, we don't need to do anything */
800 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
803 /* If anything below us is locked, we can't use 'top' protection */
804 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
807 /* If anything above us is locked, we can't use 'bottom' protection */
808 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
810 can_be_bottom = false;
812 if (!can_be_bottom && !can_be_top)
815 /* Prefer top, if both are valid */
816 use_top = can_be_top;
818 /* lock_len: length of region that should remain locked */
820 lock_len = mtd->size - (ofs + len);
825 * Need largest pow such that:
827 * 1 / (2^pow) >= (len / size)
829 * so (assuming power-of-2 size) we do:
831 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
833 pow = ilog2(mtd->size) - order_base_2(lock_len);
835 val = 0; /* fully unlocked */
837 val = mask - (pow << shift);
838 /* Some power-of-two sizes are not supported */
843 status_new = (status_old & ~mask & ~SR_TB) | val;
845 /* Don't protect status register if we're fully unlocked */
847 status_new &= ~SR_SRWD;
852 /* Don't bother if they're the same */
853 if (status_new == status_old)
856 /* Only modify protection if it will not lock other areas */
857 if ((status_new & mask) > (status_old & mask))
860 return write_sr_and_check(nor, status_new, mask);
864 * Check if a region of the flash is (completely) locked. See stm_lock() for
867 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
868 * negative on errors.
870 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
874 status = read_sr(nor);
878 return stm_is_locked_sr(nor, ofs, len, status);
880 #endif /* CONFIG_SPI_FLASH_STMICRO */
882 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
885 u8 id[SPI_NOR_MAX_ID_LEN];
886 const struct flash_info *info;
888 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
890 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
895 for (; info->name; info++) {
897 if (!memcmp(info->id, id, info->id_len))
902 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
903 id[0], id[1], id[2]);
904 return ERR_PTR(-ENODEV);
907 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
908 size_t *retlen, u_char *buf)
910 struct spi_nor *nor = mtd_to_spi_nor(mtd);
913 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
917 size_t read_len = len;
919 #ifdef CONFIG_SPI_FLASH_BAR
922 ret = write_bar(nor, addr);
925 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
927 if (len < remain_len)
930 read_len = remain_len;
933 ret = nor->read(nor, addr, read_len, buf);
935 /* We shouldn't see 0-length reads */
950 #ifdef CONFIG_SPI_FLASH_BAR
951 ret = clean_bar(nor);
956 #ifdef CONFIG_SPI_FLASH_SST
957 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
958 size_t *retlen, const u_char *buf)
963 for (actual = 0; actual < len; actual++) {
964 nor->program_opcode = SPINOR_OP_BP;
967 /* write one byte. */
968 ret = nor->write(nor, to, 1, buf + actual);
971 ret = spi_nor_wait_till_ready(nor);
982 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
983 size_t *retlen, const u_char *buf)
985 struct spi_nor *nor = mtd_to_spi_nor(mtd);
986 struct spi_slave *spi = nor->spi;
990 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
991 if (spi->mode & SPI_TX_BYTE)
992 return sst_write_byteprogram(nor, to, len, retlen, buf);
996 nor->sst_write_second = false;
999 /* Start write from odd address. */
1001 nor->program_opcode = SPINOR_OP_BP;
1003 /* write one byte. */
1004 ret = nor->write(nor, to, 1, buf);
1007 ret = spi_nor_wait_till_ready(nor);
1013 /* Write out most of the data here. */
1014 for (; actual < len - 1; actual += 2) {
1015 nor->program_opcode = SPINOR_OP_AAI_WP;
1017 /* write two bytes. */
1018 ret = nor->write(nor, to, 2, buf + actual);
1021 ret = spi_nor_wait_till_ready(nor);
1025 nor->sst_write_second = true;
1027 nor->sst_write_second = false;
1030 ret = spi_nor_wait_till_ready(nor);
1034 /* Write out trailing byte if it exists. */
1035 if (actual != len) {
1038 nor->program_opcode = SPINOR_OP_BP;
1039 ret = nor->write(nor, to, 1, buf + actual);
1042 ret = spi_nor_wait_till_ready(nor);
1054 * Write an address range to the nor chip. Data must be written in
1055 * FLASH_PAGESIZE chunks. The address range may be any size provided
1056 * it is within the physical boundaries.
1058 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1059 size_t *retlen, const u_char *buf)
1061 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1062 size_t page_offset, page_remain, i;
1065 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1067 for (i = 0; i < len; ) {
1069 loff_t addr = to + i;
1072 * If page_size is a power of two, the offset can be quickly
1073 * calculated with an AND operation. On the other cases we
1074 * need to do a modulus operation (more expensive).
1075 * Power of two numbers have only one bit set and we can use
1076 * the instruction hweight32 to detect if we need to do a
1077 * modulus (do_div()) or not.
1079 if (hweight32(nor->page_size) == 1) {
1080 page_offset = addr & (nor->page_size - 1);
1084 page_offset = do_div(aux, nor->page_size);
1086 /* the size of data remaining on the first page */
1087 page_remain = min_t(size_t,
1088 nor->page_size - page_offset, len - i);
1090 #ifdef CONFIG_SPI_FLASH_BAR
1091 ret = write_bar(nor, addr);
1096 ret = nor->write(nor, addr, page_remain, buf + i);
1101 ret = spi_nor_wait_till_ready(nor);
1106 if (written != page_remain) {
1113 #ifdef CONFIG_SPI_FLASH_BAR
1114 ret = clean_bar(nor);
1119 #ifdef CONFIG_SPI_FLASH_MACRONIX
1121 * macronix_quad_enable() - set QE bit in Status Register.
1122 * @nor: pointer to a 'struct spi_nor'
1124 * Set the Quad Enable (QE) bit in the Status Register.
1126 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1128 * Return: 0 on success, -errno otherwise.
1130 static int macronix_quad_enable(struct spi_nor *nor)
1137 if (val & SR_QUAD_EN_MX)
1142 write_sr(nor, val | SR_QUAD_EN_MX);
1144 ret = spi_nor_wait_till_ready(nor);
1149 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1150 dev_err(nor->dev, "Macronix Quad bit not set\n");
1158 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1160 * Write status Register and configuration register with 2 bytes
1161 * The first byte will be written to the status register, while the
1162 * second byte will be written to the configuration register.
1163 * Return negative if error occurred.
1165 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1171 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1174 "error while writing configuration register\n");
1178 ret = spi_nor_wait_till_ready(nor);
1181 "timeout while writing configuration register\n");
1189 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1190 * @nor: pointer to a 'struct spi_nor'
1192 * Set the Quad Enable (QE) bit in the Configuration Register.
1193 * This function should be used with QSPI memories supporting the Read
1194 * Configuration Register (35h) instruction.
1196 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1199 * Return: 0 on success, -errno otherwise.
1201 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1206 /* Check current Quad Enable bit value. */
1209 dev_dbg(dev, "error while reading configuration register\n");
1213 if (ret & CR_QUAD_EN_SPAN)
1216 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1218 /* Keep the current value of the Status Register. */
1221 dev_dbg(dev, "error while reading status register\n");
1226 ret = write_sr_cr(nor, sr_cr);
1230 /* Read back and check it. */
1232 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1233 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1240 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1242 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1243 * @nor: pointer to a 'struct spi_nor'
1245 * Set the Quad Enable (QE) bit in the Configuration Register.
1246 * This function should be used with QSPI memories not supporting the Read
1247 * Configuration Register (35h) instruction.
1249 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1252 * Return: 0 on success, -errno otherwise.
1254 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1259 /* Keep the current value of the Status Register. */
1262 dev_dbg(nor->dev, "error while reading status register\n");
1266 sr_cr[1] = CR_QUAD_EN_SPAN;
1268 return write_sr_cr(nor, sr_cr);
1271 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1272 #endif /* CONFIG_SPI_FLASH_SPANSION */
1274 struct spi_nor_read_command {
1278 enum spi_nor_protocol proto;
1281 struct spi_nor_pp_command {
1283 enum spi_nor_protocol proto;
1286 enum spi_nor_read_command_index {
1289 SNOR_CMD_READ_1_1_1_DTR,
1292 SNOR_CMD_READ_1_1_2,
1293 SNOR_CMD_READ_1_2_2,
1294 SNOR_CMD_READ_2_2_2,
1295 SNOR_CMD_READ_1_2_2_DTR,
1298 SNOR_CMD_READ_1_1_4,
1299 SNOR_CMD_READ_1_4_4,
1300 SNOR_CMD_READ_4_4_4,
1301 SNOR_CMD_READ_1_4_4_DTR,
1304 SNOR_CMD_READ_1_1_8,
1305 SNOR_CMD_READ_1_8_8,
1306 SNOR_CMD_READ_8_8_8,
1307 SNOR_CMD_READ_1_8_8_DTR,
1312 enum spi_nor_pp_command_index {
1328 struct spi_nor_flash_parameter {
1332 struct spi_nor_hwcaps hwcaps;
1333 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1334 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1336 int (*quad_enable)(struct spi_nor *nor);
1340 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1344 enum spi_nor_protocol proto)
1346 read->num_mode_clocks = num_mode_clocks;
1347 read->num_wait_states = num_wait_states;
1348 read->opcode = opcode;
1349 read->proto = proto;
1353 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1355 enum spi_nor_protocol proto)
1357 pp->opcode = opcode;
1361 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1363 * Serial Flash Discoverable Parameters (SFDP) parsing.
1367 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1368 * @nor: pointer to a 'struct spi_nor'
1369 * @addr: offset in the SFDP area to start reading data from
1370 * @len: number of bytes to read
1371 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1373 * Whatever the actual numbers of bytes for address and dummy cycles are
1374 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1375 * followed by a 3-byte address and 8 dummy clock cycles.
1377 * Return: 0 on success, -errno otherwise.
1379 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1380 size_t len, void *buf)
1382 u8 addr_width, read_opcode, read_dummy;
1385 read_opcode = nor->read_opcode;
1386 addr_width = nor->addr_width;
1387 read_dummy = nor->read_dummy;
1389 nor->read_opcode = SPINOR_OP_RDSFDP;
1390 nor->addr_width = 3;
1391 nor->read_dummy = 8;
1394 ret = nor->read(nor, addr, len, (u8 *)buf);
1395 if (!ret || ret > len) {
1409 nor->read_opcode = read_opcode;
1410 nor->addr_width = addr_width;
1411 nor->read_dummy = read_dummy;
1416 struct sfdp_parameter_header {
1420 u8 length; /* in double words */
1421 u8 parameter_table_pointer[3]; /* byte address */
1425 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1426 #define SFDP_PARAM_HEADER_PTP(p) \
1427 (((p)->parameter_table_pointer[2] << 16) | \
1428 ((p)->parameter_table_pointer[1] << 8) | \
1429 ((p)->parameter_table_pointer[0] << 0))
1431 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1432 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1434 #define SFDP_SIGNATURE 0x50444653U
1435 #define SFDP_JESD216_MAJOR 1
1436 #define SFDP_JESD216_MINOR 0
1437 #define SFDP_JESD216A_MINOR 5
1438 #define SFDP_JESD216B_MINOR 6
1440 struct sfdp_header {
1441 u32 signature; /* Ox50444653U <=> "SFDP" */
1444 u8 nph; /* 0-base number of parameter headers */
1447 /* Basic Flash Parameter Table. */
1448 struct sfdp_parameter_header bfpt_header;
1451 /* Basic Flash Parameter Table */
1454 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1455 * They are indexed from 1 but C arrays are indexed from 0.
1457 #define BFPT_DWORD(i) ((i) - 1)
1458 #define BFPT_DWORD_MAX 16
1460 /* The first version of JESB216 defined only 9 DWORDs. */
1461 #define BFPT_DWORD_MAX_JESD216 9
1464 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1465 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1466 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1467 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1468 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1469 #define BFPT_DWORD1_DTR BIT(19)
1470 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1471 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1472 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1475 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1476 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1479 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1480 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1485 * (from JESD216 rev B)
1486 * Quad Enable Requirements (QER):
1487 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1488 * reads based on instruction. DQ3/HOLD# functions are hold during
1489 * instruction phase.
1490 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1491 * two data bytes where bit 1 of the second byte is one.
1493 * Writing only one byte to the status register has the side-effect of
1494 * clearing status register 2, including the QE bit. The 100b code is
1495 * used if writing one byte to the status register does not modify
1496 * status register 2.
1497 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1498 * one data byte where bit 6 is one.
1500 * - 011b: QE is bit 7 of status register 2. It is set via Write status
1501 * register 2 instruction 3Eh with one data byte where bit 7 is one.
1503 * The status register 2 is read using instruction 3Fh.
1504 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
1505 * two data bytes where bit 1 of the second byte is one.
1507 * In contrast to the 001b code, writing one byte to the status
1508 * register does not modify status register 2.
1509 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
1510 * Read Status instruction 05h. Status register2 is read using
1511 * instruction 35h. QE is set via Writ Status instruction 01h with
1512 * two data bytes where bit 1 of the second byte is one.
1515 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
1516 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
1517 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
1518 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
1519 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
1520 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
1521 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
1524 u32 dwords[BFPT_DWORD_MAX];
1527 /* Fast Read settings. */
1530 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1532 enum spi_nor_protocol proto)
1534 read->num_mode_clocks = (half >> 5) & 0x07;
1535 read->num_wait_states = (half >> 0) & 0x1f;
1536 read->opcode = (half >> 8) & 0xff;
1537 read->proto = proto;
1540 struct sfdp_bfpt_read {
1541 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1545 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1546 * whether the Fast Read x-y-z command is supported.
1548 u32 supported_dword;
1552 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1553 * encodes the op code, the number of mode clocks and the number of wait
1554 * states to be used by Fast Read x-y-z command.
1559 /* The SPI protocol for this Fast Read x-y-z command. */
1560 enum spi_nor_protocol proto;
1563 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1564 /* Fast Read 1-1-2 */
1566 SNOR_HWCAPS_READ_1_1_2,
1567 BFPT_DWORD(1), BIT(16), /* Supported bit */
1568 BFPT_DWORD(4), 0, /* Settings */
1572 /* Fast Read 1-2-2 */
1574 SNOR_HWCAPS_READ_1_2_2,
1575 BFPT_DWORD(1), BIT(20), /* Supported bit */
1576 BFPT_DWORD(4), 16, /* Settings */
1580 /* Fast Read 2-2-2 */
1582 SNOR_HWCAPS_READ_2_2_2,
1583 BFPT_DWORD(5), BIT(0), /* Supported bit */
1584 BFPT_DWORD(6), 16, /* Settings */
1588 /* Fast Read 1-1-4 */
1590 SNOR_HWCAPS_READ_1_1_4,
1591 BFPT_DWORD(1), BIT(22), /* Supported bit */
1592 BFPT_DWORD(3), 16, /* Settings */
1596 /* Fast Read 1-4-4 */
1598 SNOR_HWCAPS_READ_1_4_4,
1599 BFPT_DWORD(1), BIT(21), /* Supported bit */
1600 BFPT_DWORD(3), 0, /* Settings */
1604 /* Fast Read 4-4-4 */
1606 SNOR_HWCAPS_READ_4_4_4,
1607 BFPT_DWORD(5), BIT(4), /* Supported bit */
1608 BFPT_DWORD(7), 16, /* Settings */
1613 struct sfdp_bfpt_erase {
1615 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1616 * op code and erase sector size to be used by Sector Erase commands.
1622 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1623 /* Erase Type 1 in DWORD8 bits[15:0] */
1626 /* Erase Type 2 in DWORD8 bits[31:16] */
1627 {BFPT_DWORD(8), 16},
1629 /* Erase Type 3 in DWORD9 bits[15:0] */
1632 /* Erase Type 4 in DWORD9 bits[31:16] */
1633 {BFPT_DWORD(9), 16},
1636 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1639 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1640 * @nor: pointer to a 'struct spi_nor'
1641 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1642 * the Basic Flash Parameter Table length and version
1643 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1646 * The Basic Flash Parameter Table is the main and only mandatory table as
1647 * defined by the SFDP (JESD216) specification.
1648 * It provides us with the total size (memory density) of the data array and
1649 * the number of address bytes for Fast Read, Page Program and Sector Erase
1651 * For Fast READ commands, it also gives the number of mode clock cycles and
1652 * wait states (regrouped in the number of dummy clock cycles) for each
1653 * supported instruction op code.
1654 * For Page Program, the page size is now available since JESD216 rev A, however
1655 * the supported instruction op codes are still not provided.
1656 * For Sector Erase commands, this table stores the supported instruction op
1657 * codes and the associated sector sizes.
1658 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
1659 * rev A. The QER bits encode the manufacturer dependent procedure to be
1660 * executed to set the Quad Enable (QE) bit in some internal register of the
1661 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1662 * sending any Quad SPI command to the memory. Actually, setting the QE bit
1663 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1664 * and IO3 hence enabling 4 (Quad) I/O lines.
1666 * Return: 0 on success, -errno otherwise.
1668 static int spi_nor_parse_bfpt(struct spi_nor *nor,
1669 const struct sfdp_parameter_header *bfpt_header,
1670 struct spi_nor_flash_parameter *params)
1672 struct mtd_info *mtd = &nor->mtd;
1673 struct sfdp_bfpt bfpt;
1679 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1680 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1683 /* Read the Basic Flash Parameter Table. */
1684 len = min_t(size_t, sizeof(bfpt),
1685 bfpt_header->length * sizeof(u32));
1686 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
1687 memset(&bfpt, 0, sizeof(bfpt));
1688 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
1692 /* Fix endianness of the BFPT DWORDs. */
1693 for (i = 0; i < BFPT_DWORD_MAX; i++)
1694 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
1696 /* Number of address bytes. */
1697 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
1698 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
1699 nor->addr_width = 3;
1702 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
1703 nor->addr_width = 4;
1710 /* Flash Memory Density (in bits). */
1711 params->size = bfpt.dwords[BFPT_DWORD(2)];
1712 if (params->size & BIT(31)) {
1713 params->size &= ~BIT(31);
1716 * Prevent overflows on params->size. Anyway, a NOR of 2^64
1717 * bits is unlikely to exist so this error probably means
1718 * the BFPT we are reading is corrupted/wrong.
1720 if (params->size > 63)
1723 params->size = 1ULL << params->size;
1727 params->size >>= 3; /* Convert to bytes. */
1729 /* Fast Read settings. */
1730 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
1731 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
1732 struct spi_nor_read_command *read;
1734 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
1735 params->hwcaps.mask &= ~rd->hwcaps;
1739 params->hwcaps.mask |= rd->hwcaps;
1740 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
1741 read = ¶ms->reads[cmd];
1742 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
1743 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
1746 /* Sector Erase settings. */
1747 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
1748 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
1752 half = bfpt.dwords[er->dword] >> er->shift;
1753 erasesize = half & 0xff;
1755 /* erasesize == 0 means this Erase Type is not supported. */
1759 erasesize = 1U << erasesize;
1760 opcode = (half >> 8) & 0xff;
1761 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1762 if (erasesize == SZ_4K) {
1763 nor->erase_opcode = opcode;
1764 mtd->erasesize = erasesize;
1768 if (!mtd->erasesize || mtd->erasesize < erasesize) {
1769 nor->erase_opcode = opcode;
1770 mtd->erasesize = erasesize;
1774 /* Stop here if not JESD216 rev A or later. */
1775 if (bfpt_header->length < BFPT_DWORD_MAX)
1778 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
1779 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
1780 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
1781 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
1782 params->page_size = 1U << params->page_size;
1784 /* Quad Enable Requirements. */
1785 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
1786 case BFPT_DWORD15_QER_NONE:
1787 params->quad_enable = NULL;
1789 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1790 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
1791 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
1792 params->quad_enable = spansion_no_read_cr_quad_enable;
1795 #ifdef CONFIG_SPI_FLASH_MACRONIX
1796 case BFPT_DWORD15_QER_SR1_BIT6:
1797 params->quad_enable = macronix_quad_enable;
1800 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1801 case BFPT_DWORD15_QER_SR2_BIT1:
1802 params->quad_enable = spansion_read_cr_quad_enable;
1813 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
1814 * @nor: pointer to a 'struct spi_nor'
1815 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1818 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
1819 * specification. This is a standard which tends to supported by almost all
1820 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
1821 * runtime the main parameters needed to perform basic SPI flash operations such
1822 * as Fast Read, Page Program or Sector Erase commands.
1824 * Return: 0 on success, -errno otherwise.
1826 static int spi_nor_parse_sfdp(struct spi_nor *nor,
1827 struct spi_nor_flash_parameter *params)
1829 const struct sfdp_parameter_header *param_header, *bfpt_header;
1830 struct sfdp_parameter_header *param_headers = NULL;
1831 struct sfdp_header header;
1835 /* Get the SFDP header. */
1836 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
1840 /* Check the SFDP header version. */
1841 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
1842 header.major != SFDP_JESD216_MAJOR)
1846 * Verify that the first and only mandatory parameter header is a
1847 * Basic Flash Parameter Table header as specified in JESD216.
1849 bfpt_header = &header.bfpt_header;
1850 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
1851 bfpt_header->major != SFDP_JESD216_MAJOR)
1855 * Allocate memory then read all parameter headers with a single
1856 * Read SFDP command. These parameter headers will actually be parsed
1857 * twice: a first time to get the latest revision of the basic flash
1858 * parameter table, then a second time to handle the supported optional
1860 * Hence we read the parameter headers once for all to reduce the
1861 * processing time. Also we use kmalloc() instead of devm_kmalloc()
1862 * because we don't need to keep these parameter headers: the allocated
1863 * memory is always released with kfree() before exiting this function.
1866 psize = header.nph * sizeof(*param_headers);
1868 param_headers = kmalloc(psize, GFP_KERNEL);
1872 err = spi_nor_read_sfdp(nor, sizeof(header),
1873 psize, param_headers);
1875 dev_err(dev, "failed to read SFDP parameter headers\n");
1881 * Check other parameter headers to get the latest revision of
1882 * the basic flash parameter table.
1884 for (i = 0; i < header.nph; i++) {
1885 param_header = ¶m_headers[i];
1887 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
1888 param_header->major == SFDP_JESD216_MAJOR &&
1889 (param_header->minor > bfpt_header->minor ||
1890 (param_header->minor == bfpt_header->minor &&
1891 param_header->length > bfpt_header->length)))
1892 bfpt_header = param_header;
1895 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
1899 /* Parse other parameter headers. */
1900 for (i = 0; i < header.nph; i++) {
1901 param_header = ¶m_headers[i];
1903 switch (SFDP_PARAM_HEADER_ID(param_header)) {
1904 case SFDP_SECTOR_MAP_ID:
1905 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
1917 kfree(param_headers);
1921 static int spi_nor_parse_sfdp(struct spi_nor *nor,
1922 struct spi_nor_flash_parameter *params)
1926 #endif /* SPI_FLASH_SFDP_SUPPORT */
1928 static int spi_nor_init_params(struct spi_nor *nor,
1929 const struct flash_info *info,
1930 struct spi_nor_flash_parameter *params)
1932 /* Set legacy flash parameters as default. */
1933 memset(params, 0, sizeof(*params));
1935 /* Set SPI NOR sizes. */
1936 params->size = info->sector_size * info->n_sectors;
1937 params->page_size = info->page_size;
1939 /* (Fast) Read settings. */
1940 params->hwcaps.mask |= SNOR_HWCAPS_READ;
1941 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
1942 0, 0, SPINOR_OP_READ,
1945 if (!(info->flags & SPI_NOR_NO_FR)) {
1946 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
1947 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
1948 0, 8, SPINOR_OP_READ_FAST,
1952 if (info->flags & SPI_NOR_DUAL_READ) {
1953 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
1954 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
1955 0, 8, SPINOR_OP_READ_1_1_2,
1959 if (info->flags & SPI_NOR_QUAD_READ) {
1960 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
1961 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
1962 0, 8, SPINOR_OP_READ_1_1_4,
1966 /* Page Program settings. */
1967 params->hwcaps.mask |= SNOR_HWCAPS_PP;
1968 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
1969 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
1971 if (info->flags & SPI_NOR_QUAD_READ) {
1972 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
1973 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
1974 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
1977 /* Select the procedure to set the Quad Enable bit. */
1978 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
1979 SNOR_HWCAPS_PP_QUAD)) {
1980 switch (JEDEC_MFR(info)) {
1981 #ifdef CONFIG_SPI_FLASH_MACRONIX
1982 case SNOR_MFR_MACRONIX:
1983 params->quad_enable = macronix_quad_enable;
1987 case SNOR_MFR_MICRON:
1991 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1992 /* Kept only for backward compatibility purpose. */
1993 params->quad_enable = spansion_read_cr_quad_enable;
1999 /* Override the parameters with data read from SFDP tables. */
2000 nor->addr_width = 0;
2001 nor->mtd.erasesize = 0;
2002 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2003 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2004 struct spi_nor_flash_parameter sfdp_params;
2006 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2007 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2008 nor->addr_width = 0;
2009 nor->mtd.erasesize = 0;
2011 memcpy(params, &sfdp_params, sizeof(*params));
2018 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2022 for (i = 0; i < size; i++)
2023 if (table[i][0] == (int)hwcaps)
2029 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2031 static const int hwcaps_read2cmd[][2] = {
2032 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2033 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2034 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2035 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2036 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2037 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2038 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2039 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2040 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2041 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2042 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2043 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2044 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2045 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2046 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2049 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2050 ARRAY_SIZE(hwcaps_read2cmd));
2053 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2055 static const int hwcaps_pp2cmd[][2] = {
2056 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2057 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2058 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2059 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2060 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2061 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2062 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2065 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2066 ARRAY_SIZE(hwcaps_pp2cmd));
2069 static int spi_nor_select_read(struct spi_nor *nor,
2070 const struct spi_nor_flash_parameter *params,
2073 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2074 const struct spi_nor_read_command *read;
2079 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2083 read = ¶ms->reads[cmd];
2084 nor->read_opcode = read->opcode;
2085 nor->read_proto = read->proto;
2088 * In the spi-nor framework, we don't need to make the difference
2089 * between mode clock cycles and wait state clock cycles.
2090 * Indeed, the value of the mode clock cycles is used by a QSPI
2091 * flash memory to know whether it should enter or leave its 0-4-4
2092 * (Continuous Read / XIP) mode.
2093 * eXecution In Place is out of the scope of the mtd sub-system.
2094 * Hence we choose to merge both mode and wait state clock cycles
2095 * into the so called dummy clock cycles.
2097 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2101 static int spi_nor_select_pp(struct spi_nor *nor,
2102 const struct spi_nor_flash_parameter *params,
2105 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2106 const struct spi_nor_pp_command *pp;
2111 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2115 pp = ¶ms->page_programs[cmd];
2116 nor->program_opcode = pp->opcode;
2117 nor->write_proto = pp->proto;
2121 static int spi_nor_select_erase(struct spi_nor *nor,
2122 const struct flash_info *info)
2124 struct mtd_info *mtd = &nor->mtd;
2126 /* Do nothing if already configured from SFDP. */
2130 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2131 /* prefer "small sector" erase if possible */
2132 if (info->flags & SECT_4K) {
2133 nor->erase_opcode = SPINOR_OP_BE_4K;
2134 mtd->erasesize = 4096;
2135 } else if (info->flags & SECT_4K_PMC) {
2136 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2137 mtd->erasesize = 4096;
2141 nor->erase_opcode = SPINOR_OP_SE;
2142 mtd->erasesize = info->sector_size;
2147 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2148 const struct spi_nor_flash_parameter *params,
2149 const struct spi_nor_hwcaps *hwcaps)
2151 u32 ignored_mask, shared_mask;
2152 bool enable_quad_io;
2156 * Keep only the hardware capabilities supported by both the SPI
2157 * controller and the SPI flash memory.
2159 shared_mask = hwcaps->mask & params->hwcaps.mask;
2161 /* SPI n-n-n protocols are not supported yet. */
2162 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2163 SNOR_HWCAPS_READ_4_4_4 |
2164 SNOR_HWCAPS_READ_8_8_8 |
2165 SNOR_HWCAPS_PP_4_4_4 |
2166 SNOR_HWCAPS_PP_8_8_8);
2167 if (shared_mask & ignored_mask) {
2169 "SPI n-n-n protocols are not supported yet.\n");
2170 shared_mask &= ~ignored_mask;
2173 /* Select the (Fast) Read command. */
2174 err = spi_nor_select_read(nor, params, shared_mask);
2177 "can't select read settings supported by both the SPI controller and memory.\n");
2181 /* Select the Page Program command. */
2182 err = spi_nor_select_pp(nor, params, shared_mask);
2185 "can't select write settings supported by both the SPI controller and memory.\n");
2189 /* Select the Sector Erase command. */
2190 err = spi_nor_select_erase(nor, info);
2193 "can't select erase settings supported by both the SPI controller and memory.\n");
2197 /* Enable Quad I/O if needed. */
2198 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2199 spi_nor_get_protocol_width(nor->write_proto) == 4);
2200 if (enable_quad_io && params->quad_enable)
2201 nor->quad_enable = params->quad_enable;
2203 nor->quad_enable = NULL;
2208 static int spi_nor_init(struct spi_nor *nor)
2213 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2214 * with the software protection bits set
2216 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2217 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2218 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2219 nor->info->flags & SPI_NOR_HAS_LOCK) {
2222 spi_nor_wait_till_ready(nor);
2225 if (nor->quad_enable) {
2226 err = nor->quad_enable(nor);
2228 dev_dbg(nor->dev, "quad mode not supported\n");
2233 if (nor->addr_width == 4 &&
2234 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2235 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2237 * If the RESET# pin isn't hooked up properly, or the system
2238 * otherwise doesn't perform a reset command in the boot
2239 * sequence, it's impossible to 100% protect against unexpected
2240 * reboots (e.g., crashes). Warn the user (or hopefully, system
2241 * designer) that this is bad.
2243 if (nor->flags & SNOR_F_BROKEN_RESET)
2244 printf("enabling reset hack; may not recover from unexpected reboots\n");
2245 set_4byte(nor, nor->info, 1);
2251 int spi_nor_scan(struct spi_nor *nor)
2253 struct spi_nor_flash_parameter params;
2254 const struct flash_info *info = NULL;
2255 struct mtd_info *mtd = &nor->mtd;
2256 struct spi_nor_hwcaps hwcaps = {
2257 .mask = SNOR_HWCAPS_READ |
2258 SNOR_HWCAPS_READ_FAST |
2261 struct spi_slave *spi = nor->spi;
2264 /* Reset SPI protocol for all commands. */
2265 nor->reg_proto = SNOR_PROTO_1_1_1;
2266 nor->read_proto = SNOR_PROTO_1_1_1;
2267 nor->write_proto = SNOR_PROTO_1_1_1;
2268 nor->read = spi_nor_read_data;
2269 nor->write = spi_nor_write_data;
2270 nor->read_reg = spi_nor_read_reg;
2271 nor->write_reg = spi_nor_write_reg;
2273 if (spi->mode & SPI_RX_QUAD) {
2274 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2276 if (spi->mode & SPI_TX_QUAD)
2277 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
2278 SNOR_HWCAPS_PP_1_1_4 |
2279 SNOR_HWCAPS_PP_1_4_4);
2280 } else if (spi->mode & SPI_RX_DUAL) {
2281 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2283 if (spi->mode & SPI_TX_DUAL)
2284 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
2287 info = spi_nor_read_id(nor);
2288 if (IS_ERR_OR_NULL(info))
2290 /* Parse the Serial Flash Discoverable Parameters table. */
2291 ret = spi_nor_init_params(nor, info, ¶ms);
2296 mtd->name = info->name;
2298 mtd->type = MTD_NORFLASH;
2300 mtd->flags = MTD_CAP_NORFLASH;
2301 mtd->size = params.size;
2302 mtd->_erase = spi_nor_erase;
2303 mtd->_read = spi_nor_read;
2305 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
2306 /* NOR protection support for STmicro/Micron chips and similar */
2307 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
2308 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2309 JEDEC_MFR(info) == SNOR_MFR_SST ||
2310 info->flags & SPI_NOR_HAS_LOCK) {
2311 nor->flash_lock = stm_lock;
2312 nor->flash_unlock = stm_unlock;
2313 nor->flash_is_locked = stm_is_locked;
2317 #ifdef CONFIG_SPI_FLASH_SST
2318 /* sst nor chips use AAI word program */
2319 if (info->flags & SST_WRITE)
2320 mtd->_write = sst_write;
2323 mtd->_write = spi_nor_write;
2325 if (info->flags & USE_FSR)
2326 nor->flags |= SNOR_F_USE_FSR;
2327 if (info->flags & SPI_NOR_HAS_TB)
2328 nor->flags |= SNOR_F_HAS_SR_TB;
2329 if (info->flags & NO_CHIP_ERASE)
2330 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2331 if (info->flags & USE_CLSR)
2332 nor->flags |= SNOR_F_USE_CLSR;
2334 if (info->flags & SPI_NOR_NO_ERASE)
2335 mtd->flags |= MTD_NO_ERASE;
2337 nor->page_size = params.page_size;
2338 mtd->writebufsize = nor->page_size;
2340 /* Some devices cannot do fast-read, no matter what DT tells us */
2341 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
2342 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2345 * Configure the SPI memory:
2346 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2347 * - set the number of dummy cycles (mode cycles + wait states).
2348 * - set the SPI protocols for register and memory accesses.
2349 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2351 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
2355 if (nor->addr_width) {
2356 /* already configured from SFDP */
2357 } else if (info->addr_width) {
2358 nor->addr_width = info->addr_width;
2359 } else if (mtd->size > SZ_16M) {
2360 #ifndef CONFIG_SPI_FLASH_BAR
2361 /* enable 4-byte addressing if the device exceeds 16MiB */
2362 nor->addr_width = 4;
2363 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2364 info->flags & SPI_NOR_4B_OPCODES)
2365 spi_nor_set_4byte_opcodes(nor, info);
2367 /* Configure the BAR - discover bank cmds and read current bank */
2368 nor->addr_width = 3;
2369 ret = read_bar(nor, info);
2374 nor->addr_width = 3;
2377 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2378 dev_dbg(dev, "address width is too large: %u\n",
2383 /* Send all the required SPI flash commands to initialize device */
2385 ret = spi_nor_init(nor);
2389 nor->name = mtd->name;
2390 nor->size = mtd->size;
2391 nor->erase_size = mtd->erasesize;
2392 nor->sector_size = mtd->erasesize;
2394 #ifndef CONFIG_SPL_BUILD
2395 printf("SF: Detected %s with page size ", nor->name);
2396 print_size(nor->page_size, ", erase size ");
2397 print_size(nor->erase_size, ", total ");
2398 print_size(nor->size, "");
2405 /* U-Boot specific functions, need to extend MTD to support these */
2406 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
2408 int sr = read_sr(nor);
2413 return (sr >> 2) & 7;