drivers/mtd/nand/raw/zynq_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq NAND Flash Controller Driver
   6  * This driver is based on plat_nand.c and mxc_nand.c drivers
   7  */
   8
   9 #include <common.h>
  10 #include <log.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <linux/errno.h>
  14 #include <nand.h>
  15 #include <linux/ioport.h>
  16 #include <linux/mtd/mtd.h>
  17 #include <linux/mtd/rawnand.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/mtd/nand_ecc.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <dm.h>
  23
  24 /* The NAND flash driver defines */
  25 #define ZYNQ_NAND_CMD_PHASE             1
  26 #define ZYNQ_NAND_DATA_PHASE            2
  27 #define ZYNQ_NAND_ECC_SIZE              512
  28 #define ZYNQ_NAND_SET_OPMODE_8BIT       (0 << 0)
  29 #define ZYNQ_NAND_SET_OPMODE_16BIT      (1 << 0)
  30 #define ZYNQ_NAND_ECC_STATUS            (1 << 6)
  31 #define ZYNQ_MEMC_CLRCR_INT_CLR1        (1 << 4)
  32 #define ZYNQ_MEMC_SR_RAW_INT_ST1        (1 << 6)
  33 #define ZYNQ_MEMC_SR_INT_ST1            (1 << 4)
  34 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK    0xC
  35
  36 /* Flash memory controller operating parameters */
  37 #define ZYNQ_NAND_CLR_CONFIG    ((0x1 << 1)  |  /* Disable interrupt */ \
  38                                 (0x1 << 4)   |  /* Clear interrupt */ \
  39                                 (0x1 << 6))     /* Disable ECC interrupt */
  40
  41 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  42
  43 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  44 #define ZYNQ_NAND_SET_CYCLES    ((0x2 << 20) |  /* t_rr from nand_cycles */ \
  45                                 (0x2 << 17)  |  /* t_ar from nand_cycles */ \
  46                                 (0x1 << 14)  |  /* t_clr from nand_cycles */ \
  47                                 (0x3 << 11)  |  /* t_wp from nand_cycles */ \
  48                                 (0x2 << 8)   |  /* t_rea from nand_cycles */ \
  49                                 (0x5 << 4)   |  /* t_wc from nand_cycles */ \
  50                                 (0x5 << 0))     /* t_rc from nand_cycles */
  51 #endif
  52
  53
  54 #define ZYNQ_NAND_DIRECT_CMD    ((0x4 << 23) |  /* Chip 0 from interface 1 */ \
  55                                 (0x2 << 21))    /* UpdateRegs operation */
  56
  57 #define ZYNQ_NAND_ECC_CONFIG    ((0x1 << 2)  |  /* ECC available on APB */ \
  58                                 (0x1 << 4)   |  /* ECC read at end of page */ \
  59                                 (0x0 << 5))     /* No Jumping */
  60
  61 #define ZYNQ_NAND_ECC_CMD1      ((0x80)      |  /* Write command */ \
  62                                 (0x00 << 8)  |  /* Read command */ \
  63                                 (0x30 << 16) |  /* Read End command */ \
  64                                 (0x1 << 24))    /* Read End command calid */
  65
  66 #define ZYNQ_NAND_ECC_CMD2      ((0x85)      |  /* Write col change cmd */ \
  67                                 (0x05 << 8)  |  /* Read col change cmd */ \
  68                                 (0xE0 << 16) |  /* Read col change end cmd */ \
  69                                 (0x1 << 24))    /* Read col change
  70                                                         end cmd valid */
  71 /* AXI Address definitions */
  72 #define START_CMD_SHIFT                 3
  73 #define END_CMD_SHIFT                   11
  74 #define END_CMD_VALID_SHIFT             20
  75 #define ADDR_CYCLES_SHIFT               21
  76 #define CLEAR_CS_SHIFT                  21
  77 #define ECC_LAST_SHIFT                  10
  78 #define COMMAND_PHASE                   (0 << 19)
  79 #define DATA_PHASE                      (1 << 19)
  80 #define ONDIE_ECC_FEATURE_ADDR          0x90
  81 #define ONDIE_ECC_FEATURE_ENABLE        0x08
  82
  83 #define ZYNQ_NAND_ECC_LAST      (1 << ECC_LAST_SHIFT)   /* Set ECC_Last */
  84 #define ZYNQ_NAND_CLEAR_CS      (1 << CLEAR_CS_SHIFT)   /* Clear chip select */
  85
  86 /* ECC block registers bit position and bit mask */
  87 #define ZYNQ_NAND_ECC_BUSY      (1 << 6)        /* ECC block is busy */
  88 #define ZYNQ_NAND_ECC_MASK      0x00FFFFFF      /* ECC value mask */
  89
  90 #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK    0x0F
  91 #define ZYNQ_NAND_COL_ADDR_CYCL_MASK    0xF0
  92
  93 #define ZYNQ_NAND_MIO_NUM_NAND_8BIT     13
  94 #define ZYNQ_NAND_MIO_NUM_NAND_16BIT    8
  95
  96 enum zynq_nand_bus_width {
  97         NAND_BW_UNKNOWN = -1,
  98         NAND_BW_8BIT,
  99         NAND_BW_16BIT,
 100 };
 101
 102 #ifndef NAND_CMD_LOCK_TIGHT
 103 #define NAND_CMD_LOCK_TIGHT 0x2c
 104 #endif
 105
 106 #ifndef NAND_CMD_LOCK_STATUS
 107 #define NAND_CMD_LOCK_STATUS 0x7a
 108 #endif
 109
 110 /* SMC register set */
 111 struct zynq_nand_smc_regs {
 112         u32 csr;                /* 0x00 */
 113         u32 reserved0[2];
 114         u32 cfr;                /* 0x0C */
 115         u32 dcr;                /* 0x10 */
 116         u32 scr;                /* 0x14 */
 117         u32 sor;                /* 0x18 */
 118         u32 reserved1[249];
 119         u32 esr;                /* 0x400 */
 120         u32 emcr;               /* 0x404 */
 121         u32 emcmd1r;            /* 0x408 */
 122         u32 emcmd2r;            /* 0x40C */
 123         u32 reserved2[2];
 124         u32 eval0r;             /* 0x418 */
 125 };
 126
 127 /*
 128  * struct nand_config - Defines the NAND flash driver instance
 129  * @parts:              Pointer to the mtd_partition structure
 130  * @nand_base:          Virtual address of the NAND flash device
 131  * @end_cmd_pending:    End command is pending
 132  * @end_cmd:            End command
 133  */
 134 struct nand_config {
 135         void __iomem    *nand_base;
 136         u8              end_cmd_pending;
 137         u8              end_cmd;
 138 };
 139
 140 struct nand_drv {
 141         struct zynq_nand_smc_regs *reg;
 142         struct nand_config config;
 143 };
 144
 145 struct zynq_nand_info {
 146         struct udevice *dev;
 147         struct nand_drv nand_ctrl;
 148         struct nand_chip nand_chip;
 149 };
 150
 151 /*
 152  * struct zynq_nand_command_format - Defines NAND flash command format
 153  * @start_cmd:          First cycle command (Start command)
 154  * @end_cmd:            Second cycle command (Last command)
 155  * @addr_cycles:        Number of address cycles required to send the address
 156  * @end_cmd_valid:      The second cycle command is valid for cmd or data phase
 157  */
 158 struct zynq_nand_command_format {
 159         u8 start_cmd;
 160         u8 end_cmd;
 161         u8 addr_cycles;
 162         u8 end_cmd_valid;
 163 };
 164
 165 /*  The NAND flash operations command format */
 166 static const struct zynq_nand_command_format zynq_nand_commands[] = {
 167         {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
 168         {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
 169         {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
 170         {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
 171         {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
 172         {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
 173         {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
 174         {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
 175         {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 176         {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 177         {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
 178         {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
 179         {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
 180         {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
 181         {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
 182         {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
 183         {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 184         /* Add all the flash commands supported by the flash device */
 185 };
 186
 187 /* Define default oob placement schemes for large and small page devices */
 188 static struct nand_ecclayout nand_oob_16 = {
 189         .eccbytes = 3,
 190         .eccpos = {0, 1, 2},
 191         .oobfree = {
 192                 { .offset = 8, .length = 8 }
 193         }
 194 };
 195
 196 static struct nand_ecclayout nand_oob_64 = {
 197         .eccbytes = 12,
 198         .eccpos = {
 199                    52, 53, 54, 55, 56, 57,
 200                    58, 59, 60, 61, 62, 63},
 201         .oobfree = {
 202                 { .offset = 2, .length = 50 }
 203         }
 204 };
 205
 206 static struct nand_ecclayout ondie_nand_oob_64 = {
 207         .eccbytes = 32,
 208
 209         .eccpos = {
 210                 8, 9, 10, 11, 12, 13, 14, 15,
 211                 24, 25, 26, 27, 28, 29, 30, 31,
 212                 40, 41, 42, 43, 44, 45, 46, 47,
 213                 56, 57, 58, 59, 60, 61, 62, 63
 214         },
 215
 216         .oobfree = {
 217                 { .offset = 4, .length = 4 },
 218                 { .offset = 20, .length = 4 },
 219                 { .offset = 36, .length = 4 },
 220                 { .offset = 52, .length = 4 }
 221         }
 222 };
 223
 224 /* bbt decriptors for chips with on-die ECC and
 225    chips with 64-byte OOB */
 226 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 227 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 228
 229 static struct nand_bbt_descr bbt_main_descr = {
 230         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 231                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 232         .offs = 4,
 233         .len = 4,
 234         .veroffs = 20,
 235         .maxblocks = 4,
 236         .pattern = bbt_pattern
 237 };
 238
 239 static struct nand_bbt_descr bbt_mirror_descr = {
 240         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 241                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 242         .offs = 4,
 243         .len = 4,
 244         .veroffs = 20,
 245         .maxblocks = 4,
 246         .pattern = mirror_pattern
 247 };
 248
 249 /*
 250  * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
 251  *
 252  * returns: status for command completion, -1 for Timeout
 253  */
 254 static int zynq_nand_waitfor_ecc_completion(struct mtd_info *mtd)
 255 {
 256         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 257         struct nand_drv *smc = nand_get_controller_data(nand_chip);
 258         unsigned long timeout;
 259         u32 status;
 260
 261         /* Wait max 10us */
 262         timeout = 10;
 263         status = readl(&smc->reg->esr);
 264         while (status & ZYNQ_NAND_ECC_BUSY) {
 265                 status = readl(&smc->reg->esr);
 266                 if (timeout == 0)
 267                         return -1;
 268                 timeout--;
 269                 udelay(1);
 270         }
 271
 272         return status;
 273 }
 274
 275 /*
 276  * zynq_nand_init_nand_flash - Initialize NAND controller
 277  * @option:     Device property flags
 278  *
 279  * This function initializes the NAND flash interface on the NAND controller.
 280  *
 281  * returns:     0 on success or error value on failure
 282  */
 283 static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option)
 284 {
 285         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 286         struct nand_drv *smc = nand_get_controller_data(nand_chip);
 287         u32 status;
 288
 289         /* disable interrupts */
 290         writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr);
 291 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 292         /* Initialize the NAND interface by setting cycles and operation mode */
 293         writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr);
 294 #endif
 295         if (option & NAND_BUSWIDTH_16)
 296                 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &smc->reg->sor);
 297         else
 298                 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &smc->reg->sor);
 299
 300         writel(ZYNQ_NAND_DIRECT_CMD, &smc->reg->dcr);
 301
 302         /* Wait till the ECC operation is complete */
 303         status = zynq_nand_waitfor_ecc_completion(mtd);
 304         if (status < 0) {
 305                 printf("%s: Timeout\n", __func__);
 306                 return status;
 307         }
 308
 309         /* Set the command1 and command2 register */
 310         writel(ZYNQ_NAND_ECC_CMD1, &smc->reg->emcmd1r);
 311         writel(ZYNQ_NAND_ECC_CMD2, &smc->reg->emcmd2r);
 312
 313         return 0;
 314 }
 315
 316 /*
 317  * zynq_nand_calculate_hwecc - Calculate Hardware ECC
 318  * @mtd:        Pointer to the mtd_info structure
 319  * @data:       Pointer to the page data
 320  * @ecc_code:   Pointer to the ECC buffer where ECC data needs to be stored
 321  *
 322  * This function retrieves the Hardware ECC data from the controller and returns
 323  * ECC data back to the MTD subsystem.
 324  *
 325  * returns:     0 on success or error value on failure
 326  */
 327 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 328                 u8 *ecc_code)
 329 {
 330         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 331         struct nand_drv *smc = nand_get_controller_data(nand_chip);
 332         u32 ecc_value = 0;
 333         u8 ecc_reg, ecc_byte;
 334         u32 ecc_status;
 335
 336         /* Wait till the ECC operation is complete */
 337         ecc_status = zynq_nand_waitfor_ecc_completion(mtd);
 338         if (ecc_status < 0) {
 339                 printf("%s: Timeout\n", __func__);
 340                 return ecc_status;
 341         }
 342
 343         for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
 344                 /* Read ECC value for each block */
 345                 ecc_value = readl(&smc->reg->eval0r + ecc_reg);
 346
 347                 /* Get the ecc status from ecc read value */
 348                 ecc_status = (ecc_value >> 24) & 0xFF;
 349
 350                 /* ECC value valid */
 351                 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
 352                         for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
 353                                 /* Copy ECC bytes to MTD buffer */
 354                                 *ecc_code = ecc_value & 0xFF;
 355                                 ecc_value = ecc_value >> 8;
 356                                 ecc_code++;
 357                         }
 358                 } else {
 359                         debug("%s: ecc status failed\n", __func__);
 360                 }
 361         }
 362
 363         return 0;
 364 }
 365
 366 /*
 367  * onehot - onehot function
 368  * @value:      value to check for onehot
 369  *
 370  * This function checks whether a value is onehot or not.
 371  * onehot is if and only if one bit is set.
 372  *
 373  * FIXME: Try to move this in common.h
 374  */
 375 static bool onehot(unsigned short value)
 376 {
 377         bool onehot;
 378
 379         onehot = value && !(value & (value - 1));
 380         return onehot;
 381 }
 382
 383 /*
 384  * zynq_nand_correct_data - ECC correction function
 385  * @mtd:        Pointer to the mtd_info structure
 386  * @buf:        Pointer to the page data
 387  * @read_ecc:   Pointer to the ECC value read from spare data area
 388  * @calc_ecc:   Pointer to the calculated ECC value
 389  *
 390  * This function corrects the ECC single bit errors & detects 2-bit errors.
 391  *
 392  * returns:     0 if no ECC errors found
 393  *              1 if single bit error found and corrected.
 394  *              -1 if multiple ECC errors found.
 395  */
 396 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
 397                         unsigned char *read_ecc, unsigned char *calc_ecc)
 398 {
 399         unsigned char bit_addr;
 400         unsigned int byte_addr;
 401         unsigned short ecc_odd, ecc_even;
 402         unsigned short read_ecc_lower, read_ecc_upper;
 403         unsigned short calc_ecc_lower, calc_ecc_upper;
 404
 405         read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
 406         read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
 407
 408         calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
 409         calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
 410
 411         ecc_odd = read_ecc_lower ^ calc_ecc_lower;
 412         ecc_even = read_ecc_upper ^ calc_ecc_upper;
 413
 414         if ((ecc_odd == 0) && (ecc_even == 0))
 415                 return 0;       /* no error */
 416
 417         if (ecc_odd == (~ecc_even & 0xfff)) {
 418                 /* bits [11:3] of error code is byte offset */
 419                 byte_addr = (ecc_odd >> 3) & 0x1ff;
 420                 /* bits [2:0] of error code is bit offset */
 421                 bit_addr = ecc_odd & 0x7;
 422                 /* Toggling error bit */
 423                 buf[byte_addr] ^= (1 << bit_addr);
 424                 return 1;
 425         }
 426
 427         if (onehot(ecc_odd | ecc_even))
 428                 return 1; /* one error in parity */
 429
 430         return -1; /* Uncorrectable error */
 431 }
 432
 433 /*
 434  * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
 435  * @mtd:        mtd info structure
 436  * @chip:       nand chip info structure
 437  * @page:       page number to read
 438  * @sndcmd:     flag whether to issue read command or not
 439  */
 440 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 441                         int page)
 442 {
 443         unsigned long data_phase_addr = 0;
 444         int data_width = 4;
 445         u8 *p;
 446
 447         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 448
 449         p = chip->oob_poi;
 450         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 451         p += mtd->oobsize - data_width;
 452
 453         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 454         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 455         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 456         chip->read_buf(mtd, p, data_width);
 457
 458         return 0;
 459 }
 460
 461 /*
 462  * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
 463  * @mtd:        mtd info structure
 464  * @chip:       nand chip info structure
 465  * @page:       page number to write
 466  */
 467 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 468                              int page)
 469 {
 470         int status = 0, data_width = 4;
 471         const u8 *buf = chip->oob_poi;
 472         unsigned long data_phase_addr = 0;
 473
 474         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 475
 476         chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
 477         buf += mtd->oobsize - data_width;
 478
 479         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 480         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 481         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 482         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 483         chip->write_buf(mtd, buf, data_width);
 484
 485         /* Send command to program the OOB data */
 486         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 487         status = chip->waitfunc(mtd, chip);
 488
 489         return status & NAND_STATUS_FAIL ? -EIO : 0;
 490 }
 491
 492 /*
 493  * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
 494  * @mtd:        mtd info structure
 495  * @chip:       nand chip info structure
 496  * @buf:        buffer to store read data
 497  * @oob_required: must write chip->oob_poi to OOB
 498  * @page:       page number to read
 499  */
 500 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 501                                    u8 *buf,  int oob_required, int page)
 502 {
 503         unsigned long data_width = 4;
 504         unsigned long data_phase_addr = 0;
 505         u8 *p;
 506
 507         chip->read_buf(mtd, buf, mtd->writesize);
 508
 509         p = chip->oob_poi;
 510         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 511         p += (mtd->oobsize - data_width);
 512
 513         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 514         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 515         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 516
 517         chip->read_buf(mtd, p, data_width);
 518         return 0;
 519 }
 520
 521 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
 522                 struct nand_chip *chip, u8 *buf, int oob_required, int page)
 523 {
 524         chip->read_buf(mtd, buf, mtd->writesize);
 525         return 0;
 526 }
 527
 528 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
 529                                     struct nand_chip *chip, u32 data_offs,
 530                                     u32 readlen, u8 *buf, int page)
 531 {
 532         if (data_offs != 0) {
 533                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
 534                 buf += data_offs;
 535         }
 536         chip->read_buf(mtd, buf, readlen);
 537
 538         return 0;
 539 }
 540
 541 /*
 542  * zynq_nand_write_page_raw - [Intern] raw page write function
 543  * @mtd:        mtd info structure
 544  * @chip:       nand chip info structure
 545  * @buf:        data buffer
 546  * @oob_required: must write chip->oob_poi to OOB
 547  */
 548 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
 549         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 550 {
 551         unsigned long data_width = 4;
 552         unsigned long data_phase_addr = 0;
 553         u8 *p;
 554
 555         chip->write_buf(mtd, buf, mtd->writesize);
 556
 557         p = chip->oob_poi;
 558         chip->write_buf(mtd, p, (mtd->oobsize - data_width));
 559         p += (mtd->oobsize - data_width);
 560
 561         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 562         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 563         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 564         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 565
 566         chip->write_buf(mtd, p, data_width);
 567
 568         return 0;
 569 }
 570
 571 /*
 572  * nand_write_page_hwecc - Hardware ECC based page write function
 573  * @mtd:        Pointer to the mtd info structure
 574  * @chip:       Pointer to the NAND chip info structure
 575  * @buf:        Pointer to the data buffer
 576  * @oob_required: must write chip->oob_poi to OOB
 577  *
 578  * This functions writes data and hardware generated ECC values in to the page.
 579  */
 580 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
 581         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 582 {
 583         int i, eccsteps, eccsize = chip->ecc.size;
 584         u8 *ecc_calc = chip->buffers->ecccalc;
 585         const u8 *p = buf;
 586         u32 *eccpos = chip->ecc.layout->eccpos;
 587         unsigned long data_phase_addr = 0;
 588         unsigned long data_width = 4;
 589         u8 *oob_ptr;
 590
 591         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 592                 chip->write_buf(mtd, p, eccsize);
 593                 p += eccsize;
 594         }
 595         chip->write_buf(mtd, p, (eccsize - data_width));
 596         p += eccsize - data_width;
 597
 598         /* Set ECC Last bit to 1 */
 599         data_phase_addr = (unsigned long) chip->IO_ADDR_W;
 600         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 601         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 602         chip->write_buf(mtd, p, data_width);
 603
 604         /* Wait for ECC to be calculated and read the error values */
 605         p = buf;
 606         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 607
 608         for (i = 0; i < chip->ecc.total; i++)
 609                 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
 610
 611         /* Clear ECC last bit */
 612         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 613         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 614         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 615
 616         /* Write the spare area with ECC bytes */
 617         oob_ptr = chip->oob_poi;
 618         chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 619
 620         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 621         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 622         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 623         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 624         oob_ptr += (mtd->oobsize - data_width);
 625         chip->write_buf(mtd, oob_ptr, data_width);
 626
 627         return 0;
 628 }
 629
 630 /*
 631  * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
 632  * write function
 633  * @mtd:        mtd info structure
 634  * @chip:       nand chip info structure
 635  * @buf:        data buffer
 636  * @oob_required: must write chip->oob_poi to OOB
 637  */
 638 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
 639         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 640 {
 641         int i, eccsize = chip->ecc.size;
 642         int eccbytes = chip->ecc.bytes;
 643         int eccsteps = chip->ecc.steps;
 644         u8 *ecc_calc = chip->buffers->ecccalc;
 645         const u8 *p = buf;
 646         u32 *eccpos = chip->ecc.layout->eccpos;
 647
 648         /* Software ecc calculation */
 649         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 650                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 651
 652         for (i = 0; i < chip->ecc.total; i++)
 653                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
 654
 655         return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 656 }
 657
 658 /*
 659  * nand_read_page_hwecc - Hardware ECC based page read function
 660  * @mtd:        Pointer to the mtd info structure
 661  * @chip:       Pointer to the NAND chip info structure
 662  * @buf:        Pointer to the buffer to store read data
 663  * @oob_required: must write chip->oob_poi to OOB
 664  * @page:       page number to read
 665  *
 666  * This functions reads data and checks the data integrity by comparing hardware
 667  * generated ECC values and read ECC values from spare area.
 668  *
 669  * returns:     0 always and updates ECC operation status in to MTD structure
 670  */
 671 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
 672         struct nand_chip *chip, u8 *buf, int oob_required, int page)
 673 {
 674         int i, stat, eccsteps, eccsize = chip->ecc.size;
 675         int eccbytes = chip->ecc.bytes;
 676         u8 *p = buf;
 677         u8 *ecc_calc = chip->buffers->ecccalc;
 678         u8 *ecc_code = chip->buffers->ecccode;
 679         u32 *eccpos = chip->ecc.layout->eccpos;
 680         unsigned long data_phase_addr = 0;
 681         unsigned long data_width = 4;
 682         u8 *oob_ptr;
 683
 684         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 685                 chip->read_buf(mtd, p, eccsize);
 686                 p += eccsize;
 687         }
 688         chip->read_buf(mtd, p, (eccsize - data_width));
 689         p += eccsize - data_width;
 690
 691         /* Set ECC Last bit to 1 */
 692         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 693         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 694         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 695         chip->read_buf(mtd, p, data_width);
 696
 697         /* Read the calculated ECC value */
 698         p = buf;
 699         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 700
 701         /* Clear ECC last bit */
 702         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 703         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 704         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 705
 706         /* Read the stored ECC value */
 707         oob_ptr = chip->oob_poi;
 708         chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 709
 710         /* de-assert chip select */
 711         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 712         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 713         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 714
 715         oob_ptr += (mtd->oobsize - data_width);
 716         chip->read_buf(mtd, oob_ptr, data_width);
 717
 718         for (i = 0; i < chip->ecc.total; i++)
 719                 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
 720
 721         eccsteps = chip->ecc.steps;
 722         p = buf;
 723
 724         /* Check ECC error for all blocks and correct if it is correctable */
 725         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 726                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 727                 if (stat < 0)
 728                         mtd->ecc_stats.failed++;
 729                 else
 730                         mtd->ecc_stats.corrected += stat;
 731         }
 732         return 0;
 733 }
 734
 735 /*
 736  * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
 737  * read function
 738  * @mtd:        mtd info structure
 739  * @chip:       nand chip info structure
 740  * @buf:        buffer to store read data
 741  * @page:       page number to read
 742  */
 743 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
 744         struct nand_chip *chip, u8 *buf, int oob_required,  int page)
 745 {
 746         int i, eccsize = chip->ecc.size;
 747         int eccbytes = chip->ecc.bytes;
 748         int eccsteps = chip->ecc.steps;
 749         u8 *p = buf;
 750         u8 *ecc_calc = chip->buffers->ecccalc;
 751         u8 *ecc_code = chip->buffers->ecccode;
 752         u32 *eccpos = chip->ecc.layout->eccpos;
 753
 754         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 755
 756         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 757                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 758
 759         for (i = 0; i < chip->ecc.total; i++)
 760                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 761
 762         eccsteps = chip->ecc.steps;
 763         p = buf;
 764
 765         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 766                 int stat;
 767
 768                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 769                 if (stat < 0)
 770                         mtd->ecc_stats.failed++;
 771                 else
 772                         mtd->ecc_stats.corrected += stat;
 773         }
 774         return 0;
 775 }
 776
 777 /*
 778  * zynq_nand_select_chip - Select the flash device
 779  * @mtd:        Pointer to the mtd_info structure
 780  * @chip:       Chip number to be selected
 781  *
 782  * This function is empty as the NAND controller handles chip select line
 783  * internally based on the chip address passed in command and data phase.
 784  */
 785 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
 786 {
 787         /* Not support multiple chips yet */
 788 }
 789
 790 /*
 791  * zynq_nand_cmd_function - Send command to NAND device
 792  * @mtd:        Pointer to the mtd_info structure
 793  * @command:    The command to be sent to the flash device
 794  * @column:     The column address for this command, -1 if none
 795  * @page_addr:  The page address for this command, -1 if none
 796  */
 797 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 798                                  int column, int page_addr)
 799 {
 800         struct nand_chip *chip = mtd_to_nand(mtd);
 801         struct nand_drv *smc = nand_get_controller_data(chip);
 802         const struct zynq_nand_command_format *curr_cmd = NULL;
 803         u8 addr_cycles = 0;
 804         struct nand_config *xnand = &smc->config;
 805         void *cmd_addr;
 806         unsigned long cmd_data = 0;
 807         unsigned long cmd_phase_addr = 0;
 808         unsigned long data_phase_addr = 0;
 809         u8 end_cmd = 0;
 810         u8 end_cmd_valid = 0;
 811         u32 index;
 812
 813         if (xnand->end_cmd_pending) {
 814                 /* Check for end command if this command request is same as the
 815                  * pending command then return
 816                  */
 817                 if (xnand->end_cmd == command) {
 818                         xnand->end_cmd = 0;
 819                         xnand->end_cmd_pending = 0;
 820                         return;
 821                 }
 822         }
 823
 824         /* Emulate NAND_CMD_READOOB for large page device */
 825         if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
 826             (command == NAND_CMD_READOOB)) {
 827                 column += mtd->writesize;
 828                 command = NAND_CMD_READ0;
 829         }
 830
 831         /* Get the command format */
 832         for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
 833                 if (command == zynq_nand_commands[index].start_cmd)
 834                         break;
 835
 836         if (index == ARRAY_SIZE(zynq_nand_commands)) {
 837                 printf("%s: Unsupported start cmd %02x\n", __func__, command);
 838                 return;
 839         }
 840         curr_cmd = &zynq_nand_commands[index];
 841
 842         /* Clear interrupt */
 843         writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &smc->reg->cfr);
 844
 845         /* Get the command phase address */
 846         if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
 847                 end_cmd_valid = 1;
 848
 849         if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE)
 850                 end_cmd = 0x0;
 851         else
 852                 end_cmd = curr_cmd->end_cmd;
 853
 854         if (command == NAND_CMD_READ0 ||
 855             command == NAND_CMD_SEQIN) {
 856                 addr_cycles = chip->onfi_params.addr_cycles &
 857                                 ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
 858                 addr_cycles += ((chip->onfi_params.addr_cycles &
 859                                 ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
 860         } else {
 861                 addr_cycles = curr_cmd->addr_cycles;
 862         }
 863
 864         cmd_phase_addr = (unsigned long)xnand->nand_base        |
 865                         (addr_cycles << ADDR_CYCLES_SHIFT)      |
 866                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 867                         (COMMAND_PHASE)                                 |
 868                         (end_cmd << END_CMD_SHIFT)                      |
 869                         (curr_cmd->start_cmd << START_CMD_SHIFT);
 870
 871         cmd_addr = (void __iomem *)cmd_phase_addr;
 872
 873         /* Get the data phase address */
 874         end_cmd_valid = 0;
 875
 876         data_phase_addr = (unsigned long)xnand->nand_base       |
 877                         (0x0 << CLEAR_CS_SHIFT)                         |
 878                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 879                         (DATA_PHASE)                                    |
 880                         (end_cmd << END_CMD_SHIFT)                      |
 881                         (0x0 << ECC_LAST_SHIFT);
 882
 883         chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
 884         chip->IO_ADDR_W = chip->IO_ADDR_R;
 885
 886         /* Command phase AXI Read & Write */
 887         if (column != -1 && page_addr != -1) {
 888                 /* Adjust columns for 16 bit bus width */
 889                 if (chip->options & NAND_BUSWIDTH_16)
 890                         column >>= 1;
 891                 cmd_data = column;
 892                 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
 893                         cmd_data |= page_addr << 16;
 894                         /* Another address cycle for devices > 128MiB */
 895                         if (chip->chipsize > (128 << 20)) {
 896                                 writel(cmd_data, cmd_addr);
 897                                 cmd_data = (page_addr >> 16);
 898                         }
 899                 } else {
 900                         cmd_data |= page_addr << 8;
 901                 }
 902         } else if (page_addr != -1)  { /* Erase */
 903                 cmd_data = page_addr;
 904         } else if (column != -1) { /* Change read/write column, read id etc */
 905                 /* Adjust columns for 16 bit bus width */
 906                 if ((chip->options & NAND_BUSWIDTH_16) &&
 907                     ((command == NAND_CMD_READ0) ||
 908                      (command == NAND_CMD_SEQIN) ||
 909                      (command == NAND_CMD_RNDOUT) ||
 910                      (command == NAND_CMD_RNDIN)))
 911                         column >>= 1;
 912                 cmd_data = column;
 913         }
 914
 915         writel(cmd_data, cmd_addr);
 916
 917         if (curr_cmd->end_cmd_valid) {
 918                 xnand->end_cmd = curr_cmd->end_cmd;
 919                 xnand->end_cmd_pending = 1;
 920         }
 921
 922         ndelay(100);
 923
 924         if ((command == NAND_CMD_READ0) ||
 925             (command == NAND_CMD_RESET) ||
 926             (command == NAND_CMD_PARAM) ||
 927             (command == NAND_CMD_GET_FEATURES))
 928                 /* wait until command is processed */
 929                 nand_wait_ready(mtd);
 930 }
 931
 932 /*
 933  * zynq_nand_read_buf - read chip data into buffer
 934  * @mtd:        MTD device structure
 935  * @buf:        buffer to store date
 936  * @len:        number of bytes to read
 937  */
 938 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 939 {
 940         struct nand_chip *chip = mtd_to_nand(mtd);
 941
 942         /* Make sure that buf is 32 bit aligned */
 943         if (((unsigned long)buf & 0x3) != 0) {
 944                 if (((unsigned long)buf & 0x1) != 0) {
 945                         if (len) {
 946                                 *buf = readb(chip->IO_ADDR_R);
 947                                 buf += 1;
 948                                 len--;
 949                         }
 950                 }
 951
 952                 if (((unsigned long)buf & 0x3) != 0) {
 953                         if (len >= 2) {
 954                                 *(u16 *)buf = readw(chip->IO_ADDR_R);
 955                                 buf += 2;
 956                                 len -= 2;
 957                         }
 958                 }
 959         }
 960
 961         /* copy aligned data */
 962         while (len >= 4) {
 963                 *(u32 *)buf = readl(chip->IO_ADDR_R);
 964                 buf += 4;
 965                 len -= 4;
 966         }
 967
 968         /* mop up any remaining bytes */
 969         if (len) {
 970                 if (len >= 2) {
 971                         *(u16 *)buf = readw(chip->IO_ADDR_R);
 972                         buf += 2;
 973                         len -= 2;
 974                 }
 975                 if (len)
 976                         *buf = readb(chip->IO_ADDR_R);
 977         }
 978 }
 979
 980 /*
 981  * zynq_nand_write_buf - write buffer to chip
 982  * @mtd:        MTD device structure
 983  * @buf:        data buffer
 984  * @len:        number of bytes to write
 985  */
 986 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 987 {
 988         struct nand_chip *chip = mtd_to_nand(mtd);
 989         const u32 *nand = chip->IO_ADDR_W;
 990
 991         /* Make sure that buf is 32 bit aligned */
 992         if (((unsigned long)buf & 0x3) != 0) {
 993                 if (((unsigned long)buf & 0x1) != 0) {
 994                         if (len) {
 995                                 writeb(*buf, nand);
 996                                 buf += 1;
 997                                 len--;
 998                         }
 999                 }
1000
1001                 if (((unsigned long)buf & 0x3) != 0) {
1002                         if (len >= 2) {
1003                                 writew(*(u16 *)buf, nand);
1004                                 buf += 2;
1005                                 len -= 2;
1006                         }
1007                 }
1008         }
1009
1010         /* copy aligned data */
1011         while (len >= 4) {
1012                 writel(*(u32 *)buf, nand);
1013                 buf += 4;
1014                 len -= 4;
1015         }
1016
1017         /* mop up any remaining bytes */
1018         if (len) {
1019                 if (len >= 2) {
1020                         writew(*(u16 *)buf, nand);
1021                         buf += 2;
1022                         len -= 2;
1023                 }
1024
1025                 if (len)
1026                         writeb(*buf, nand);
1027         }
1028 }
1029
1030 /*
1031  * zynq_nand_device_ready - Check device ready/busy line
1032  * @mtd:        Pointer to the mtd_info structure
1033  *
1034  * returns:     0 on busy or 1 on ready state
1035  */
1036 static int zynq_nand_device_ready(struct mtd_info *mtd)
1037 {
1038         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1039         struct nand_drv *smc = nand_get_controller_data(nand_chip);
1040         u32 csr_val;
1041
1042         csr_val = readl(&smc->reg->csr);
1043         /* Check the raw_int_status1 bit */
1044         if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
1045                 /* Clear the interrupt condition */
1046                 writel(ZYNQ_MEMC_SR_INT_ST1, &smc->reg->cfr);
1047                 return 1;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int zynq_nand_check_is_16bit_bw_flash(void)
1054 {
1055         int is_16bit_bw = NAND_BW_UNKNOWN;
1056         int mio_num_8bit = 0, mio_num_16bit = 0;
1057
1058         mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
1059         if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
1060                 is_16bit_bw = NAND_BW_8BIT;
1061
1062         mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
1063         if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
1064             mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
1065                 is_16bit_bw = NAND_BW_16BIT;
1066
1067         return is_16bit_bw;
1068 }
1069
1070 static int zynq_nand_probe(struct udevice *dev)
1071 {
1072         struct zynq_nand_info *zynq = dev_get_priv(dev);
1073         struct nand_chip *nand_chip = &zynq->nand_chip;
1074         struct nand_drv *smc = &zynq->nand_ctrl;
1075         struct nand_config *xnand = &smc->config;
1076         struct mtd_info *mtd;
1077         struct resource res;
1078         ofnode of_nand;
1079         unsigned long ecc_page_size;
1080         u8 maf_id, dev_id, i;
1081         u8 get_feature[4];
1082         u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1083         unsigned long ecc_cfg;
1084         int ondie_ecc_enabled = 0;
1085         int is_16bit_bw;
1086
1087         smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
1088         of_nand = dev_read_subnode(dev, "flash@e1000000");
1089         if (!ofnode_valid(of_nand)) {
1090                 printf("Failed to find nand node in dt\n");
1091                 return -ENODEV;
1092         }
1093
1094         if (!ofnode_is_available(of_nand)) {
1095                 debug("Nand node in dt disabled\n");
1096                 return dm_scan_fdt_dev(dev);
1097         }
1098
1099         if (ofnode_read_resource(of_nand, 0, &res)) {
1100                 printf("Failed to get nand resource\n");
1101                 return -ENODEV;
1102         }
1103
1104         xnand->nand_base = (void __iomem *)res.start;
1105         mtd = nand_to_mtd(nand_chip);
1106         nand_set_controller_data(nand_chip, &zynq->nand_ctrl);
1107
1108         /* Set address of NAND IO lines */
1109         nand_chip->IO_ADDR_R = xnand->nand_base;
1110         nand_chip->IO_ADDR_W = xnand->nand_base;
1111
1112         /* Set the driver entry points for MTD */
1113         nand_chip->cmdfunc = zynq_nand_cmd_function;
1114         nand_chip->dev_ready = zynq_nand_device_ready;
1115         nand_chip->select_chip = zynq_nand_select_chip;
1116
1117         /* If we don't set this delay driver sets 20us by default */
1118         nand_chip->chip_delay = 30;
1119
1120         /* Buffer read/write routines */
1121         nand_chip->read_buf = zynq_nand_read_buf;
1122         nand_chip->write_buf = zynq_nand_write_buf;
1123
1124         is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
1125         if (is_16bit_bw == NAND_BW_UNKNOWN) {
1126                 printf("%s: Unable detect NAND based on MIO settings\n",
1127                        __func__);
1128                 return -EINVAL;
1129         }
1130
1131         if (is_16bit_bw == NAND_BW_16BIT)
1132                 nand_chip->options = NAND_BUSWIDTH_16;
1133
1134         nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1135
1136         /* Initialize the NAND flash interface on NAND controller */
1137         if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) {
1138                 printf("%s: nand flash init failed\n", __func__);
1139                 return -EINVAL;
1140         }
1141
1142         /* first scan to find the device and get the page size */
1143         if (nand_scan_ident(mtd, 1, NULL)) {
1144                 printf("%s: nand_scan_ident failed\n", __func__);
1145                 return -EINVAL;
1146         }
1147         /* Send the command for reading device ID */
1148         nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1149         nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1150
1151         /* Read manufacturer and device IDs */
1152         maf_id = nand_chip->read_byte(mtd);
1153         dev_id = nand_chip->read_byte(mtd);
1154
1155         if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1156                                  (dev_id == 0xa1) || (dev_id == 0xb1) ||
1157                                  (dev_id == 0xaa) || (dev_id == 0xba) ||
1158                                  (dev_id == 0xda) || (dev_id == 0xca) ||
1159                                  (dev_id == 0xac) || (dev_id == 0xbc) ||
1160                                  (dev_id == 0xdc) || (dev_id == 0xcc) ||
1161                                  (dev_id == 0xa3) || (dev_id == 0xb3) ||
1162                                  (dev_id == 0xd3) || (dev_id == 0xc3))) {
1163                 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1164                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1165                 for (i = 0; i < 4; i++)
1166                         writeb(set_feature[i], nand_chip->IO_ADDR_W);
1167
1168                 /* Wait for 1us after writing data with SET_FEATURES command */
1169                 ndelay(1000);
1170
1171                 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1172                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1173                 nand_chip->read_buf(mtd, get_feature, 4);
1174
1175                 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1176                         debug("%s: OnDie ECC flash\n", __func__);
1177                         ondie_ecc_enabled = 1;
1178                 } else {
1179                         printf("%s: Unable to detect OnDie ECC\n", __func__);
1180                 }
1181         }
1182
1183         if (ondie_ecc_enabled) {
1184                 /* Bypass the controller ECC block */
1185                 ecc_cfg = readl(&smc->reg->emcr);
1186                 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1187                 writel(ecc_cfg, &smc->reg->emcr);
1188
1189                 /* The software ECC routines won't work
1190                  * with the SMC controller
1191                  */
1192                 nand_chip->ecc.mode = NAND_ECC_HW;
1193                 nand_chip->ecc.strength = 1;
1194                 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1195                 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1196                 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1197                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1198                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1199                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1200                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1201                 nand_chip->ecc.size = mtd->writesize;
1202                 nand_chip->ecc.bytes = 0;
1203
1204                 /* NAND with on-die ECC supports subpage reads */
1205                 nand_chip->options |= NAND_SUBPAGE_READ;
1206
1207                 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1208                 if (ondie_ecc_enabled) {
1209                         nand_chip->ecc.layout = &ondie_nand_oob_64;
1210                         /* Use the BBT pattern descriptors */
1211                         nand_chip->bbt_td = &bbt_main_descr;
1212                         nand_chip->bbt_md = &bbt_mirror_descr;
1213                 }
1214         } else {
1215                 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1216                 nand_chip->ecc.mode = NAND_ECC_HW;
1217                 nand_chip->ecc.strength = 1;
1218                 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1219                 nand_chip->ecc.bytes = 3;
1220                 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1221                 nand_chip->ecc.correct = zynq_nand_correct_data;
1222                 nand_chip->ecc.hwctl = NULL;
1223                 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1224                 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1225                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1226                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1227                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1228                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1229
1230                 switch (mtd->writesize) {
1231                 case 512:
1232                         ecc_page_size = 0x1;
1233                         /* Set the ECC memory config register */
1234                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1235                                &smc->reg->emcr);
1236                         break;
1237                 case 1024:
1238                         ecc_page_size = 0x2;
1239                         /* Set the ECC memory config register */
1240                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1241                                &smc->reg->emcr);
1242                         break;
1243                 case 2048:
1244                         ecc_page_size = 0x3;
1245                         /* Set the ECC memory config register */
1246                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1247                                &smc->reg->emcr);
1248                         break;
1249                 default:
1250                         nand_chip->ecc.mode = NAND_ECC_SOFT;
1251                         nand_chip->ecc.calculate = nand_calculate_ecc;
1252                         nand_chip->ecc.correct = nand_correct_data;
1253                         nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1254                         nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1255                         nand_chip->ecc.size = 256;
1256                         break;
1257                 }
1258
1259                 if (mtd->oobsize == 16)
1260                         nand_chip->ecc.layout = &nand_oob_16;
1261                 else if (mtd->oobsize == 64)
1262                         nand_chip->ecc.layout = &nand_oob_64;
1263                 else
1264                         printf("%s: No oob layout found\n", __func__);
1265         }
1266
1267         /* Second phase scan */
1268         if (nand_scan_tail(mtd)) {
1269                 printf("%s: nand_scan_tail failed\n", __func__);
1270                 return -EINVAL;
1271         }
1272         if (nand_register(0, mtd))
1273                 return -EINVAL;
1274
1275         return 0;
1276 }
1277
1278 static const struct udevice_id zynq_nand_dt_ids[] = {
1279         {.compatible = "arm,pl353-smc-r2p1",},
1280         { /* sentinel */ }
1281 };
1282
1283 U_BOOT_DRIVER(zynq_nand) = {
1284         .name = "zynq-nand",
1285         .id = UCLASS_MTD,
1286         .of_match = zynq_nand_dt_ids,
1287         .probe = zynq_nand_probe,
1288         .priv_auto_alloc_size = sizeof(struct zynq_nand_info),
1289 };
1290
1291 void board_nand_init(void)
1292 {
1293         struct udevice *dev;
1294         int ret;
1295
1296         ret = uclass_get_device_by_driver(UCLASS_MTD,
1297                                           DM_GET_DRIVER(zynq_nand), &dev);
1298         if (ret && ret != -ENODEV)
1299                 pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
1300 }