drivers/mtd/nand/raw/tegra_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
   5  * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
   6  * (C) Copyright 2006 DENX Software Engineering
   7  */
   8
   9 #include <common.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <memalign.h>
  13 #include <nand.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/funcmux.h>
  16 #include <asm/arch-tegra/clk_rst.h>
  17 #include <dm/device_compat.h>
  18 #include <linux/bug.h>
  19 #include <linux/errno.h>
  20 #include <asm/gpio.h>
  21 #include <fdtdec.h>
  22 #include <bouncebuf.h>
  23 #include <dm.h>
  24 #include "tegra_nand.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define NAND_CMD_TIMEOUT_MS             10
  29
  30 #define SKIPPED_SPARE_BYTES             4
  31
  32 /* ECC bytes to be generated for tag data */
  33 #define TAG_ECC_BYTES                   4
  34
  35 static const struct udevice_id tegra_nand_dt_ids[] = {
  36         {
  37                 .compatible = "nvidia,tegra20-nand",
  38         },
  39         { /* sentinel */ }
  40 };
  41
  42 /* 64 byte oob block info for large page (== 2KB) device
  43  *
  44  * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  45  *      Skipped bytes(4)
  46  *      Main area Ecc(36)
  47  *      Tag data(20)
  48  *      Tag data Ecc(4)
  49  *
  50  * Yaffs2 will use 16 tag bytes.
  51  */
  52 static struct nand_ecclayout eccoob = {
  53         .eccbytes = 36,
  54         .eccpos = {
  55                 4,  5,  6,  7,  8,  9,  10, 11, 12,
  56                 13, 14, 15, 16, 17, 18, 19, 20, 21,
  57                 22, 23, 24, 25, 26, 27, 28, 29, 30,
  58                 31, 32, 33, 34, 35, 36, 37, 38, 39,
  59         },
  60         .oobavail = 20,
  61         .oobfree = {
  62                         {
  63                         .offset = 40,
  64                         .length = 20,
  65                         },
  66         }
  67 };
  68
  69 enum {
  70         ECC_OK,
  71         ECC_TAG_ERROR = 1 << 0,
  72         ECC_DATA_ERROR = 1 << 1
  73 };
  74
  75 /* Timing parameters */
  76 enum {
  77         FDT_NAND_MAX_TRP_TREA,
  78         FDT_NAND_TWB,
  79         FDT_NAND_MAX_TCR_TAR_TRR,
  80         FDT_NAND_TWHR,
  81         FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  82         FDT_NAND_TWH,
  83         FDT_NAND_TWP,
  84         FDT_NAND_TRH,
  85         FDT_NAND_TADL,
  86
  87         FDT_NAND_TIMING_COUNT
  88 };
  89
  90 /* Information about an attached NAND chip */
  91 struct fdt_nand {
  92         struct nand_ctlr *reg;
  93         int enabled;            /* 1 to enable, 0 to disable */
  94         struct gpio_desc wp_gpio;       /* write-protect GPIO */
  95         s32 width;              /* bit width, normally 8 */
  96         u32 timing[FDT_NAND_TIMING_COUNT];
  97 };
  98
  99 struct nand_drv {
 100         struct nand_ctlr *reg;
 101         struct fdt_nand config;
 102 };
 103
 104 struct tegra_nand_info {
 105         struct udevice *dev;
 106         struct nand_drv nand_ctrl;
 107         struct nand_chip nand_chip;
 108 };
 109
 110 /**
 111  * Wait for command completion
 112  *
 113  * @param reg   nand_ctlr structure
 114  * @return
 115  *      1 - Command completed
 116  *      0 - Timeout
 117  */
 118 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
 119 {
 120         u32 reg_val;
 121         int running;
 122         int i;
 123
 124         for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
 125                 if ((readl(&reg->command) & CMD_GO) ||
 126                                 !(readl(&reg->status) & STATUS_RBSY0) ||
 127                                 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
 128                         udelay(1);
 129                         continue;
 130                 }
 131                 reg_val = readl(&reg->dma_mst_ctrl);
 132                 /*
 133                  * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
 134                  * is set, that means DMA engine is running.
 135                  *
 136                  * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
 137                  * is cleared, indicating DMA transfer completion.
 138                  */
 139                 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
 140                                 DMA_MST_CTRL_EN_B_ENABLE);
 141                 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
 142                         return 1;
 143                 udelay(1);
 144         }
 145         return 0;
 146 }
 147
 148 /**
 149  * Read one byte from the chip
 150  *
 151  * @param mtd   MTD device structure
 152  * @return      data byte
 153  *
 154  * Read function for 8bit bus-width
 155  */
 156 static uint8_t read_byte(struct mtd_info *mtd)
 157 {
 158         struct nand_chip *chip = mtd_to_nand(mtd);
 159         struct nand_drv *info;
 160
 161         info = (struct nand_drv *)nand_get_controller_data(chip);
 162
 163         writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
 164                &info->reg->command);
 165         if (!nand_waitfor_cmd_completion(info->reg))
 166                 printf("Command timeout\n");
 167
 168         return (uint8_t)readl(&info->reg->resp);
 169 }
 170
 171 /**
 172  * Read len bytes from the chip into a buffer
 173  *
 174  * @param mtd   MTD device structure
 175  * @param buf   buffer to store data to
 176  * @param len   number of bytes to read
 177  *
 178  * Read function for 8bit bus-width
 179  */
 180 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 181 {
 182         int i, s;
 183         unsigned int reg;
 184         struct nand_chip *chip = mtd_to_nand(mtd);
 185         struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
 186
 187         for (i = 0; i < len; i += 4) {
 188                 s = (len - i) > 4 ? 4 : len - i;
 189                 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
 190                         ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
 191                         &info->reg->command);
 192                 if (!nand_waitfor_cmd_completion(info->reg))
 193                         puts("Command timeout during read_buf\n");
 194                 reg = readl(&info->reg->resp);
 195                 memcpy(buf + i, &reg, s);
 196         }
 197 }
 198
 199 /**
 200  * Check NAND status to see if it is ready or not
 201  *
 202  * @param mtd   MTD device structure
 203  * @return
 204  *      1 - ready
 205  *      0 - not ready
 206  */
 207 static int nand_dev_ready(struct mtd_info *mtd)
 208 {
 209         struct nand_chip *chip = mtd_to_nand(mtd);
 210         int reg_val;
 211         struct nand_drv *info;
 212
 213         info = (struct nand_drv *)nand_get_controller_data(chip);
 214
 215         reg_val = readl(&info->reg->status);
 216         if (reg_val & STATUS_RBSY0)
 217                 return 1;
 218         else
 219                 return 0;
 220 }
 221
 222 /* Dummy implementation: we don't support multiple chips */
 223 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 224 {
 225         switch (chipnr) {
 226         case -1:
 227         case 0:
 228                 break;
 229
 230         default:
 231                 BUG();
 232         }
 233 }
 234
 235 /**
 236  * Clear all interrupt status bits
 237  *
 238  * @param reg   nand_ctlr structure
 239  */
 240 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
 241 {
 242         u32 reg_val;
 243
 244         /* Clear interrupt status */
 245         reg_val = readl(&reg->isr);
 246         writel(reg_val, &reg->isr);
 247 }
 248
 249 /**
 250  * Send command to NAND device
 251  *
 252  * @param mtd           MTD device structure
 253  * @param command       the command to be sent
 254  * @param column        the column address for this command, -1 if none
 255  * @param page_addr     the page address for this command, -1 if none
 256  */
 257 static void nand_command(struct mtd_info *mtd, unsigned int command,
 258         int column, int page_addr)
 259 {
 260         struct nand_chip *chip = mtd_to_nand(mtd);
 261         struct nand_drv *info;
 262
 263         info = (struct nand_drv *)nand_get_controller_data(chip);
 264
 265         /*
 266          * Write out the command to the device.
 267          *
 268          * Only command NAND_CMD_RESET or NAND_CMD_READID will come
 269          * here before mtd->writesize is initialized.
 270          */
 271
 272         /* Emulate NAND_CMD_READOOB */
 273         if (command == NAND_CMD_READOOB) {
 274                 assert(mtd->writesize != 0);
 275                 column += mtd->writesize;
 276                 command = NAND_CMD_READ0;
 277         }
 278
 279         /* Adjust columns for 16 bit bus-width */
 280         if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
 281                 column >>= 1;
 282
 283         nand_clear_interrupt_status(info->reg);
 284
 285         /* Stop DMA engine, clear DMA completion status */
 286         writel(DMA_MST_CTRL_EN_A_DISABLE
 287                 | DMA_MST_CTRL_EN_B_DISABLE
 288                 | DMA_MST_CTRL_IS_DMA_DONE,
 289                 &info->reg->dma_mst_ctrl);
 290
 291         /*
 292          * Program and erase have their own busy handlers
 293          * status and sequential in needs no delay
 294          */
 295         switch (command) {
 296         case NAND_CMD_READID:
 297                 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
 298                 writel(column & 0xFF, &info->reg->addr_reg1);
 299                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 300                        &info->reg->command);
 301                 break;
 302         case NAND_CMD_PARAM:
 303                 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
 304                 writel(column & 0xFF, &info->reg->addr_reg1);
 305                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 306                         &info->reg->command);
 307                 break;
 308         case NAND_CMD_READ0:
 309                 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
 310                 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
 311                 writel((page_addr << 16) | (column & 0xFFFF),
 312                         &info->reg->addr_reg1);
 313                 writel(page_addr >> 16, &info->reg->addr_reg2);
 314                 return;
 315         case NAND_CMD_SEQIN:
 316                 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
 317                 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
 318                 writel((page_addr << 16) | (column & 0xFFFF),
 319                         &info->reg->addr_reg1);
 320                 writel(page_addr >> 16,
 321                         &info->reg->addr_reg2);
 322                 return;
 323         case NAND_CMD_PAGEPROG:
 324                 return;
 325         case NAND_CMD_ERASE1:
 326                 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
 327                 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
 328                 writel(page_addr, &info->reg->addr_reg1);
 329                 writel(CMD_GO | CMD_CLE | CMD_ALE |
 330                         CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
 331                         &info->reg->command);
 332                 break;
 333         case NAND_CMD_ERASE2:
 334                 return;
 335         case NAND_CMD_STATUS:
 336                 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
 337                 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
 338                         | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
 339                         | CMD_CE0,
 340                         &info->reg->command);
 341                 break;
 342         case NAND_CMD_RESET:
 343                 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
 344                 writel(CMD_GO | CMD_CLE | CMD_CE0,
 345                         &info->reg->command);
 346                 break;
 347         case NAND_CMD_RNDOUT:
 348         default:
 349                 printf("%s: Unsupported command %d\n", __func__, command);
 350                 return;
 351         }
 352         if (!nand_waitfor_cmd_completion(info->reg))
 353                 printf("Command 0x%02X timeout\n", command);
 354 }
 355
 356 /**
 357  * Check whether the pointed buffer are all 0xff (blank).
 358  *
 359  * @param buf   data buffer for blank check
 360  * @param len   length of the buffer in byte
 361  * @return
 362  *      1 - blank
 363  *      0 - non-blank
 364  */
 365 static int blank_check(u8 *buf, int len)
 366 {
 367         int i;
 368
 369         for (i = 0; i < len; i++)
 370                 if (buf[i] != 0xFF)
 371                         return 0;
 372         return 1;
 373 }
 374
 375 /**
 376  * After a DMA transfer for read, we call this function to see whether there
 377  * is any uncorrectable error on the pointed data buffer or oob buffer.
 378  *
 379  * @param reg           nand_ctlr structure
 380  * @param databuf       data buffer
 381  * @param a_len         data buffer length
 382  * @param oobbuf        oob buffer
 383  * @param b_len         oob buffer length
 384  * @return
 385  *      ECC_OK - no ECC error or correctable ECC error
 386  *      ECC_TAG_ERROR - uncorrectable tag ECC error
 387  *      ECC_DATA_ERROR - uncorrectable data ECC error
 388  *      ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
 389  */
 390 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
 391         int a_len, u8 *oobbuf, int b_len)
 392 {
 393         int return_val = ECC_OK;
 394         u32 reg_val;
 395
 396         if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
 397                 return ECC_OK;
 398
 399         /*
 400          * Area A is used for the data block (databuf). Area B is used for
 401          * the spare block (oobbuf)
 402          */
 403         reg_val = readl(&reg->dec_status);
 404         if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
 405                 reg_val = readl(&reg->bch_dec_status_buf);
 406                 /*
 407                  * If uncorrectable error occurs on data area, then see whether
 408                  * they are all FF. If all are FF, it's a blank page.
 409                  * Not error.
 410                  */
 411                 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
 412                                 !blank_check(databuf, a_len))
 413                         return_val |= ECC_DATA_ERROR;
 414         }
 415
 416         if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
 417                 reg_val = readl(&reg->bch_dec_status_buf);
 418                 /*
 419                  * If uncorrectable error occurs on tag area, then see whether
 420                  * they are all FF. If all are FF, it's a blank page.
 421                  * Not error.
 422                  */
 423                 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
 424                                 !blank_check(oobbuf, b_len))
 425                         return_val |= ECC_TAG_ERROR;
 426         }
 427
 428         return return_val;
 429 }
 430
 431 /**
 432  * Set GO bit to send command to device
 433  *
 434  * @param reg   nand_ctlr structure
 435  */
 436 static void start_command(struct nand_ctlr *reg)
 437 {
 438         u32 reg_val;
 439
 440         reg_val = readl(&reg->command);
 441         reg_val |= CMD_GO;
 442         writel(reg_val, &reg->command);
 443 }
 444
 445 /**
 446  * Clear command GO bit, DMA GO bit, and DMA completion status
 447  *
 448  * @param reg   nand_ctlr structure
 449  */
 450 static void stop_command(struct nand_ctlr *reg)
 451 {
 452         /* Stop command */
 453         writel(0, &reg->command);
 454
 455         /* Stop DMA engine and clear DMA completion status */
 456         writel(DMA_MST_CTRL_GO_DISABLE
 457                 | DMA_MST_CTRL_IS_DMA_DONE,
 458                 &reg->dma_mst_ctrl);
 459 }
 460
 461 /**
 462  * Set up NAND bus width and page size
 463  *
 464  * @param info          nand_info structure
 465  * @param *reg_val      address of reg_val
 466  * @return 0 if ok, -1 on error
 467  */
 468 static int set_bus_width_page_size(struct mtd_info *our_mtd,
 469                                    struct fdt_nand *config, u32 *reg_val)
 470 {
 471         if (config->width == 8)
 472                 *reg_val = CFG_BUS_WIDTH_8BIT;
 473         else if (config->width == 16)
 474                 *reg_val = CFG_BUS_WIDTH_16BIT;
 475         else {
 476                 debug("%s: Unsupported bus width %d\n", __func__,
 477                       config->width);
 478                 return -1;
 479         }
 480
 481         if (our_mtd->writesize == 512)
 482                 *reg_val |= CFG_PAGE_SIZE_512;
 483         else if (our_mtd->writesize == 2048)
 484                 *reg_val |= CFG_PAGE_SIZE_2048;
 485         else if (our_mtd->writesize == 4096)
 486                 *reg_val |= CFG_PAGE_SIZE_4096;
 487         else {
 488                 debug("%s: Unsupported page size %d\n", __func__,
 489                       our_mtd->writesize);
 490                 return -1;
 491         }
 492
 493         return 0;
 494 }
 495
 496 /**
 497  * Page read/write function
 498  *
 499  * @param mtd           mtd info structure
 500  * @param chip          nand chip info structure
 501  * @param buf           data buffer
 502  * @param page          page number
 503  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 504  * @param is_writing    0 for read, 1 for write
 505  * @return      0 when successfully completed
 506  *              -EIO when command timeout
 507  */
 508 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 509         uint8_t *buf, int page, int with_ecc, int is_writing)
 510 {
 511         u32 reg_val;
 512         int tag_size;
 513         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 514         /* 4*128=512 (byte) is the value that our HW can support. */
 515         ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
 516         char *tag_ptr;
 517         struct nand_drv *info;
 518         struct fdt_nand *config;
 519         unsigned int bbflags;
 520         struct bounce_buffer bbstate, bbstate_oob;
 521
 522         if ((uintptr_t)buf & 0x03) {
 523                 printf("buf %p has to be 4-byte aligned\n", buf);
 524                 return -EINVAL;
 525         }
 526
 527         info = (struct nand_drv *)nand_get_controller_data(chip);
 528         config = &info->config;
 529         if (set_bus_width_page_size(mtd, config, &reg_val))
 530                 return -EINVAL;
 531
 532         /* Need to be 4-byte aligned */
 533         tag_ptr = (char *)tag_buf;
 534
 535         stop_command(info->reg);
 536
 537         if (is_writing)
 538                 bbflags = GEN_BB_READ;
 539         else
 540                 bbflags = GEN_BB_WRITE;
 541
 542         bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
 543                             bbflags);
 544         writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
 545         writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
 546
 547         /* Set ECC selection, configure ECC settings */
 548         if (with_ecc) {
 549                 if (is_writing)
 550                         memcpy(tag_ptr, chip->oob_poi + free->offset,
 551                                chip->ecc.layout->oobavail + TAG_ECC_BYTES);
 552                 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
 553                 reg_val |= (CFG_SKIP_SPARE_SEL_4
 554                         | CFG_SKIP_SPARE_ENABLE
 555                         | CFG_HW_ECC_CORRECTION_ENABLE
 556                         | CFG_ECC_EN_TAG_DISABLE
 557                         | CFG_HW_ECC_SEL_RS
 558                         | CFG_HW_ECC_ENABLE
 559                         | CFG_TVAL4
 560                         | (tag_size - 1));
 561
 562                 if (!is_writing)
 563                         tag_size += SKIPPED_SPARE_BYTES;
 564                 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
 565                                     bbflags);
 566         } else {
 567                 tag_size = mtd->oobsize;
 568                 reg_val |= (CFG_SKIP_SPARE_DISABLE
 569                         | CFG_HW_ECC_CORRECTION_DISABLE
 570                         | CFG_ECC_EN_TAG_DISABLE
 571                         | CFG_HW_ECC_DISABLE
 572                         | (tag_size - 1));
 573                 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
 574                                     tag_size, bbflags);
 575         }
 576         writel(reg_val, &info->reg->config);
 577         writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
 578         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 579         writel(tag_size - 1, &info->reg->dma_cfg_b);
 580
 581         nand_clear_interrupt_status(info->reg);
 582
 583         reg_val = CMD_CLE | CMD_ALE
 584                 | CMD_SEC_CMD
 585                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 586                 | CMD_A_VALID
 587                 | CMD_B_VALID
 588                 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
 589                 | CMD_CE0;
 590         if (!is_writing)
 591                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 592         else
 593                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 594         writel(reg_val, &info->reg->command);
 595
 596         /* Setup DMA engine */
 597         reg_val = DMA_MST_CTRL_GO_ENABLE
 598                 | DMA_MST_CTRL_BURST_8WORDS
 599                 | DMA_MST_CTRL_EN_A_ENABLE
 600                 | DMA_MST_CTRL_EN_B_ENABLE;
 601
 602         if (!is_writing)
 603                 reg_val |= DMA_MST_CTRL_DIR_READ;
 604         else
 605                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 606
 607         writel(reg_val, &info->reg->dma_mst_ctrl);
 608
 609         start_command(info->reg);
 610
 611         if (!nand_waitfor_cmd_completion(info->reg)) {
 612                 if (!is_writing)
 613                         printf("Read Page 0x%X timeout ", page);
 614                 else
 615                         printf("Write Page 0x%X timeout ", page);
 616                 if (with_ecc)
 617                         printf("with ECC");
 618                 else
 619                         printf("without ECC");
 620                 printf("\n");
 621                 return -EIO;
 622         }
 623
 624         bounce_buffer_stop(&bbstate_oob);
 625         bounce_buffer_stop(&bbstate);
 626
 627         if (with_ecc && !is_writing) {
 628                 memcpy(chip->oob_poi, tag_ptr,
 629                         SKIPPED_SPARE_BYTES);
 630                 memcpy(chip->oob_poi + free->offset,
 631                         tag_ptr + SKIPPED_SPARE_BYTES,
 632                         chip->ecc.layout->oobavail);
 633                 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
 634                         1 << chip->page_shift,
 635                         (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
 636                         chip->ecc.layout->oobavail);
 637                 if (reg_val & ECC_TAG_ERROR)
 638                         printf("Read Page 0x%X tag ECC error\n", page);
 639                 if (reg_val & ECC_DATA_ERROR)
 640                         printf("Read Page 0x%X data ECC error\n",
 641                                 page);
 642                 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
 643                         return -EIO;
 644         }
 645         return 0;
 646 }
 647
 648 /**
 649  * Hardware ecc based page read function
 650  *
 651  * @param mtd   mtd info structure
 652  * @param chip  nand chip info structure
 653  * @param buf   buffer to store read data
 654  * @param page  page number to read
 655  * @return      0 when successfully completed
 656  *              -EIO when command timeout
 657  */
 658 static int nand_read_page_hwecc(struct mtd_info *mtd,
 659         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 660 {
 661         return nand_rw_page(mtd, chip, buf, page, 1, 0);
 662 }
 663
 664 /**
 665  * Hardware ecc based page write function
 666  *
 667  * @param mtd   mtd info structure
 668  * @param chip  nand chip info structure
 669  * @param buf   data buffer
 670  */
 671 static int nand_write_page_hwecc(struct mtd_info *mtd,
 672         struct nand_chip *chip, const uint8_t *buf, int oob_required,
 673         int page)
 674 {
 675         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
 676         return 0;
 677 }
 678
 679
 680 /**
 681  * Read raw page data without ecc
 682  *
 683  * @param mtd   mtd info structure
 684  * @param chip  nand chip info structure
 685  * @param buf   buffer to store read data
 686  * @param page  page number to read
 687  * @return      0 when successfully completed
 688  *              -EINVAL when chip->oob_poi is not double-word aligned
 689  *              -EIO when command timeout
 690  */
 691 static int nand_read_page_raw(struct mtd_info *mtd,
 692         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 693 {
 694         return nand_rw_page(mtd, chip, buf, page, 0, 0);
 695 }
 696
 697 /**
 698  * Raw page write function
 699  *
 700  * @param mtd   mtd info structure
 701  * @param chip  nand chip info structure
 702  * @param buf   data buffer
 703  */
 704 static int nand_write_page_raw(struct mtd_info *mtd,
 705                 struct nand_chip *chip, const uint8_t *buf,
 706                 int oob_required, int page)
 707 {
 708         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
 709         return 0;
 710 }
 711
 712 /**
 713  * OOB data read/write function
 714  *
 715  * @param mtd           mtd info structure
 716  * @param chip          nand chip info structure
 717  * @param page          page number to read
 718  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 719  * @param is_writing    0 for read, 1 for write
 720  * @return      0 when successfully completed
 721  *              -EINVAL when chip->oob_poi is not double-word aligned
 722  *              -EIO when command timeout
 723  */
 724 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 725         int page, int with_ecc, int is_writing)
 726 {
 727         u32 reg_val;
 728         int tag_size;
 729         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 730         struct nand_drv *info;
 731         unsigned int bbflags;
 732         struct bounce_buffer bbstate_oob;
 733
 734         if (((int)chip->oob_poi) & 0x03)
 735                 return -EINVAL;
 736         info = (struct nand_drv *)nand_get_controller_data(chip);
 737         if (set_bus_width_page_size(mtd, &info->config, &reg_val))
 738                 return -EINVAL;
 739
 740         stop_command(info->reg);
 741
 742         /* Set ECC selection */
 743         tag_size = mtd->oobsize;
 744         if (with_ecc)
 745                 reg_val |= CFG_ECC_EN_TAG_ENABLE;
 746         else
 747                 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
 748
 749         reg_val |= ((tag_size - 1) |
 750                 CFG_SKIP_SPARE_DISABLE |
 751                 CFG_HW_ECC_CORRECTION_DISABLE |
 752                 CFG_HW_ECC_DISABLE);
 753         writel(reg_val, &info->reg->config);
 754
 755         if (is_writing && with_ecc)
 756                 tag_size -= TAG_ECC_BYTES;
 757
 758         if (is_writing)
 759                 bbflags = GEN_BB_READ;
 760         else
 761                 bbflags = GEN_BB_WRITE;
 762
 763         bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
 764                             bbflags);
 765         writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
 766
 767         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 768
 769         writel(tag_size - 1, &info->reg->dma_cfg_b);
 770
 771         nand_clear_interrupt_status(info->reg);
 772
 773         reg_val = CMD_CLE | CMD_ALE
 774                 | CMD_SEC_CMD
 775                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 776                 | CMD_B_VALID
 777                 | CMD_CE0;
 778         if (!is_writing)
 779                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 780         else
 781                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 782         writel(reg_val, &info->reg->command);
 783
 784         /* Setup DMA engine */
 785         reg_val = DMA_MST_CTRL_GO_ENABLE
 786                 | DMA_MST_CTRL_BURST_8WORDS
 787                 | DMA_MST_CTRL_EN_B_ENABLE;
 788         if (!is_writing)
 789                 reg_val |= DMA_MST_CTRL_DIR_READ;
 790         else
 791                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 792
 793         writel(reg_val, &info->reg->dma_mst_ctrl);
 794
 795         start_command(info->reg);
 796
 797         if (!nand_waitfor_cmd_completion(info->reg)) {
 798                 if (!is_writing)
 799                         printf("Read OOB of Page 0x%X timeout\n", page);
 800                 else
 801                         printf("Write OOB of Page 0x%X timeout\n", page);
 802                 return -EIO;
 803         }
 804
 805         bounce_buffer_stop(&bbstate_oob);
 806
 807         if (with_ecc && !is_writing) {
 808                 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
 809                         (u8 *)(chip->oob_poi + free->offset),
 810                         chip->ecc.layout->oobavail);
 811                 if (reg_val & ECC_TAG_ERROR)
 812                         printf("Read OOB of Page 0x%X tag ECC error\n", page);
 813         }
 814         return 0;
 815 }
 816
 817 /**
 818  * OOB data read function
 819  *
 820  * @param mtd           mtd info structure
 821  * @param chip          nand chip info structure
 822  * @param page          page number to read
 823  */
 824 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 825         int page)
 826 {
 827         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 828         nand_rw_oob(mtd, chip, page, 0, 0);
 829         return 0;
 830 }
 831
 832 /**
 833  * OOB data write function
 834  *
 835  * @param mtd   mtd info structure
 836  * @param chip  nand chip info structure
 837  * @param page  page number to write
 838  * @return      0 when successfully completed
 839  *              -EINVAL when chip->oob_poi is not double-word aligned
 840  *              -EIO when command timeout
 841  */
 842 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 843         int page)
 844 {
 845         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 846
 847         return nand_rw_oob(mtd, chip, page, 0, 1);
 848 }
 849
 850 /**
 851  * Set up NAND memory timings according to the provided parameters
 852  *
 853  * @param timing        Timing parameters
 854  * @param reg           NAND controller register address
 855  */
 856 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
 857                          struct nand_ctlr *reg)
 858 {
 859         u32 reg_val, clk_rate, clk_period, time_val;
 860
 861         clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
 862                 CLOCK_ID_PERIPH) / 1000000;
 863         clk_period = 1000 / clk_rate;
 864         reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 865                 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
 866         reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
 867                 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
 868         time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
 869         if (time_val > 2)
 870                 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
 871                         TIMING_TCR_TAR_TRR_CNT_MASK;
 872         reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
 873                 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
 874         time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
 875         if (time_val > 1)
 876                 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
 877                         TIMING_TCS_CNT_MASK;
 878         reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
 879                 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
 880         reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
 881                 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
 882         reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
 883                 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
 884         reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 885                 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
 886         writel(reg_val, &reg->timing);
 887
 888         reg_val = 0;
 889         time_val = timing[FDT_NAND_TADL] / clk_period;
 890         if (time_val > 2)
 891                 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
 892         writel(reg_val, &reg->timing2);
 893 }
 894
 895 /**
 896  * Decode NAND parameters from the device tree
 897  *
 898  * @param dev           Driver model device
 899  * @param config        Device tree NAND configuration
 900  * @return 0 if ok, -ve on error (FDT_ERR_...)
 901  */
 902 static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
 903 {
 904         int err;
 905
 906         config->reg = (struct nand_ctlr *)dev_read_addr(dev);
 907         config->enabled = dev_read_enabled(dev);
 908         config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
 909         err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
 910                                    GPIOD_IS_OUT);
 911         if (err)
 912                 return err;
 913         err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
 914                                  FDT_NAND_TIMING_COUNT);
 915         if (err < 0)
 916                 return err;
 917
 918         return 0;
 919 }
 920
 921 static int tegra_probe(struct udevice *dev)
 922 {
 923         struct tegra_nand_info *tegra = dev_get_priv(dev);
 924         struct nand_chip *nand = &tegra->nand_chip;
 925         struct nand_drv *info = &tegra->nand_ctrl;
 926         struct fdt_nand *config = &info->config;
 927         struct mtd_info *our_mtd;
 928         int ret;
 929
 930         if (fdt_decode_nand(dev, config)) {
 931                 printf("Could not decode nand-flash in device tree\n");
 932                 return -1;
 933         }
 934         if (!config->enabled)
 935                 return -1;
 936         info->reg = config->reg;
 937         nand->ecc.mode = NAND_ECC_HW;
 938         nand->ecc.layout = &eccoob;
 939
 940         nand->options = LP_OPTIONS;
 941         nand->cmdfunc = nand_command;
 942         nand->read_byte = read_byte;
 943         nand->read_buf = read_buf;
 944         nand->ecc.read_page = nand_read_page_hwecc;
 945         nand->ecc.write_page = nand_write_page_hwecc;
 946         nand->ecc.read_page_raw = nand_read_page_raw;
 947         nand->ecc.write_page_raw = nand_write_page_raw;
 948         nand->ecc.read_oob = nand_read_oob;
 949         nand->ecc.write_oob = nand_write_oob;
 950         nand->ecc.strength = 1;
 951         nand->select_chip = nand_select_chip;
 952         nand->dev_ready  = nand_dev_ready;
 953         nand_set_controller_data(nand, &tegra->nand_ctrl);
 954
 955         /* Disable subpage writes as we do not provide ecc->hwctl */
 956         nand->options |= NAND_NO_SUBPAGE_WRITE;
 957
 958         /* Adjust controller clock rate */
 959         clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
 960
 961         /* Adjust timing for NAND device */
 962         setup_timing(config->timing, info->reg);
 963
 964         dm_gpio_set_value(&config->wp_gpio, 1);
 965
 966         our_mtd = nand_to_mtd(nand);
 967         ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 968         if (ret)
 969                 return ret;
 970
 971         nand->ecc.size = our_mtd->writesize;
 972         nand->ecc.bytes = our_mtd->oobsize;
 973
 974         ret = nand_scan_tail(our_mtd);
 975         if (ret)
 976                 return ret;
 977
 978         ret = nand_register(0, our_mtd);
 979         if (ret) {
 980                 dev_err(dev, "Failed to register MTD: %d\n", ret);
 981                 return ret;
 982         }
 983
 984         return 0;
 985 }
 986
 987 U_BOOT_DRIVER(tegra_nand) = {
 988         .name = "tegra-nand",
 989         .id = UCLASS_MTD,
 990         .of_match = tegra_nand_dt_ids,
 991         .probe = tegra_probe,
 992         .priv_auto_alloc_size = sizeof(struct tegra_nand_info),
 993 };
 994
 995 void board_nand_init(void)
 996 {
 997         struct udevice *dev;
 998         int ret;
 999
1000         ret = uclass_get_device_by_driver(UCLASS_MTD,
1001                                           DM_GET_DRIVER(tegra_nand), &dev);
1002         if (ret && ret != -ENODEV)
1003                 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
1004                        ret);
1005 }