drivers/mtd/nand/raw/sunxi_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
   4  * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
   5  *
   6  * Derived from:
   7  *      https://github.com/yuq/sunxi-nfc-mtd
   8  *      Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
   9  *
  10  *      https://github.com/hno/Allwinner-Info
  11  *      Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  12  *
  13  *      Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  14  *      Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  */
  26
  27 #include <common.h>
  28 #include <fdtdec.h>
  29 #include <malloc.h>
  30 #include <memalign.h>
  31 #include <nand.h>
  32 #include <dm/device_compat.h>
  33 #include <dm/devres.h>
  34 #include <linux/err.h>
  35
  36 #include <linux/kernel.h>
  37 #include <linux/mtd/mtd.h>
  38 #include <linux/mtd/rawnand.h>
  39 #include <linux/mtd/partitions.h>
  40 #include <linux/io.h>
  41
  42 #include <asm/gpio.h>
  43 #include <asm/arch/clock.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 #define NFC_REG_CTL             0x0000
  48 #define NFC_REG_ST              0x0004
  49 #define NFC_REG_INT             0x0008
  50 #define NFC_REG_TIMING_CTL      0x000C
  51 #define NFC_REG_TIMING_CFG      0x0010
  52 #define NFC_REG_ADDR_LOW        0x0014
  53 #define NFC_REG_ADDR_HIGH       0x0018
  54 #define NFC_REG_SECTOR_NUM      0x001C
  55 #define NFC_REG_CNT             0x0020
  56 #define NFC_REG_CMD             0x0024
  57 #define NFC_REG_RCMD_SET        0x0028
  58 #define NFC_REG_WCMD_SET        0x002C
  59 #define NFC_REG_IO_DATA         0x0030
  60 #define NFC_REG_ECC_CTL         0x0034
  61 #define NFC_REG_ECC_ST          0x0038
  62 #define NFC_REG_DEBUG           0x003C
  63 #define NFC_REG_ECC_ERR_CNT(x)  ((0x0040 + (x)) & ~0x3)
  64 #define NFC_REG_USER_DATA(x)    (0x0050 + ((x) * 4))
  65 #define NFC_REG_SPARE_AREA      0x00A0
  66 #define NFC_REG_PAT_ID          0x00A4
  67 #define NFC_RAM0_BASE           0x0400
  68 #define NFC_RAM1_BASE           0x0800
  69
  70 /* define bit use in NFC_CTL */
  71 #define NFC_EN                  BIT(0)
  72 #define NFC_RESET               BIT(1)
  73 #define NFC_BUS_WIDTH_MSK       BIT(2)
  74 #define NFC_BUS_WIDTH_8         (0 << 2)
  75 #define NFC_BUS_WIDTH_16        (1 << 2)
  76 #define NFC_RB_SEL_MSK          BIT(3)
  77 #define NFC_RB_SEL(x)           ((x) << 3)
  78 #define NFC_CE_SEL_MSK          (0x7 << 24)
  79 #define NFC_CE_SEL(x)           ((x) << 24)
  80 #define NFC_CE_CTL              BIT(6)
  81 #define NFC_PAGE_SHIFT_MSK      (0xf << 8)
  82 #define NFC_PAGE_SHIFT(x)       (((x) < 10 ? 0 : (x) - 10) << 8)
  83 #define NFC_SAM                 BIT(12)
  84 #define NFC_RAM_METHOD          BIT(14)
  85 #define NFC_DEBUG_CTL           BIT(31)
  86
  87 /* define bit use in NFC_ST */
  88 #define NFC_RB_B2R              BIT(0)
  89 #define NFC_CMD_INT_FLAG        BIT(1)
  90 #define NFC_DMA_INT_FLAG        BIT(2)
  91 #define NFC_CMD_FIFO_STATUS     BIT(3)
  92 #define NFC_STA                 BIT(4)
  93 #define NFC_NATCH_INT_FLAG      BIT(5)
  94 #define NFC_RB_STATE(x)         BIT(x + 8)
  95
  96 /* define bit use in NFC_INT */
  97 #define NFC_B2R_INT_ENABLE      BIT(0)
  98 #define NFC_CMD_INT_ENABLE      BIT(1)
  99 #define NFC_DMA_INT_ENABLE      BIT(2)
 100 #define NFC_INT_MASK            (NFC_B2R_INT_ENABLE | \
 101                                  NFC_CMD_INT_ENABLE | \
 102                                  NFC_DMA_INT_ENABLE)
 103
 104 /* define bit use in NFC_TIMING_CTL */
 105 #define NFC_TIMING_CTL_EDO      BIT(8)
 106
 107 /* define NFC_TIMING_CFG register layout */
 108 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD)             \
 109         (((tWB) & 0x3) | (((tADL) & 0x3) << 2) |                \
 110         (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) |         \
 111         (((tCAD) & 0x7) << 8))
 112
 113 /* define bit use in NFC_CMD */
 114 #define NFC_CMD_LOW_BYTE_MSK    0xff
 115 #define NFC_CMD_HIGH_BYTE_MSK   (0xff << 8)
 116 #define NFC_CMD(x)              (x)
 117 #define NFC_ADR_NUM_MSK         (0x7 << 16)
 118 #define NFC_ADR_NUM(x)          (((x) - 1) << 16)
 119 #define NFC_SEND_ADR            BIT(19)
 120 #define NFC_ACCESS_DIR          BIT(20)
 121 #define NFC_DATA_TRANS          BIT(21)
 122 #define NFC_SEND_CMD1           BIT(22)
 123 #define NFC_WAIT_FLAG           BIT(23)
 124 #define NFC_SEND_CMD2           BIT(24)
 125 #define NFC_SEQ                 BIT(25)
 126 #define NFC_DATA_SWAP_METHOD    BIT(26)
 127 #define NFC_ROW_AUTO_INC        BIT(27)
 128 #define NFC_SEND_CMD3           BIT(28)
 129 #define NFC_SEND_CMD4           BIT(29)
 130 #define NFC_CMD_TYPE_MSK        (0x3 << 30)
 131 #define NFC_NORMAL_OP           (0 << 30)
 132 #define NFC_ECC_OP              (1 << 30)
 133 #define NFC_PAGE_OP             (2 << 30)
 134
 135 /* define bit use in NFC_RCMD_SET */
 136 #define NFC_READ_CMD_MSK        0xff
 137 #define NFC_RND_READ_CMD0_MSK   (0xff << 8)
 138 #define NFC_RND_READ_CMD1_MSK   (0xff << 16)
 139
 140 /* define bit use in NFC_WCMD_SET */
 141 #define NFC_PROGRAM_CMD_MSK     0xff
 142 #define NFC_RND_WRITE_CMD_MSK   (0xff << 8)
 143 #define NFC_READ_CMD0_MSK       (0xff << 16)
 144 #define NFC_READ_CMD1_MSK       (0xff << 24)
 145
 146 /* define bit use in NFC_ECC_CTL */
 147 #define NFC_ECC_EN              BIT(0)
 148 #define NFC_ECC_PIPELINE        BIT(3)
 149 #define NFC_ECC_EXCEPTION       BIT(4)
 150 #define NFC_ECC_BLOCK_SIZE_MSK  BIT(5)
 151 #define NFC_ECC_BLOCK_512       (1 << 5)
 152 #define NFC_RANDOM_EN           BIT(9)
 153 #define NFC_RANDOM_DIRECTION    BIT(10)
 154 #define NFC_ECC_MODE_MSK        (0xf << 12)
 155 #define NFC_ECC_MODE(x)         ((x) << 12)
 156 #define NFC_RANDOM_SEED_MSK     (0x7fff << 16)
 157 #define NFC_RANDOM_SEED(x)      ((x) << 16)
 158
 159 /* define bit use in NFC_ECC_ST */
 160 #define NFC_ECC_ERR(x)          BIT(x)
 161 #define NFC_ECC_PAT_FOUND(x)    BIT(x + 16)
 162 #define NFC_ECC_ERR_CNT(b, x)   (((x) >> ((b) * 8)) & 0xff)
 163
 164 #define NFC_DEFAULT_TIMEOUT_MS  1000
 165
 166 #define NFC_SRAM_SIZE           1024
 167
 168 #define NFC_MAX_CS              7
 169
 170 /*
 171  * Ready/Busy detection type: describes the Ready/Busy detection modes
 172  *
 173  * @RB_NONE:    no external detection available, rely on STATUS command
 174  *              and software timeouts
 175  * @RB_NATIVE:  use sunxi NAND controller Ready/Busy support. The Ready/Busy
 176  *              pin of the NAND flash chip must be connected to one of the
 177  *              native NAND R/B pins (those which can be muxed to the NAND
 178  *              Controller)
 179  * @RB_GPIO:    use a simple GPIO to handle Ready/Busy status. The Ready/Busy
 180  *              pin of the NAND flash chip must be connected to a GPIO capable
 181  *              pin.
 182  */
 183 enum sunxi_nand_rb_type {
 184         RB_NONE,
 185         RB_NATIVE,
 186         RB_GPIO,
 187 };
 188
 189 /*
 190  * Ready/Busy structure: stores information related to Ready/Busy detection
 191  *
 192  * @type:       the Ready/Busy detection mode
 193  * @info:       information related to the R/B detection mode. Either a gpio
 194  *              id or a native R/B id (those supported by the NAND controller).
 195  */
 196 struct sunxi_nand_rb {
 197         enum sunxi_nand_rb_type type;
 198         union {
 199                 struct gpio_desc gpio;
 200                 int nativeid;
 201         } info;
 202 };
 203
 204 /*
 205  * Chip Select structure: stores information related to NAND Chip Select
 206  *
 207  * @cs:         the NAND CS id used to communicate with a NAND Chip
 208  * @rb:         the Ready/Busy description
 209  */
 210 struct sunxi_nand_chip_sel {
 211         u8 cs;
 212         struct sunxi_nand_rb rb;
 213 };
 214
 215 /*
 216  * sunxi HW ECC infos: stores information related to HW ECC support
 217  *
 218  * @mode:       the sunxi ECC mode field deduced from ECC requirements
 219  * @layout:     the OOB layout depending on the ECC requirements and the
 220  *              selected ECC mode
 221  */
 222 struct sunxi_nand_hw_ecc {
 223         int mode;
 224         struct nand_ecclayout layout;
 225 };
 226
 227 /*
 228  * NAND chip structure: stores NAND chip device related information
 229  *
 230  * @node:               used to store NAND chips into a list
 231  * @nand:               base NAND chip structure
 232  * @mtd:                base MTD structure
 233  * @clk_rate:           clk_rate required for this NAND chip
 234  * @timing_cfg          TIMING_CFG register value for this NAND chip
 235  * @selected:           current active CS
 236  * @nsels:              number of CS lines required by the NAND chip
 237  * @sels:               array of CS lines descriptions
 238  */
 239 struct sunxi_nand_chip {
 240         struct list_head node;
 241         struct nand_chip nand;
 242         unsigned long clk_rate;
 243         u32 timing_cfg;
 244         u32 timing_ctl;
 245         int selected;
 246         int addr_cycles;
 247         u32 addr[2];
 248         int cmd_cycles;
 249         u8 cmd[2];
 250         int nsels;
 251         struct sunxi_nand_chip_sel sels[0];
 252 };
 253
 254 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
 255 {
 256         return container_of(nand, struct sunxi_nand_chip, nand);
 257 }
 258
 259 /*
 260  * NAND Controller structure: stores sunxi NAND controller information
 261  *
 262  * @controller:         base controller structure
 263  * @dev:                parent device (used to print error messages)
 264  * @regs:               NAND controller registers
 265  * @ahb_clk:            NAND Controller AHB clock
 266  * @mod_clk:            NAND Controller mod clock
 267  * @assigned_cs:        bitmask describing already assigned CS lines
 268  * @clk_rate:           NAND controller current clock rate
 269  * @chips:              a list containing all the NAND chips attached to
 270  *                      this NAND controller
 271  * @complete:           a completion object used to wait for NAND
 272  *                      controller events
 273  */
 274 struct sunxi_nfc {
 275         struct nand_hw_control controller;
 276         struct device *dev;
 277         void __iomem *regs;
 278         struct clk *ahb_clk;
 279         struct clk *mod_clk;
 280         unsigned long assigned_cs;
 281         unsigned long clk_rate;
 282         struct list_head chips;
 283 };
 284
 285 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
 286 {
 287         return container_of(ctrl, struct sunxi_nfc, controller);
 288 }
 289
 290 static void sunxi_nfc_set_clk_rate(unsigned long hz)
 291 {
 292         struct sunxi_ccm_reg *const ccm =
 293         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 294         int div_m, div_n;
 295
 296         div_m = (clock_get_pll6() + hz - 1) / hz;
 297         for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
 298                 if (div_m % 2)
 299                         div_m++;
 300                 div_m >>= 1;
 301         }
 302         if (div_m > 16)
 303                 div_m = 16;
 304
 305         /* config mod clock */
 306         writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
 307                CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
 308                &ccm->nand0_clk_cfg);
 309
 310         /* gate on nand clock */
 311         setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
 312 #ifdef CONFIG_MACH_SUN9I
 313         setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 314 #else
 315         setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
 316 #endif
 317 }
 318
 319 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
 320                               unsigned int timeout_ms)
 321 {
 322         unsigned int timeout_ticks;
 323         u32 time_start, status;
 324         int ret = -ETIMEDOUT;
 325
 326         if (!timeout_ms)
 327                 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
 328
 329         timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
 330
 331         time_start = get_timer(0);
 332
 333         do {
 334                 status = readl(nfc->regs + NFC_REG_ST);
 335                 if ((status & flags) == flags) {
 336                         ret = 0;
 337                         break;
 338                 }
 339
 340                 udelay(1);
 341         } while (get_timer(time_start) < timeout_ticks);
 342
 343         writel(status & flags, nfc->regs + NFC_REG_ST);
 344
 345         return ret;
 346 }
 347
 348 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
 349 {
 350         unsigned long timeout = (CONFIG_SYS_HZ *
 351                                  NFC_DEFAULT_TIMEOUT_MS) / 1000;
 352         u32 time_start;
 353
 354         time_start = get_timer(0);
 355         do {
 356                 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
 357                         return 0;
 358         } while (get_timer(time_start) < timeout);
 359
 360         dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
 361         return -ETIMEDOUT;
 362 }
 363
 364 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
 365 {
 366         unsigned long timeout = (CONFIG_SYS_HZ *
 367                                  NFC_DEFAULT_TIMEOUT_MS) / 1000;
 368         u32 time_start;
 369
 370         writel(0, nfc->regs + NFC_REG_ECC_CTL);
 371         writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
 372
 373         time_start = get_timer(0);
 374         do {
 375                 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
 376                         return 0;
 377         } while (get_timer(time_start) < timeout);
 378
 379         dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
 380         return -ETIMEDOUT;
 381 }
 382
 383 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
 384 {
 385         struct nand_chip *nand = mtd_to_nand(mtd);
 386         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 387         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 388         struct sunxi_nand_rb *rb;
 389         unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
 390         int ret;
 391
 392         if (sunxi_nand->selected < 0)
 393                 return 0;
 394
 395         rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
 396
 397         switch (rb->type) {
 398         case RB_NATIVE:
 399                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 400                          NFC_RB_STATE(rb->info.nativeid));
 401                 if (ret)
 402                         break;
 403
 404                 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
 405                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 406                          NFC_RB_STATE(rb->info.nativeid));
 407                 break;
 408         case RB_GPIO:
 409                 ret = dm_gpio_get_value(&rb->info.gpio);
 410                 break;
 411         case RB_NONE:
 412         default:
 413                 ret = 0;
 414                 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
 415                 break;
 416         }
 417
 418         return ret;
 419 }
 420
 421 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
 422 {
 423         struct nand_chip *nand = mtd_to_nand(mtd);
 424         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 425         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 426         struct sunxi_nand_chip_sel *sel;
 427         u32 ctl;
 428
 429         if (chip > 0 && chip >= sunxi_nand->nsels)
 430                 return;
 431
 432         if (chip == sunxi_nand->selected)
 433                 return;
 434
 435         ctl = readl(nfc->regs + NFC_REG_CTL) &
 436               ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
 437
 438         if (chip >= 0) {
 439                 sel = &sunxi_nand->sels[chip];
 440
 441                 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
 442                        NFC_PAGE_SHIFT(nand->page_shift - 10);
 443                 if (sel->rb.type == RB_NONE) {
 444                         nand->dev_ready = NULL;
 445                 } else {
 446                         nand->dev_ready = sunxi_nfc_dev_ready;
 447                         if (sel->rb.type == RB_NATIVE)
 448                                 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
 449                 }
 450
 451                 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
 452
 453                 if (nfc->clk_rate != sunxi_nand->clk_rate) {
 454                         sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
 455                         nfc->clk_rate = sunxi_nand->clk_rate;
 456                 }
 457         }
 458
 459         writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
 460         writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
 461         writel(ctl, nfc->regs + NFC_REG_CTL);
 462
 463         sunxi_nand->selected = chip;
 464 }
 465
 466 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 467 {
 468         struct nand_chip *nand = mtd_to_nand(mtd);
 469         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 470         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 471         int ret;
 472         int cnt;
 473         int offs = 0;
 474         u32 tmp;
 475
 476         while (len > offs) {
 477                 cnt = min(len - offs, NFC_SRAM_SIZE);
 478
 479                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 480                 if (ret)
 481                         break;
 482
 483                 writel(cnt, nfc->regs + NFC_REG_CNT);
 484                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
 485                 writel(tmp, nfc->regs + NFC_REG_CMD);
 486
 487                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 488                 if (ret)
 489                         break;
 490
 491                 if (buf)
 492                         memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
 493                                       cnt);
 494                 offs += cnt;
 495         }
 496 }
 497
 498 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 499                                 int len)
 500 {
 501         struct nand_chip *nand = mtd_to_nand(mtd);
 502         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 503         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 504         int ret;
 505         int cnt;
 506         int offs = 0;
 507         u32 tmp;
 508
 509         while (len > offs) {
 510                 cnt = min(len - offs, NFC_SRAM_SIZE);
 511
 512                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 513                 if (ret)
 514                         break;
 515
 516                 writel(cnt, nfc->regs + NFC_REG_CNT);
 517                 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
 518                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 519                       NFC_ACCESS_DIR;
 520                 writel(tmp, nfc->regs + NFC_REG_CMD);
 521
 522                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 523                 if (ret)
 524                         break;
 525
 526                 offs += cnt;
 527         }
 528 }
 529
 530 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
 531 {
 532         uint8_t ret;
 533
 534         sunxi_nfc_read_buf(mtd, &ret, 1);
 535
 536         return ret;
 537 }
 538
 539 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
 540                                unsigned int ctrl)
 541 {
 542         struct nand_chip *nand = mtd_to_nand(mtd);
 543         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 544         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 545         int ret;
 546         u32 tmp;
 547
 548         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 549         if (ret)
 550                 return;
 551
 552         if (ctrl & NAND_CTRL_CHANGE) {
 553                 tmp = readl(nfc->regs + NFC_REG_CTL);
 554                 if (ctrl & NAND_NCE)
 555                         tmp |= NFC_CE_CTL;
 556                 else
 557                         tmp &= ~NFC_CE_CTL;
 558                 writel(tmp, nfc->regs + NFC_REG_CTL);
 559         }
 560
 561         if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
 562             !(ctrl & (NAND_CLE | NAND_ALE))) {
 563                 u32 cmd = 0;
 564
 565                 if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
 566                         return;
 567
 568                 if (sunxi_nand->cmd_cycles--)
 569                         cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
 570
 571                 if (sunxi_nand->cmd_cycles--) {
 572                         cmd |= NFC_SEND_CMD2;
 573                         writel(sunxi_nand->cmd[1],
 574                                nfc->regs + NFC_REG_RCMD_SET);
 575                 }
 576
 577                 sunxi_nand->cmd_cycles = 0;
 578
 579                 if (sunxi_nand->addr_cycles) {
 580                         cmd |= NFC_SEND_ADR |
 581                                NFC_ADR_NUM(sunxi_nand->addr_cycles);
 582                         writel(sunxi_nand->addr[0],
 583                                nfc->regs + NFC_REG_ADDR_LOW);
 584                 }
 585
 586                 if (sunxi_nand->addr_cycles > 4)
 587                         writel(sunxi_nand->addr[1],
 588                                nfc->regs + NFC_REG_ADDR_HIGH);
 589
 590                 writel(cmd, nfc->regs + NFC_REG_CMD);
 591                 sunxi_nand->addr[0] = 0;
 592                 sunxi_nand->addr[1] = 0;
 593                 sunxi_nand->addr_cycles = 0;
 594                 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 595         }
 596
 597         if (ctrl & NAND_CLE) {
 598                 sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
 599         } else if (ctrl & NAND_ALE) {
 600                 sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
 601                                 dat << ((sunxi_nand->addr_cycles % 4) * 8);
 602                 sunxi_nand->addr_cycles++;
 603         }
 604 }
 605
 606 /* These seed values have been extracted from Allwinner's BSP */
 607 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
 608         0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
 609         0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
 610         0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
 611         0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
 612         0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
 613         0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
 614         0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
 615         0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
 616         0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
 617         0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
 618         0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
 619         0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
 620         0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
 621         0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
 622         0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
 623         0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 624 };
 625
 626 /*
 627  * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
 628  * have been generated using
 629  * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
 630  * the randomizer engine does internally before de/scrambling OOB data.
 631  *
 632  * Those tables are statically defined to avoid calculating randomizer state
 633  * at runtime.
 634  */
 635 static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
 636         0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
 637         0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
 638         0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
 639         0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
 640         0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
 641         0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
 642         0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
 643         0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
 644         0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
 645         0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
 646         0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
 647         0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
 648         0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
 649         0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
 650         0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
 651         0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
 652 };
 653
 654 static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
 655         0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
 656         0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
 657         0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
 658         0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
 659         0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
 660         0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
 661         0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
 662         0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
 663         0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
 664         0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
 665         0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
 666         0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
 667         0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
 668         0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
 669         0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
 670         0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
 671 };
 672
 673 static u16 sunxi_nfc_randomizer_step(u16 state, int count)
 674 {
 675         state &= 0x7fff;
 676
 677         /*
 678          * This loop is just a simple implementation of a Fibonacci LFSR using
 679          * the x16 + x15 + 1 polynomial.
 680          */
 681         while (count--)
 682                 state = ((state >> 1) |
 683                          (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
 684
 685         return state;
 686 }
 687
 688 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
 689 {
 690         const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
 691         int mod = mtd->erasesize / mtd->writesize;
 692
 693         if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
 694                 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
 695
 696         if (ecc) {
 697                 if (mtd->ecc_step_size == 512)
 698                         seeds = sunxi_nfc_randomizer_ecc512_seeds;
 699                 else
 700                         seeds = sunxi_nfc_randomizer_ecc1024_seeds;
 701         }
 702
 703         return seeds[page % mod];
 704 }
 705
 706 static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
 707                                         int page, bool ecc)
 708 {
 709         struct nand_chip *nand = mtd_to_nand(mtd);
 710         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 711         u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 712         u16 state;
 713
 714         if (!(nand->options & NAND_NEED_SCRAMBLING))
 715                 return;
 716
 717         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 718         state = sunxi_nfc_randomizer_state(mtd, page, ecc);
 719         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
 720         writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
 721 }
 722
 723 static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
 724 {
 725         struct nand_chip *nand = mtd_to_nand(mtd);
 726         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 727
 728         if (!(nand->options & NAND_NEED_SCRAMBLING))
 729                 return;
 730
 731         writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
 732                nfc->regs + NFC_REG_ECC_CTL);
 733 }
 734
 735 static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
 736 {
 737         struct nand_chip *nand = mtd_to_nand(mtd);
 738         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 739
 740         if (!(nand->options & NAND_NEED_SCRAMBLING))
 741                 return;
 742
 743         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
 744                nfc->regs + NFC_REG_ECC_CTL);
 745 }
 746
 747 static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
 748 {
 749         u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
 750
 751         bbm[0] ^= state;
 752         bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
 753 }
 754
 755 static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
 756                                            const uint8_t *buf, int len,
 757                                            bool ecc, int page)
 758 {
 759         sunxi_nfc_randomizer_config(mtd, page, ecc);
 760         sunxi_nfc_randomizer_enable(mtd);
 761         sunxi_nfc_write_buf(mtd, buf, len);
 762         sunxi_nfc_randomizer_disable(mtd);
 763 }
 764
 765 static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
 766                                           int len, bool ecc, int page)
 767 {
 768         sunxi_nfc_randomizer_config(mtd, page, ecc);
 769         sunxi_nfc_randomizer_enable(mtd);
 770         sunxi_nfc_read_buf(mtd, buf, len);
 771         sunxi_nfc_randomizer_disable(mtd);
 772 }
 773
 774 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
 775 {
 776         struct nand_chip *nand = mtd_to_nand(mtd);
 777         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 778         struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
 779         u32 ecc_ctl;
 780
 781         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 782         ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
 783                      NFC_ECC_BLOCK_SIZE_MSK);
 784         ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
 785
 786         if (nand->ecc.size == 512)
 787                 ecc_ctl |= NFC_ECC_BLOCK_512;
 788
 789         writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
 790 }
 791
 792 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
 793 {
 794         struct nand_chip *nand = mtd_to_nand(mtd);
 795         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 796
 797         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
 798                nfc->regs + NFC_REG_ECC_CTL);
 799 }
 800
 801 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
 802 {
 803         buf[0] = user_data;
 804         buf[1] = user_data >> 8;
 805         buf[2] = user_data >> 16;
 806         buf[3] = user_data >> 24;
 807 }
 808
 809 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
 810                                        u8 *data, int data_off,
 811                                        u8 *oob, int oob_off,
 812                                        int *cur_off,
 813                                        unsigned int *max_bitflips,
 814                                        bool bbm, int page)
 815 {
 816         struct nand_chip *nand = mtd_to_nand(mtd);
 817         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 818         struct nand_ecc_ctrl *ecc = &nand->ecc;
 819         int raw_mode = 0;
 820         u32 status;
 821         int ret;
 822
 823         if (*cur_off != data_off)
 824                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 825
 826         sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
 827
 828         if (data_off + ecc->size != oob_off)
 829                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 830
 831         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 832         if (ret)
 833                 return ret;
 834
 835         sunxi_nfc_randomizer_enable(mtd);
 836         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
 837                nfc->regs + NFC_REG_CMD);
 838
 839         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 840         sunxi_nfc_randomizer_disable(mtd);
 841         if (ret)
 842                 return ret;
 843
 844         *cur_off = oob_off + ecc->bytes + 4;
 845
 846         status = readl(nfc->regs + NFC_REG_ECC_ST);
 847         if (status & NFC_ECC_PAT_FOUND(0)) {
 848                 u8 pattern = 0xff;
 849
 850                 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
 851                         pattern = 0x0;
 852
 853                 memset(data, pattern, ecc->size);
 854                 memset(oob, pattern, ecc->bytes + 4);
 855
 856                 return 1;
 857         }
 858
 859         ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
 860
 861         memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
 862
 863         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 864         sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
 865
 866         if (status & NFC_ECC_ERR(0)) {
 867                 /*
 868                  * Re-read the data with the randomizer disabled to identify
 869                  * bitflips in erased pages.
 870                  */
 871                 if (nand->options & NAND_NEED_SCRAMBLING) {
 872                         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 873                         nand->read_buf(mtd, data, ecc->size);
 874                         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 875                         nand->read_buf(mtd, oob, ecc->bytes + 4);
 876                 }
 877
 878                 ret = nand_check_erased_ecc_chunk(data, ecc->size,
 879                                                   oob, ecc->bytes + 4,
 880                                                   NULL, 0, ecc->strength);
 881                 if (ret >= 0)
 882                         raw_mode = 1;
 883         } else {
 884                 /*
 885                  * The engine protects 4 bytes of OOB data per chunk.
 886                  * Retrieve the corrected OOB bytes.
 887                  */
 888                 sunxi_nfc_user_data_to_buf(readl(nfc->regs +
 889                                                  NFC_REG_USER_DATA(0)),
 890                                            oob);
 891
 892                 /* De-randomize the Bad Block Marker. */
 893                 if (bbm && nand->options & NAND_NEED_SCRAMBLING)
 894                         sunxi_nfc_randomize_bbm(mtd, page, oob);
 895         }
 896
 897         if (ret < 0) {
 898                 mtd->ecc_stats.failed++;
 899         } else {
 900                 mtd->ecc_stats.corrected += ret;
 901                 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
 902         }
 903
 904         return raw_mode;
 905 }
 906
 907 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
 908                                             u8 *oob, int *cur_off,
 909                                             bool randomize, int page)
 910 {
 911         struct nand_chip *nand = mtd_to_nand(mtd);
 912         struct nand_ecc_ctrl *ecc = &nand->ecc;
 913         int offset = ((ecc->bytes + 4) * ecc->steps);
 914         int len = mtd->oobsize - offset;
 915
 916         if (len <= 0)
 917                 return;
 918
 919         if (*cur_off != offset)
 920                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
 921                               offset + mtd->writesize, -1);
 922
 923         if (!randomize)
 924                 sunxi_nfc_read_buf(mtd, oob + offset, len);
 925         else
 926                 sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
 927                                               false, page);
 928
 929         *cur_off = mtd->oobsize + mtd->writesize;
 930 }
 931
 932 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
 933 {
 934         return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
 935 }
 936
 937 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
 938                                         const u8 *data, int data_off,
 939                                         const u8 *oob, int oob_off,
 940                                         int *cur_off, bool bbm,
 941                                         int page)
 942 {
 943         struct nand_chip *nand = mtd_to_nand(mtd);
 944         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 945         struct nand_ecc_ctrl *ecc = &nand->ecc;
 946         int ret;
 947
 948         if (data_off != *cur_off)
 949                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
 950
 951         sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
 952
 953         /* Fill OOB data in */
 954         if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
 955                 u8 user_data[4];
 956
 957                 memcpy(user_data, oob, 4);
 958                 sunxi_nfc_randomize_bbm(mtd, page, user_data);
 959                 writel(sunxi_nfc_buf_to_user_data(user_data),
 960                        nfc->regs + NFC_REG_USER_DATA(0));
 961         } else {
 962                 writel(sunxi_nfc_buf_to_user_data(oob),
 963                        nfc->regs + NFC_REG_USER_DATA(0));
 964         }
 965
 966         if (data_off + ecc->size != oob_off)
 967                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
 968
 969         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 970         if (ret)
 971                 return ret;
 972
 973         sunxi_nfc_randomizer_enable(mtd);
 974         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 975                NFC_ACCESS_DIR | NFC_ECC_OP,
 976                nfc->regs + NFC_REG_CMD);
 977
 978         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 979         sunxi_nfc_randomizer_disable(mtd);
 980         if (ret)
 981                 return ret;
 982
 983         *cur_off = oob_off + ecc->bytes + 4;
 984
 985         return 0;
 986 }
 987
 988 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
 989                                              u8 *oob, int *cur_off,
 990                                              int page)
 991 {
 992         struct nand_chip *nand = mtd_to_nand(mtd);
 993         struct nand_ecc_ctrl *ecc = &nand->ecc;
 994         int offset = ((ecc->bytes + 4) * ecc->steps);
 995         int len = mtd->oobsize - offset;
 996
 997         if (len <= 0)
 998                 return;
 999
1000         if (*cur_off != offset)
1001                 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
1002                               offset + mtd->writesize, -1);
1003
1004         sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
1005
1006         *cur_off = mtd->oobsize + mtd->writesize;
1007 }
1008
1009 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
1010                                       struct nand_chip *chip, uint8_t *buf,
1011                                       int oob_required, int page)
1012 {
1013         struct nand_ecc_ctrl *ecc = &chip->ecc;
1014         unsigned int max_bitflips = 0;
1015         int ret, i, cur_off = 0;
1016         bool raw_mode = false;
1017
1018         sunxi_nfc_hw_ecc_enable(mtd);
1019
1020         for (i = 0; i < ecc->steps; i++) {
1021                 int data_off = i * ecc->size;
1022                 int oob_off = i * (ecc->bytes + 4);
1023                 u8 *data = buf + data_off;
1024                 u8 *oob = chip->oob_poi + oob_off;
1025
1026                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1027                                                   oob_off + mtd->writesize,
1028                                                   &cur_off, &max_bitflips,
1029                                                   !i, page);
1030                 if (ret < 0)
1031                         return ret;
1032                 else if (ret)
1033                         raw_mode = true;
1034         }
1035
1036         if (oob_required)
1037                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1038                                                 !raw_mode, page);
1039
1040         sunxi_nfc_hw_ecc_disable(mtd);
1041
1042         return max_bitflips;
1043 }
1044
1045 static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
1046                                          struct nand_chip *chip,
1047                                          uint32_t data_offs, uint32_t readlen,
1048                                          uint8_t *bufpoi, int page)
1049 {
1050         struct nand_ecc_ctrl *ecc = &chip->ecc;
1051         int ret, i, cur_off = 0;
1052         unsigned int max_bitflips = 0;
1053
1054         sunxi_nfc_hw_ecc_enable(mtd);
1055
1056         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1057         for (i = data_offs / ecc->size;
1058              i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1059                 int data_off = i * ecc->size;
1060                 int oob_off = i * (ecc->bytes + 4);
1061                 u8 *data = bufpoi + data_off;
1062                 u8 *oob = chip->oob_poi + oob_off;
1063
1064                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
1065                         oob, oob_off + mtd->writesize,
1066                         &cur_off, &max_bitflips, !i, page);
1067                 if (ret < 0)
1068                         return ret;
1069         }
1070
1071         sunxi_nfc_hw_ecc_disable(mtd);
1072
1073         return max_bitflips;
1074 }
1075
1076 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
1077                                        struct nand_chip *chip,
1078                                        const uint8_t *buf, int oob_required,
1079                                        int page)
1080 {
1081         struct nand_ecc_ctrl *ecc = &chip->ecc;
1082         int ret, i, cur_off = 0;
1083
1084         sunxi_nfc_hw_ecc_enable(mtd);
1085
1086         for (i = 0; i < ecc->steps; i++) {
1087                 int data_off = i * ecc->size;
1088                 int oob_off = i * (ecc->bytes + 4);
1089                 const u8 *data = buf + data_off;
1090                 const u8 *oob = chip->oob_poi + oob_off;
1091
1092                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1093                                                    oob_off + mtd->writesize,
1094                                                    &cur_off, !i, page);
1095                 if (ret)
1096                         return ret;
1097         }
1098
1099         if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1100                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1101                                                  &cur_off, page);
1102
1103         sunxi_nfc_hw_ecc_disable(mtd);
1104
1105         return 0;
1106 }
1107
1108 static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
1109                                           struct nand_chip *chip,
1110                                           u32 data_offs, u32 data_len,
1111                                           const u8 *buf, int oob_required,
1112                                           int page)
1113 {
1114         struct nand_ecc_ctrl *ecc = &chip->ecc;
1115         int ret, i, cur_off = 0;
1116
1117         sunxi_nfc_hw_ecc_enable(mtd);
1118
1119         for (i = data_offs / ecc->size;
1120              i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1121                 int data_off = i * ecc->size;
1122                 int oob_off = i * (ecc->bytes + 4);
1123                 const u8 *data = buf + data_off;
1124                 const u8 *oob = chip->oob_poi + oob_off;
1125
1126                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1127                                                    oob_off + mtd->writesize,
1128                                                    &cur_off, !i, page);
1129                 if (ret)
1130                         return ret;
1131         }
1132
1133         sunxi_nfc_hw_ecc_disable(mtd);
1134
1135         return 0;
1136 }
1137
1138 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
1139                                                struct nand_chip *chip,
1140                                                uint8_t *buf, int oob_required,
1141                                                int page)
1142 {
1143         struct nand_ecc_ctrl *ecc = &chip->ecc;
1144         unsigned int max_bitflips = 0;
1145         int ret, i, cur_off = 0;
1146         bool raw_mode = false;
1147
1148         sunxi_nfc_hw_ecc_enable(mtd);
1149
1150         for (i = 0; i < ecc->steps; i++) {
1151                 int data_off = i * (ecc->size + ecc->bytes + 4);
1152                 int oob_off = data_off + ecc->size;
1153                 u8 *data = buf + (i * ecc->size);
1154                 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1155
1156                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1157                                                   oob_off, &cur_off,
1158                                                   &max_bitflips, !i, page);
1159                 if (ret < 0)
1160                         return ret;
1161                 else if (ret)
1162                         raw_mode = true;
1163         }
1164
1165         if (oob_required)
1166                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1167                                                 !raw_mode, page);
1168
1169         sunxi_nfc_hw_ecc_disable(mtd);
1170
1171         return max_bitflips;
1172 }
1173
1174 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
1175                                                 struct nand_chip *chip,
1176                                                 const uint8_t *buf,
1177                                                 int oob_required, int page)
1178 {
1179         struct nand_ecc_ctrl *ecc = &chip->ecc;
1180         int ret, i, cur_off = 0;
1181
1182         sunxi_nfc_hw_ecc_enable(mtd);
1183
1184         for (i = 0; i < ecc->steps; i++) {
1185                 int data_off = i * (ecc->size + ecc->bytes + 4);
1186                 int oob_off = data_off + ecc->size;
1187                 const u8 *data = buf + (i * ecc->size);
1188                 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1189
1190                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
1191                                                    oob, oob_off, &cur_off,
1192                                                    false, page);
1193                 if (ret)
1194                         return ret;
1195         }
1196
1197         if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1198                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1199                                                  &cur_off, page);
1200
1201         sunxi_nfc_hw_ecc_disable(mtd);
1202
1203         return 0;
1204 }
1205
1206 static const s32 tWB_lut[] = {6, 12, 16, 20};
1207 static const s32 tRHW_lut[] = {4, 8, 12, 20};
1208
1209 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1210                 u32 clk_period)
1211 {
1212         u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1213         int i;
1214
1215         for (i = 0; i < lut_size; i++) {
1216                 if (clk_cycles <= lut[i])
1217                         return i;
1218         }
1219
1220         /* Doesn't fit */
1221         return -EINVAL;
1222 }
1223
1224 #define sunxi_nand_lookup_timing(l, p, c) \
1225                         _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1226
1227 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1228                                        const struct nand_sdr_timings *timings)
1229 {
1230         u32 min_clk_period = 0;
1231         s32 tWB, tADL, tWHR, tRHW, tCAD;
1232
1233         /* T1 <=> tCLS */
1234         if (timings->tCLS_min > min_clk_period)
1235                 min_clk_period = timings->tCLS_min;
1236
1237         /* T2 <=> tCLH */
1238         if (timings->tCLH_min > min_clk_period)
1239                 min_clk_period = timings->tCLH_min;
1240
1241         /* T3 <=> tCS */
1242         if (timings->tCS_min > min_clk_period)
1243                 min_clk_period = timings->tCS_min;
1244
1245         /* T4 <=> tCH */
1246         if (timings->tCH_min > min_clk_period)
1247                 min_clk_period = timings->tCH_min;
1248
1249         /* T5 <=> tWP */
1250         if (timings->tWP_min > min_clk_period)
1251                 min_clk_period = timings->tWP_min;
1252
1253         /* T6 <=> tWH */
1254         if (timings->tWH_min > min_clk_period)
1255                 min_clk_period = timings->tWH_min;
1256
1257         /* T7 <=> tALS */
1258         if (timings->tALS_min > min_clk_period)
1259                 min_clk_period = timings->tALS_min;
1260
1261         /* T8 <=> tDS */
1262         if (timings->tDS_min > min_clk_period)
1263                 min_clk_period = timings->tDS_min;
1264
1265         /* T9 <=> tDH */
1266         if (timings->tDH_min > min_clk_period)
1267                 min_clk_period = timings->tDH_min;
1268
1269         /* T10 <=> tRR */
1270         if (timings->tRR_min > (min_clk_period * 3))
1271                 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1272
1273         /* T11 <=> tALH */
1274         if (timings->tALH_min > min_clk_period)
1275                 min_clk_period = timings->tALH_min;
1276
1277         /* T12 <=> tRP */
1278         if (timings->tRP_min > min_clk_period)
1279                 min_clk_period = timings->tRP_min;
1280
1281         /* T13 <=> tREH */
1282         if (timings->tREH_min > min_clk_period)
1283                 min_clk_period = timings->tREH_min;
1284
1285         /* T14 <=> tRC */
1286         if (timings->tRC_min > (min_clk_period * 2))
1287                 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1288
1289         /* T15 <=> tWC */
1290         if (timings->tWC_min > (min_clk_period * 2))
1291                 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1292
1293         /* T16 - T19 + tCAD */
1294         tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1295                                         min_clk_period);
1296         if (tWB < 0) {
1297                 dev_err(nfc->dev, "unsupported tWB\n");
1298                 return tWB;
1299         }
1300
1301         tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1302         if (tADL > 3) {
1303                 dev_err(nfc->dev, "unsupported tADL\n");
1304                 return -EINVAL;
1305         }
1306
1307         tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1308         if (tWHR > 3) {
1309                 dev_err(nfc->dev, "unsupported tWHR\n");
1310                 return -EINVAL;
1311         }
1312
1313         tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1314                                         min_clk_period);
1315         if (tRHW < 0) {
1316                 dev_err(nfc->dev, "unsupported tRHW\n");
1317                 return tRHW;
1318         }
1319
1320         /*
1321          * TODO: according to ONFI specs this value only applies for DDR NAND,
1322          * but Allwinner seems to set this to 0x7. Mimic them for now.
1323          */
1324         tCAD = 0x7;
1325
1326         /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1327         chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1328
1329         /*
1330          * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1331          * output cycle timings shall be used if the host drives tRC less than
1332          * 30 ns.
1333          */
1334         chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
1335
1336         /* Convert min_clk_period from picoseconds to nanoseconds */
1337         min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1338
1339         /*
1340          * Convert min_clk_period into a clk frequency, then get the
1341          * appropriate rate for the NAND controller IP given this formula
1342          * (specified in the datasheet):
1343          * nand clk_rate = min_clk_rate
1344          */
1345         chip->clk_rate = 1000000000L / min_clk_period;
1346
1347         return 0;
1348 }
1349
1350 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
1351 {
1352         struct mtd_info *mtd = nand_to_mtd(&chip->nand);
1353         const struct nand_sdr_timings *timings;
1354         int ret;
1355         int mode;
1356
1357         mode = onfi_get_async_timing_mode(&chip->nand);
1358         if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1359                 mode = chip->nand.onfi_timing_mode_default;
1360         } else {
1361                 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1362                 int i;
1363
1364                 mode = fls(mode) - 1;
1365                 if (mode < 0)
1366                         mode = 0;
1367
1368                 feature[0] = mode;
1369                 for (i = 0; i < chip->nsels; i++) {
1370                         chip->nand.select_chip(mtd, i);
1371                         ret = chip->nand.onfi_set_features(mtd,
1372                                                 &chip->nand,
1373                                                 ONFI_FEATURE_ADDR_TIMING_MODE,
1374                                                 feature);
1375                         chip->nand.select_chip(mtd, -1);
1376                         if (ret && ret != -ENOTSUPP)
1377                                 return ret;
1378                 }
1379         }
1380
1381         timings = onfi_async_timing_mode_to_sdr_timings(mode);
1382         if (IS_ERR(timings))
1383                 return PTR_ERR(timings);
1384
1385         return sunxi_nand_chip_set_timings(chip, timings);
1386 }
1387
1388 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1389                                               struct nand_ecc_ctrl *ecc)
1390 {
1391         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1392         struct sunxi_nand_hw_ecc *data;
1393         struct nand_ecclayout *layout;
1394         int nsectors;
1395         int ret;
1396         int i;
1397
1398         data = kzalloc(sizeof(*data), GFP_KERNEL);
1399         if (!data)
1400                 return -ENOMEM;
1401
1402         if (ecc->size != 512 && ecc->size != 1024)
1403                 return -EINVAL;
1404
1405         /* Prefer 1k ECC chunk over 512 ones */
1406         if (ecc->size == 512 && mtd->writesize > 512) {
1407                 ecc->size = 1024;
1408                 ecc->strength *= 2;
1409         }
1410
1411         /* Add ECC info retrieval from DT */
1412         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1413                 if (ecc->strength <= strengths[i]) {
1414                         /*
1415                          * Update ecc->strength value with the actual strength
1416                          * that will be used by the ECC engine.
1417                          */
1418                         ecc->strength = strengths[i];
1419                         break;
1420                 }
1421         }
1422
1423         if (i >= ARRAY_SIZE(strengths)) {
1424                 dev_err(nfc->dev, "unsupported strength\n");
1425                 ret = -ENOTSUPP;
1426                 goto err;
1427         }
1428
1429         data->mode = i;
1430
1431         /* HW ECC always request ECC bytes for 1024 bytes blocks */
1432         ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1433
1434         /* HW ECC always work with even numbers of ECC bytes */
1435         ecc->bytes = ALIGN(ecc->bytes, 2);
1436
1437         layout = &data->layout;
1438         nsectors = mtd->writesize / ecc->size;
1439
1440         if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1441                 ret = -EINVAL;
1442                 goto err;
1443         }
1444
1445         layout->eccbytes = (ecc->bytes * nsectors);
1446
1447         ecc->layout = layout;
1448         ecc->priv = data;
1449
1450         return 0;
1451
1452 err:
1453         kfree(data);
1454
1455         return ret;
1456 }
1457
1458 #ifndef __UBOOT__
1459 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1460 {
1461         kfree(ecc->priv);
1462 }
1463 #endif /* __UBOOT__ */
1464
1465 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1466                                        struct nand_ecc_ctrl *ecc)
1467 {
1468         struct nand_ecclayout *layout;
1469         int nsectors;
1470         int i, j;
1471         int ret;
1472
1473         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1474         if (ret)
1475                 return ret;
1476
1477         ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1478         ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1479         ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1480         ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1481         layout = ecc->layout;
1482         nsectors = mtd->writesize / ecc->size;
1483
1484         for (i = 0; i < nsectors; i++) {
1485                 if (i) {
1486                         layout->oobfree[i].offset =
1487                                 layout->oobfree[i - 1].offset +
1488                                 layout->oobfree[i - 1].length +
1489                                 ecc->bytes;
1490                         layout->oobfree[i].length = 4;
1491                 } else {
1492                         /*
1493                          * The first 2 bytes are used for BB markers, hence we
1494                          * only have 2 bytes available in the first user data
1495                          * section.
1496                          */
1497                         layout->oobfree[i].length = 2;
1498                         layout->oobfree[i].offset = 2;
1499                 }
1500
1501                 for (j = 0; j < ecc->bytes; j++)
1502                         layout->eccpos[(ecc->bytes * i) + j] =
1503                                         layout->oobfree[i].offset +
1504                                         layout->oobfree[i].length + j;
1505         }
1506
1507         if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1508                 layout->oobfree[nsectors].offset =
1509                                 layout->oobfree[nsectors - 1].offset +
1510                                 layout->oobfree[nsectors - 1].length +
1511                                 ecc->bytes;
1512                 layout->oobfree[nsectors].length = mtd->oobsize -
1513                                 ((ecc->bytes + 4) * nsectors);
1514         }
1515
1516         return 0;
1517 }
1518
1519 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1520                                                 struct nand_ecc_ctrl *ecc)
1521 {
1522         struct nand_ecclayout *layout;
1523         int nsectors;
1524         int i;
1525         int ret;
1526
1527         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1528         if (ret)
1529                 return ret;
1530
1531         ecc->prepad = 4;
1532         ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1533         ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1534
1535         layout = ecc->layout;
1536         nsectors = mtd->writesize / ecc->size;
1537
1538         for (i = 0; i < (ecc->bytes * nsectors); i++)
1539                 layout->eccpos[i] = i;
1540
1541         layout->oobfree[0].length = mtd->oobsize - i;
1542         layout->oobfree[0].offset = i;
1543
1544         return 0;
1545 }
1546
1547 #ifndef __UBOOT__
1548 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1549 {
1550         switch (ecc->mode) {
1551         case NAND_ECC_HW:
1552         case NAND_ECC_HW_SYNDROME:
1553                 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1554                 break;
1555         case NAND_ECC_NONE:
1556                 kfree(ecc->layout);
1557         default:
1558                 break;
1559         }
1560 }
1561 #endif /* __UBOOT__ */
1562
1563 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
1564 {
1565         struct nand_chip *nand = mtd_to_nand(mtd);
1566         int ret;
1567
1568         if (!ecc->size) {
1569                 ecc->size = nand->ecc_step_ds;
1570                 ecc->strength = nand->ecc_strength_ds;
1571         }
1572
1573         if (!ecc->size || !ecc->strength)
1574                 return -EINVAL;
1575
1576         switch (ecc->mode) {
1577         case NAND_ECC_SOFT_BCH:
1578                 break;
1579         case NAND_ECC_HW:
1580                 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
1581                 if (ret)
1582                         return ret;
1583                 break;
1584         case NAND_ECC_HW_SYNDROME:
1585                 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
1586                 if (ret)
1587                         return ret;
1588                 break;
1589         case NAND_ECC_NONE:
1590                 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1591                 if (!ecc->layout)
1592                         return -ENOMEM;
1593                 ecc->layout->oobfree[0].length = mtd->oobsize;
1594         case NAND_ECC_SOFT:
1595                 break;
1596         default:
1597                 return -EINVAL;
1598         }
1599
1600         return 0;
1601 }
1602
1603 static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
1604 {
1605         const struct nand_sdr_timings *timings;
1606         const void *blob = gd->fdt_blob;
1607         struct sunxi_nand_chip *chip;
1608         struct mtd_info *mtd;
1609         struct nand_chip *nand;
1610         int nsels;
1611         int ret;
1612         int i;
1613         u32 cs[8], rb[8];
1614
1615         if (!fdt_getprop(blob, node, "reg", &nsels))
1616                 return -EINVAL;
1617
1618         nsels /= sizeof(u32);
1619         if (!nsels || nsels > 8) {
1620                 dev_err(dev, "invalid reg property size\n");
1621                 return -EINVAL;
1622         }
1623
1624         chip = kzalloc(sizeof(*chip) +
1625                        (nsels * sizeof(struct sunxi_nand_chip_sel)),
1626                        GFP_KERNEL);
1627         if (!chip) {
1628                 dev_err(dev, "could not allocate chip\n");
1629                 return -ENOMEM;
1630         }
1631
1632         chip->nsels = nsels;
1633         chip->selected = -1;
1634
1635         for (i = 0; i < nsels; i++) {
1636                 cs[i] = -1;
1637                 rb[i] = -1;
1638         }
1639
1640         ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
1641         if (ret) {
1642                 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1643                 return ret;
1644         }
1645
1646         ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
1647                                    nsels);
1648         if (ret) {
1649                 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1650                 return ret;
1651         }
1652
1653         for (i = 0; i < nsels; i++) {
1654                 int tmp = cs[i];
1655
1656                 if (tmp > NFC_MAX_CS) {
1657                         dev_err(dev,
1658                                 "invalid reg value: %u (max CS = 7)\n",
1659                                 tmp);
1660                         return -EINVAL;
1661                 }
1662
1663                 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1664                         dev_err(dev, "CS %d already assigned\n", tmp);
1665                         return -EINVAL;
1666                 }
1667
1668                 chip->sels[i].cs = tmp;
1669
1670                 tmp = rb[i];
1671                 if (tmp >= 0 && tmp < 2) {
1672                         chip->sels[i].rb.type = RB_NATIVE;
1673                         chip->sels[i].rb.info.nativeid = tmp;
1674                 } else {
1675                         ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
1676                                                 "rb-gpios", i,
1677                                                 &chip->sels[i].rb.info.gpio,
1678                                                 GPIOD_IS_IN);
1679                         if (ret)
1680                                 chip->sels[i].rb.type = RB_GPIO;
1681                         else
1682                                 chip->sels[i].rb.type = RB_NONE;
1683                 }
1684         }
1685
1686         timings = onfi_async_timing_mode_to_sdr_timings(0);
1687         if (IS_ERR(timings)) {
1688                 ret = PTR_ERR(timings);
1689                 dev_err(dev,
1690                         "could not retrieve timings for ONFI mode 0: %d\n",
1691                         ret);
1692                 return ret;
1693         }
1694
1695         ret = sunxi_nand_chip_set_timings(chip, timings);
1696         if (ret) {
1697                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1698                 return ret;
1699         }
1700
1701         nand = &chip->nand;
1702         /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1703         nand->chip_delay = 200;
1704         nand->controller = &nfc->controller;
1705         /*
1706          * Set the ECC mode to the default value in case nothing is specified
1707          * in the DT.
1708          */
1709         nand->ecc.mode = NAND_ECC_HW;
1710         nand->flash_node = node;
1711         nand->select_chip = sunxi_nfc_select_chip;
1712         nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1713         nand->read_buf = sunxi_nfc_read_buf;
1714         nand->write_buf = sunxi_nfc_write_buf;
1715         nand->read_byte = sunxi_nfc_read_byte;
1716
1717         mtd = nand_to_mtd(nand);
1718         ret = nand_scan_ident(mtd, nsels, NULL);
1719         if (ret)
1720                 return ret;
1721
1722         if (nand->bbt_options & NAND_BBT_USE_FLASH)
1723                 nand->bbt_options |= NAND_BBT_NO_OOB;
1724
1725         if (nand->options & NAND_NEED_SCRAMBLING)
1726                 nand->options |= NAND_NO_SUBPAGE_WRITE;
1727
1728         nand->options |= NAND_SUBPAGE_READ;
1729
1730         ret = sunxi_nand_chip_init_timings(chip);
1731         if (ret) {
1732                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1733                 return ret;
1734         }
1735
1736         ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
1737         if (ret) {
1738                 dev_err(dev, "ECC init failed: %d\n", ret);
1739                 return ret;
1740         }
1741
1742         ret = nand_scan_tail(mtd);
1743         if (ret) {
1744                 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1745                 return ret;
1746         }
1747
1748         ret = nand_register(devnum, mtd);
1749         if (ret) {
1750                 dev_err(dev, "failed to register mtd device: %d\n", ret);
1751                 return ret;
1752         }
1753
1754         list_add_tail(&chip->node, &nfc->chips);
1755
1756         return 0;
1757 }
1758
1759 static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
1760 {
1761         const void *blob = gd->fdt_blob;
1762         int nand_node;
1763         int ret, i = 0;
1764
1765         for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1766              nand_node = fdt_next_subnode(blob, nand_node))
1767                 i++;
1768
1769         if (i > 8) {
1770                 dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
1771                 return -EINVAL;
1772         }
1773
1774         i = 0;
1775         for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1776              nand_node = fdt_next_subnode(blob, nand_node)) {
1777                 ret = sunxi_nand_chip_init(nand_node, nfc, i++);
1778                 if (ret)
1779                         return ret;
1780         }
1781
1782         return 0;
1783 }
1784
1785 #ifndef __UBOOT__
1786 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1787 {
1788         struct sunxi_nand_chip *chip;
1789
1790         while (!list_empty(&nfc->chips)) {
1791                 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1792                                         node);
1793                 nand_release(&chip->mtd);
1794                 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1795                 list_del(&chip->node);
1796                 kfree(chip);
1797         }
1798 }
1799 #endif /* __UBOOT__ */
1800
1801 void sunxi_nand_init(void)
1802 {
1803         const void *blob = gd->fdt_blob;
1804         struct sunxi_nfc *nfc;
1805         fdt_addr_t regs;
1806         int node;
1807         int ret;
1808
1809         nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
1810         if (!nfc)
1811                 return;
1812
1813         spin_lock_init(&nfc->controller.lock);
1814         init_waitqueue_head(&nfc->controller.wq);
1815         INIT_LIST_HEAD(&nfc->chips);
1816
1817         node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
1818         if (node < 0) {
1819                 pr_err("unable to find nfc node in device tree\n");
1820                 goto err;
1821         }
1822
1823         if (!fdtdec_get_is_enabled(blob, node)) {
1824                 pr_err("nfc disabled in device tree\n");
1825                 goto err;
1826         }
1827
1828         regs = fdtdec_get_addr(blob, node, "reg");
1829         if (regs == FDT_ADDR_T_NONE) {
1830                 pr_err("unable to find nfc address in device tree\n");
1831                 goto err;
1832         }
1833
1834         nfc->regs = (void *)regs;
1835
1836         ret = sunxi_nfc_rst(nfc);
1837         if (ret)
1838                 goto err;
1839
1840         ret = sunxi_nand_chips_init(node, nfc);
1841         if (ret) {
1842                 dev_err(dev, "failed to init nand chips\n");
1843                 goto err;
1844         }
1845
1846         return;
1847
1848 err:
1849         kfree(nfc);
1850 }
1851
1852 MODULE_LICENSE("GPL v2");
1853 MODULE_AUTHOR("Boris BREZILLON");
1854 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");