drivers/mtd/nand/raw/sunxi_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
   4  * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
   5  *
   6  * Derived from:
   7  *      https://github.com/yuq/sunxi-nfc-mtd
   8  *      Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
   9  *
  10  *      https://github.com/hno/Allwinner-Info
  11  *      Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  12  *
  13  *      Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  14  *      Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  */
  26
  27 #include <common.h>
  28 #include <fdtdec.h>
  29 #include <malloc.h>
  30 #include <memalign.h>
  31 #include <nand.h>
  32 #include <dm/device_compat.h>
  33 #include <dm/devres.h>
  34 #include <linux/delay.h>
  35 #include <linux/err.h>
  36
  37 #include <linux/kernel.h>
  38 #include <linux/mtd/mtd.h>
  39 #include <linux/mtd/rawnand.h>
  40 #include <linux/mtd/partitions.h>
  41 #include <linux/io.h>
  42
  43 #include <asm/gpio.h>
  44 #include <asm/arch/clock.h>
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 #define NFC_REG_CTL             0x0000
  49 #define NFC_REG_ST              0x0004
  50 #define NFC_REG_INT             0x0008
  51 #define NFC_REG_TIMING_CTL      0x000C
  52 #define NFC_REG_TIMING_CFG      0x0010
  53 #define NFC_REG_ADDR_LOW        0x0014
  54 #define NFC_REG_ADDR_HIGH       0x0018
  55 #define NFC_REG_SECTOR_NUM      0x001C
  56 #define NFC_REG_CNT             0x0020
  57 #define NFC_REG_CMD             0x0024
  58 #define NFC_REG_RCMD_SET        0x0028
  59 #define NFC_REG_WCMD_SET        0x002C
  60 #define NFC_REG_IO_DATA         0x0030
  61 #define NFC_REG_ECC_CTL         0x0034
  62 #define NFC_REG_ECC_ST          0x0038
  63 #define NFC_REG_DEBUG           0x003C
  64 #define NFC_REG_ECC_ERR_CNT(x)  ((0x0040 + (x)) & ~0x3)
  65 #define NFC_REG_USER_DATA(x)    (0x0050 + ((x) * 4))
  66 #define NFC_REG_SPARE_AREA      0x00A0
  67 #define NFC_REG_PAT_ID          0x00A4
  68 #define NFC_RAM0_BASE           0x0400
  69 #define NFC_RAM1_BASE           0x0800
  70
  71 /* define bit use in NFC_CTL */
  72 #define NFC_EN                  BIT(0)
  73 #define NFC_RESET               BIT(1)
  74 #define NFC_BUS_WIDTH_MSK       BIT(2)
  75 #define NFC_BUS_WIDTH_8         (0 << 2)
  76 #define NFC_BUS_WIDTH_16        (1 << 2)
  77 #define NFC_RB_SEL_MSK          BIT(3)
  78 #define NFC_RB_SEL(x)           ((x) << 3)
  79 #define NFC_CE_SEL_MSK          (0x7 << 24)
  80 #define NFC_CE_SEL(x)           ((x) << 24)
  81 #define NFC_CE_CTL              BIT(6)
  82 #define NFC_PAGE_SHIFT_MSK      (0xf << 8)
  83 #define NFC_PAGE_SHIFT(x)       (((x) < 10 ? 0 : (x) - 10) << 8)
  84 #define NFC_SAM                 BIT(12)
  85 #define NFC_RAM_METHOD          BIT(14)
  86 #define NFC_DEBUG_CTL           BIT(31)
  87
  88 /* define bit use in NFC_ST */
  89 #define NFC_RB_B2R              BIT(0)
  90 #define NFC_CMD_INT_FLAG        BIT(1)
  91 #define NFC_DMA_INT_FLAG        BIT(2)
  92 #define NFC_CMD_FIFO_STATUS     BIT(3)
  93 #define NFC_STA                 BIT(4)
  94 #define NFC_NATCH_INT_FLAG      BIT(5)
  95 #define NFC_RB_STATE(x)         BIT(x + 8)
  96
  97 /* define bit use in NFC_INT */
  98 #define NFC_B2R_INT_ENABLE      BIT(0)
  99 #define NFC_CMD_INT_ENABLE      BIT(1)
 100 #define NFC_DMA_INT_ENABLE      BIT(2)
 101 #define NFC_INT_MASK            (NFC_B2R_INT_ENABLE | \
 102                                  NFC_CMD_INT_ENABLE | \
 103                                  NFC_DMA_INT_ENABLE)
 104
 105 /* define bit use in NFC_TIMING_CTL */
 106 #define NFC_TIMING_CTL_EDO      BIT(8)
 107
 108 /* define NFC_TIMING_CFG register layout */
 109 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD)             \
 110         (((tWB) & 0x3) | (((tADL) & 0x3) << 2) |                \
 111         (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) |         \
 112         (((tCAD) & 0x7) << 8))
 113
 114 /* define bit use in NFC_CMD */
 115 #define NFC_CMD_LOW_BYTE_MSK    0xff
 116 #define NFC_CMD_HIGH_BYTE_MSK   (0xff << 8)
 117 #define NFC_CMD(x)              (x)
 118 #define NFC_ADR_NUM_MSK         (0x7 << 16)
 119 #define NFC_ADR_NUM(x)          (((x) - 1) << 16)
 120 #define NFC_SEND_ADR            BIT(19)
 121 #define NFC_ACCESS_DIR          BIT(20)
 122 #define NFC_DATA_TRANS          BIT(21)
 123 #define NFC_SEND_CMD1           BIT(22)
 124 #define NFC_WAIT_FLAG           BIT(23)
 125 #define NFC_SEND_CMD2           BIT(24)
 126 #define NFC_SEQ                 BIT(25)
 127 #define NFC_DATA_SWAP_METHOD    BIT(26)
 128 #define NFC_ROW_AUTO_INC        BIT(27)
 129 #define NFC_SEND_CMD3           BIT(28)
 130 #define NFC_SEND_CMD4           BIT(29)
 131 #define NFC_CMD_TYPE_MSK        (0x3 << 30)
 132 #define NFC_NORMAL_OP           (0 << 30)
 133 #define NFC_ECC_OP              (1 << 30)
 134 #define NFC_PAGE_OP             (2 << 30)
 135
 136 /* define bit use in NFC_RCMD_SET */
 137 #define NFC_READ_CMD_MSK        0xff
 138 #define NFC_RND_READ_CMD0_MSK   (0xff << 8)
 139 #define NFC_RND_READ_CMD1_MSK   (0xff << 16)
 140
 141 /* define bit use in NFC_WCMD_SET */
 142 #define NFC_PROGRAM_CMD_MSK     0xff
 143 #define NFC_RND_WRITE_CMD_MSK   (0xff << 8)
 144 #define NFC_READ_CMD0_MSK       (0xff << 16)
 145 #define NFC_READ_CMD1_MSK       (0xff << 24)
 146
 147 /* define bit use in NFC_ECC_CTL */
 148 #define NFC_ECC_EN              BIT(0)
 149 #define NFC_ECC_PIPELINE        BIT(3)
 150 #define NFC_ECC_EXCEPTION       BIT(4)
 151 #define NFC_ECC_BLOCK_SIZE_MSK  BIT(5)
 152 #define NFC_ECC_BLOCK_512       (1 << 5)
 153 #define NFC_RANDOM_EN           BIT(9)
 154 #define NFC_RANDOM_DIRECTION    BIT(10)
 155 #define NFC_ECC_MODE_MSK        (0xf << 12)
 156 #define NFC_ECC_MODE(x)         ((x) << 12)
 157 #define NFC_RANDOM_SEED_MSK     (0x7fff << 16)
 158 #define NFC_RANDOM_SEED(x)      ((x) << 16)
 159
 160 /* define bit use in NFC_ECC_ST */
 161 #define NFC_ECC_ERR(x)          BIT(x)
 162 #define NFC_ECC_PAT_FOUND(x)    BIT(x + 16)
 163 #define NFC_ECC_ERR_CNT(b, x)   (((x) >> ((b) * 8)) & 0xff)
 164
 165 #define NFC_DEFAULT_TIMEOUT_MS  1000
 166
 167 #define NFC_SRAM_SIZE           1024
 168
 169 #define NFC_MAX_CS              7
 170
 171 /*
 172  * Ready/Busy detection type: describes the Ready/Busy detection modes
 173  *
 174  * @RB_NONE:    no external detection available, rely on STATUS command
 175  *              and software timeouts
 176  * @RB_NATIVE:  use sunxi NAND controller Ready/Busy support. The Ready/Busy
 177  *              pin of the NAND flash chip must be connected to one of the
 178  *              native NAND R/B pins (those which can be muxed to the NAND
 179  *              Controller)
 180  * @RB_GPIO:    use a simple GPIO to handle Ready/Busy status. The Ready/Busy
 181  *              pin of the NAND flash chip must be connected to a GPIO capable
 182  *              pin.
 183  */
 184 enum sunxi_nand_rb_type {
 185         RB_NONE,
 186         RB_NATIVE,
 187         RB_GPIO,
 188 };
 189
 190 /*
 191  * Ready/Busy structure: stores information related to Ready/Busy detection
 192  *
 193  * @type:       the Ready/Busy detection mode
 194  * @info:       information related to the R/B detection mode. Either a gpio
 195  *              id or a native R/B id (those supported by the NAND controller).
 196  */
 197 struct sunxi_nand_rb {
 198         enum sunxi_nand_rb_type type;
 199         union {
 200                 struct gpio_desc gpio;
 201                 int nativeid;
 202         } info;
 203 };
 204
 205 /*
 206  * Chip Select structure: stores information related to NAND Chip Select
 207  *
 208  * @cs:         the NAND CS id used to communicate with a NAND Chip
 209  * @rb:         the Ready/Busy description
 210  */
 211 struct sunxi_nand_chip_sel {
 212         u8 cs;
 213         struct sunxi_nand_rb rb;
 214 };
 215
 216 /*
 217  * sunxi HW ECC infos: stores information related to HW ECC support
 218  *
 219  * @mode:       the sunxi ECC mode field deduced from ECC requirements
 220  * @layout:     the OOB layout depending on the ECC requirements and the
 221  *              selected ECC mode
 222  */
 223 struct sunxi_nand_hw_ecc {
 224         int mode;
 225         struct nand_ecclayout layout;
 226 };
 227
 228 /*
 229  * NAND chip structure: stores NAND chip device related information
 230  *
 231  * @node:               used to store NAND chips into a list
 232  * @nand:               base NAND chip structure
 233  * @mtd:                base MTD structure
 234  * @clk_rate:           clk_rate required for this NAND chip
 235  * @timing_cfg          TIMING_CFG register value for this NAND chip
 236  * @selected:           current active CS
 237  * @nsels:              number of CS lines required by the NAND chip
 238  * @sels:               array of CS lines descriptions
 239  */
 240 struct sunxi_nand_chip {
 241         struct list_head node;
 242         struct nand_chip nand;
 243         unsigned long clk_rate;
 244         u32 timing_cfg;
 245         u32 timing_ctl;
 246         int selected;
 247         int addr_cycles;
 248         u32 addr[2];
 249         int cmd_cycles;
 250         u8 cmd[2];
 251         int nsels;
 252         struct sunxi_nand_chip_sel sels[0];
 253 };
 254
 255 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
 256 {
 257         return container_of(nand, struct sunxi_nand_chip, nand);
 258 }
 259
 260 /*
 261  * NAND Controller structure: stores sunxi NAND controller information
 262  *
 263  * @controller:         base controller structure
 264  * @dev:                parent device (used to print error messages)
 265  * @regs:               NAND controller registers
 266  * @ahb_clk:            NAND Controller AHB clock
 267  * @mod_clk:            NAND Controller mod clock
 268  * @assigned_cs:        bitmask describing already assigned CS lines
 269  * @clk_rate:           NAND controller current clock rate
 270  * @chips:              a list containing all the NAND chips attached to
 271  *                      this NAND controller
 272  * @complete:           a completion object used to wait for NAND
 273  *                      controller events
 274  */
 275 struct sunxi_nfc {
 276         struct nand_hw_control controller;
 277         struct device *dev;
 278         void __iomem *regs;
 279         struct clk *ahb_clk;
 280         struct clk *mod_clk;
 281         unsigned long assigned_cs;
 282         unsigned long clk_rate;
 283         struct list_head chips;
 284 };
 285
 286 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
 287 {
 288         return container_of(ctrl, struct sunxi_nfc, controller);
 289 }
 290
 291 static void sunxi_nfc_set_clk_rate(unsigned long hz)
 292 {
 293         struct sunxi_ccm_reg *const ccm =
 294         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 295         int div_m, div_n;
 296
 297         div_m = (clock_get_pll6() + hz - 1) / hz;
 298         for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
 299                 if (div_m % 2)
 300                         div_m++;
 301                 div_m >>= 1;
 302         }
 303         if (div_m > 16)
 304                 div_m = 16;
 305
 306         /* config mod clock */
 307         writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
 308                CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
 309                &ccm->nand0_clk_cfg);
 310
 311         /* gate on nand clock */
 312         setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
 313 #ifdef CONFIG_MACH_SUN9I
 314         setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 315 #else
 316         setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
 317 #endif
 318 }
 319
 320 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
 321                               unsigned int timeout_ms)
 322 {
 323         unsigned int timeout_ticks;
 324         u32 time_start, status;
 325         int ret = -ETIMEDOUT;
 326
 327         if (!timeout_ms)
 328                 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
 329
 330         timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
 331
 332         time_start = get_timer(0);
 333
 334         do {
 335                 status = readl(nfc->regs + NFC_REG_ST);
 336                 if ((status & flags) == flags) {
 337                         ret = 0;
 338                         break;
 339                 }
 340
 341                 udelay(1);
 342         } while (get_timer(time_start) < timeout_ticks);
 343
 344         writel(status & flags, nfc->regs + NFC_REG_ST);
 345
 346         return ret;
 347 }
 348
 349 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
 350 {
 351         unsigned long timeout = (CONFIG_SYS_HZ *
 352                                  NFC_DEFAULT_TIMEOUT_MS) / 1000;
 353         u32 time_start;
 354
 355         time_start = get_timer(0);
 356         do {
 357                 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
 358                         return 0;
 359         } while (get_timer(time_start) < timeout);
 360
 361         dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
 362         return -ETIMEDOUT;
 363 }
 364
 365 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
 366 {
 367         unsigned long timeout = (CONFIG_SYS_HZ *
 368                                  NFC_DEFAULT_TIMEOUT_MS) / 1000;
 369         u32 time_start;
 370
 371         writel(0, nfc->regs + NFC_REG_ECC_CTL);
 372         writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
 373
 374         time_start = get_timer(0);
 375         do {
 376                 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
 377                         return 0;
 378         } while (get_timer(time_start) < timeout);
 379
 380         dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
 381         return -ETIMEDOUT;
 382 }
 383
 384 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
 385 {
 386         struct nand_chip *nand = mtd_to_nand(mtd);
 387         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 388         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 389         struct sunxi_nand_rb *rb;
 390         unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
 391         int ret;
 392
 393         if (sunxi_nand->selected < 0)
 394                 return 0;
 395
 396         rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
 397
 398         switch (rb->type) {
 399         case RB_NATIVE:
 400                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 401                          NFC_RB_STATE(rb->info.nativeid));
 402                 if (ret)
 403                         break;
 404
 405                 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
 406                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 407                          NFC_RB_STATE(rb->info.nativeid));
 408                 break;
 409         case RB_GPIO:
 410                 ret = dm_gpio_get_value(&rb->info.gpio);
 411                 break;
 412         case RB_NONE:
 413         default:
 414                 ret = 0;
 415                 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
 416                 break;
 417         }
 418
 419         return ret;
 420 }
 421
 422 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
 423 {
 424         struct nand_chip *nand = mtd_to_nand(mtd);
 425         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 426         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 427         struct sunxi_nand_chip_sel *sel;
 428         u32 ctl;
 429
 430         if (chip > 0 && chip >= sunxi_nand->nsels)
 431                 return;
 432
 433         if (chip == sunxi_nand->selected)
 434                 return;
 435
 436         ctl = readl(nfc->regs + NFC_REG_CTL) &
 437               ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
 438
 439         if (chip >= 0) {
 440                 sel = &sunxi_nand->sels[chip];
 441
 442                 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
 443                        NFC_PAGE_SHIFT(nand->page_shift - 10);
 444                 if (sel->rb.type == RB_NONE) {
 445                         nand->dev_ready = NULL;
 446                 } else {
 447                         nand->dev_ready = sunxi_nfc_dev_ready;
 448                         if (sel->rb.type == RB_NATIVE)
 449                                 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
 450                 }
 451
 452                 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
 453
 454                 if (nfc->clk_rate != sunxi_nand->clk_rate) {
 455                         sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
 456                         nfc->clk_rate = sunxi_nand->clk_rate;
 457                 }
 458         }
 459
 460         writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
 461         writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
 462         writel(ctl, nfc->regs + NFC_REG_CTL);
 463
 464         sunxi_nand->selected = chip;
 465 }
 466
 467 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 468 {
 469         struct nand_chip *nand = mtd_to_nand(mtd);
 470         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 471         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 472         int ret;
 473         int cnt;
 474         int offs = 0;
 475         u32 tmp;
 476
 477         while (len > offs) {
 478                 cnt = min(len - offs, NFC_SRAM_SIZE);
 479
 480                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 481                 if (ret)
 482                         break;
 483
 484                 writel(cnt, nfc->regs + NFC_REG_CNT);
 485                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
 486                 writel(tmp, nfc->regs + NFC_REG_CMD);
 487
 488                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 489                 if (ret)
 490                         break;
 491
 492                 if (buf)
 493                         memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
 494                                       cnt);
 495                 offs += cnt;
 496         }
 497 }
 498
 499 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 500                                 int len)
 501 {
 502         struct nand_chip *nand = mtd_to_nand(mtd);
 503         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 504         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 505         int ret;
 506         int cnt;
 507         int offs = 0;
 508         u32 tmp;
 509
 510         while (len > offs) {
 511                 cnt = min(len - offs, NFC_SRAM_SIZE);
 512
 513                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 514                 if (ret)
 515                         break;
 516
 517                 writel(cnt, nfc->regs + NFC_REG_CNT);
 518                 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
 519                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 520                       NFC_ACCESS_DIR;
 521                 writel(tmp, nfc->regs + NFC_REG_CMD);
 522
 523                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 524                 if (ret)
 525                         break;
 526
 527                 offs += cnt;
 528         }
 529 }
 530
 531 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
 532 {
 533         uint8_t ret;
 534
 535         sunxi_nfc_read_buf(mtd, &ret, 1);
 536
 537         return ret;
 538 }
 539
 540 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
 541                                unsigned int ctrl)
 542 {
 543         struct nand_chip *nand = mtd_to_nand(mtd);
 544         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 545         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 546         int ret;
 547         u32 tmp;
 548
 549         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 550         if (ret)
 551                 return;
 552
 553         if (ctrl & NAND_CTRL_CHANGE) {
 554                 tmp = readl(nfc->regs + NFC_REG_CTL);
 555                 if (ctrl & NAND_NCE)
 556                         tmp |= NFC_CE_CTL;
 557                 else
 558                         tmp &= ~NFC_CE_CTL;
 559                 writel(tmp, nfc->regs + NFC_REG_CTL);
 560         }
 561
 562         if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
 563             !(ctrl & (NAND_CLE | NAND_ALE))) {
 564                 u32 cmd = 0;
 565
 566                 if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
 567                         return;
 568
 569                 if (sunxi_nand->cmd_cycles--)
 570                         cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
 571
 572                 if (sunxi_nand->cmd_cycles--) {
 573                         cmd |= NFC_SEND_CMD2;
 574                         writel(sunxi_nand->cmd[1],
 575                                nfc->regs + NFC_REG_RCMD_SET);
 576                 }
 577
 578                 sunxi_nand->cmd_cycles = 0;
 579
 580                 if (sunxi_nand->addr_cycles) {
 581                         cmd |= NFC_SEND_ADR |
 582                                NFC_ADR_NUM(sunxi_nand->addr_cycles);
 583                         writel(sunxi_nand->addr[0],
 584                                nfc->regs + NFC_REG_ADDR_LOW);
 585                 }
 586
 587                 if (sunxi_nand->addr_cycles > 4)
 588                         writel(sunxi_nand->addr[1],
 589                                nfc->regs + NFC_REG_ADDR_HIGH);
 590
 591                 writel(cmd, nfc->regs + NFC_REG_CMD);
 592                 sunxi_nand->addr[0] = 0;
 593                 sunxi_nand->addr[1] = 0;
 594                 sunxi_nand->addr_cycles = 0;
 595                 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 596         }
 597
 598         if (ctrl & NAND_CLE) {
 599                 sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
 600         } else if (ctrl & NAND_ALE) {
 601                 sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
 602                                 dat << ((sunxi_nand->addr_cycles % 4) * 8);
 603                 sunxi_nand->addr_cycles++;
 604         }
 605 }
 606
 607 /* These seed values have been extracted from Allwinner's BSP */
 608 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
 609         0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
 610         0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
 611         0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
 612         0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
 613         0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
 614         0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
 615         0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
 616         0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
 617         0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
 618         0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
 619         0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
 620         0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
 621         0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
 622         0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
 623         0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
 624         0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 625 };
 626
 627 /*
 628  * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
 629  * have been generated using
 630  * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
 631  * the randomizer engine does internally before de/scrambling OOB data.
 632  *
 633  * Those tables are statically defined to avoid calculating randomizer state
 634  * at runtime.
 635  */
 636 static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
 637         0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
 638         0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
 639         0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
 640         0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
 641         0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
 642         0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
 643         0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
 644         0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
 645         0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
 646         0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
 647         0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
 648         0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
 649         0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
 650         0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
 651         0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
 652         0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
 653 };
 654
 655 static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
 656         0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
 657         0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
 658         0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
 659         0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
 660         0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
 661         0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
 662         0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
 663         0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
 664         0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
 665         0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
 666         0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
 667         0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
 668         0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
 669         0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
 670         0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
 671         0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
 672 };
 673
 674 static u16 sunxi_nfc_randomizer_step(u16 state, int count)
 675 {
 676         state &= 0x7fff;
 677
 678         /*
 679          * This loop is just a simple implementation of a Fibonacci LFSR using
 680          * the x16 + x15 + 1 polynomial.
 681          */
 682         while (count--)
 683                 state = ((state >> 1) |
 684                          (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
 685
 686         return state;
 687 }
 688
 689 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
 690 {
 691         const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
 692         int mod = mtd->erasesize / mtd->writesize;
 693
 694         if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
 695                 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
 696
 697         if (ecc) {
 698                 if (mtd->ecc_step_size == 512)
 699                         seeds = sunxi_nfc_randomizer_ecc512_seeds;
 700                 else
 701                         seeds = sunxi_nfc_randomizer_ecc1024_seeds;
 702         }
 703
 704         return seeds[page % mod];
 705 }
 706
 707 static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
 708                                         int page, bool ecc)
 709 {
 710         struct nand_chip *nand = mtd_to_nand(mtd);
 711         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 712         u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 713         u16 state;
 714
 715         if (!(nand->options & NAND_NEED_SCRAMBLING))
 716                 return;
 717
 718         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 719         state = sunxi_nfc_randomizer_state(mtd, page, ecc);
 720         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
 721         writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
 722 }
 723
 724 static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
 725 {
 726         struct nand_chip *nand = mtd_to_nand(mtd);
 727         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 728
 729         if (!(nand->options & NAND_NEED_SCRAMBLING))
 730                 return;
 731
 732         writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
 733                nfc->regs + NFC_REG_ECC_CTL);
 734 }
 735
 736 static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
 737 {
 738         struct nand_chip *nand = mtd_to_nand(mtd);
 739         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 740
 741         if (!(nand->options & NAND_NEED_SCRAMBLING))
 742                 return;
 743
 744         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
 745                nfc->regs + NFC_REG_ECC_CTL);
 746 }
 747
 748 static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
 749 {
 750         u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
 751
 752         bbm[0] ^= state;
 753         bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
 754 }
 755
 756 static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
 757                                            const uint8_t *buf, int len,
 758                                            bool ecc, int page)
 759 {
 760         sunxi_nfc_randomizer_config(mtd, page, ecc);
 761         sunxi_nfc_randomizer_enable(mtd);
 762         sunxi_nfc_write_buf(mtd, buf, len);
 763         sunxi_nfc_randomizer_disable(mtd);
 764 }
 765
 766 static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
 767                                           int len, bool ecc, int page)
 768 {
 769         sunxi_nfc_randomizer_config(mtd, page, ecc);
 770         sunxi_nfc_randomizer_enable(mtd);
 771         sunxi_nfc_read_buf(mtd, buf, len);
 772         sunxi_nfc_randomizer_disable(mtd);
 773 }
 774
 775 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
 776 {
 777         struct nand_chip *nand = mtd_to_nand(mtd);
 778         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 779         struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
 780         u32 ecc_ctl;
 781
 782         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 783         ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
 784                      NFC_ECC_BLOCK_SIZE_MSK);
 785         ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
 786
 787         if (nand->ecc.size == 512)
 788                 ecc_ctl |= NFC_ECC_BLOCK_512;
 789
 790         writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
 791 }
 792
 793 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
 794 {
 795         struct nand_chip *nand = mtd_to_nand(mtd);
 796         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 797
 798         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
 799                nfc->regs + NFC_REG_ECC_CTL);
 800 }
 801
 802 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
 803 {
 804         buf[0] = user_data;
 805         buf[1] = user_data >> 8;
 806         buf[2] = user_data >> 16;
 807         buf[3] = user_data >> 24;
 808 }
 809
 810 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
 811                                        u8 *data, int data_off,
 812                                        u8 *oob, int oob_off,
 813                                        int *cur_off,
 814                                        unsigned int *max_bitflips,
 815                                        bool bbm, int page)
 816 {
 817         struct nand_chip *nand = mtd_to_nand(mtd);
 818         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 819         struct nand_ecc_ctrl *ecc = &nand->ecc;
 820         int raw_mode = 0;
 821         u32 status;
 822         int ret;
 823
 824         if (*cur_off != data_off)
 825                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 826
 827         sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
 828
 829         if (data_off + ecc->size != oob_off)
 830                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 831
 832         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 833         if (ret)
 834                 return ret;
 835
 836         sunxi_nfc_randomizer_enable(mtd);
 837         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
 838                nfc->regs + NFC_REG_CMD);
 839
 840         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 841         sunxi_nfc_randomizer_disable(mtd);
 842         if (ret)
 843                 return ret;
 844
 845         *cur_off = oob_off + ecc->bytes + 4;
 846
 847         status = readl(nfc->regs + NFC_REG_ECC_ST);
 848         if (status & NFC_ECC_PAT_FOUND(0)) {
 849                 u8 pattern = 0xff;
 850
 851                 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
 852                         pattern = 0x0;
 853
 854                 memset(data, pattern, ecc->size);
 855                 memset(oob, pattern, ecc->bytes + 4);
 856
 857                 return 1;
 858         }
 859
 860         ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
 861
 862         memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
 863
 864         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 865         sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
 866
 867         if (status & NFC_ECC_ERR(0)) {
 868                 /*
 869                  * Re-read the data with the randomizer disabled to identify
 870                  * bitflips in erased pages.
 871                  */
 872                 if (nand->options & NAND_NEED_SCRAMBLING) {
 873                         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 874                         nand->read_buf(mtd, data, ecc->size);
 875                         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 876                         nand->read_buf(mtd, oob, ecc->bytes + 4);
 877                 }
 878
 879                 ret = nand_check_erased_ecc_chunk(data, ecc->size,
 880                                                   oob, ecc->bytes + 4,
 881                                                   NULL, 0, ecc->strength);
 882                 if (ret >= 0)
 883                         raw_mode = 1;
 884         } else {
 885                 /*
 886                  * The engine protects 4 bytes of OOB data per chunk.
 887                  * Retrieve the corrected OOB bytes.
 888                  */
 889                 sunxi_nfc_user_data_to_buf(readl(nfc->regs +
 890                                                  NFC_REG_USER_DATA(0)),
 891                                            oob);
 892
 893                 /* De-randomize the Bad Block Marker. */
 894                 if (bbm && nand->options & NAND_NEED_SCRAMBLING)
 895                         sunxi_nfc_randomize_bbm(mtd, page, oob);
 896         }
 897
 898         if (ret < 0) {
 899                 mtd->ecc_stats.failed++;
 900         } else {
 901                 mtd->ecc_stats.corrected += ret;
 902                 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
 903         }
 904
 905         return raw_mode;
 906 }
 907
 908 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
 909                                             u8 *oob, int *cur_off,
 910                                             bool randomize, int page)
 911 {
 912         struct nand_chip *nand = mtd_to_nand(mtd);
 913         struct nand_ecc_ctrl *ecc = &nand->ecc;
 914         int offset = ((ecc->bytes + 4) * ecc->steps);
 915         int len = mtd->oobsize - offset;
 916
 917         if (len <= 0)
 918                 return;
 919
 920         if (*cur_off != offset)
 921                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
 922                               offset + mtd->writesize, -1);
 923
 924         if (!randomize)
 925                 sunxi_nfc_read_buf(mtd, oob + offset, len);
 926         else
 927                 sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
 928                                               false, page);
 929
 930         *cur_off = mtd->oobsize + mtd->writesize;
 931 }
 932
 933 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
 934 {
 935         return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
 936 }
 937
 938 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
 939                                         const u8 *data, int data_off,
 940                                         const u8 *oob, int oob_off,
 941                                         int *cur_off, bool bbm,
 942                                         int page)
 943 {
 944         struct nand_chip *nand = mtd_to_nand(mtd);
 945         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 946         struct nand_ecc_ctrl *ecc = &nand->ecc;
 947         int ret;
 948
 949         if (data_off != *cur_off)
 950                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
 951
 952         sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
 953
 954         /* Fill OOB data in */
 955         if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
 956                 u8 user_data[4];
 957
 958                 memcpy(user_data, oob, 4);
 959                 sunxi_nfc_randomize_bbm(mtd, page, user_data);
 960                 writel(sunxi_nfc_buf_to_user_data(user_data),
 961                        nfc->regs + NFC_REG_USER_DATA(0));
 962         } else {
 963                 writel(sunxi_nfc_buf_to_user_data(oob),
 964                        nfc->regs + NFC_REG_USER_DATA(0));
 965         }
 966
 967         if (data_off + ecc->size != oob_off)
 968                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
 969
 970         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 971         if (ret)
 972                 return ret;
 973
 974         sunxi_nfc_randomizer_enable(mtd);
 975         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 976                NFC_ACCESS_DIR | NFC_ECC_OP,
 977                nfc->regs + NFC_REG_CMD);
 978
 979         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 980         sunxi_nfc_randomizer_disable(mtd);
 981         if (ret)
 982                 return ret;
 983
 984         *cur_off = oob_off + ecc->bytes + 4;
 985
 986         return 0;
 987 }
 988
 989 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
 990                                              u8 *oob, int *cur_off,
 991                                              int page)
 992 {
 993         struct nand_chip *nand = mtd_to_nand(mtd);
 994         struct nand_ecc_ctrl *ecc = &nand->ecc;
 995         int offset = ((ecc->bytes + 4) * ecc->steps);
 996         int len = mtd->oobsize - offset;
 997
 998         if (len <= 0)
 999                 return;
1000
1001         if (*cur_off != offset)
1002                 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
1003                               offset + mtd->writesize, -1);
1004
1005         sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
1006
1007         *cur_off = mtd->oobsize + mtd->writesize;
1008 }
1009
1010 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
1011                                       struct nand_chip *chip, uint8_t *buf,
1012                                       int oob_required, int page)
1013 {
1014         struct nand_ecc_ctrl *ecc = &chip->ecc;
1015         unsigned int max_bitflips = 0;
1016         int ret, i, cur_off = 0;
1017         bool raw_mode = false;
1018
1019         sunxi_nfc_hw_ecc_enable(mtd);
1020
1021         for (i = 0; i < ecc->steps; i++) {
1022                 int data_off = i * ecc->size;
1023                 int oob_off = i * (ecc->bytes + 4);
1024                 u8 *data = buf + data_off;
1025                 u8 *oob = chip->oob_poi + oob_off;
1026
1027                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1028                                                   oob_off + mtd->writesize,
1029                                                   &cur_off, &max_bitflips,
1030                                                   !i, page);
1031                 if (ret < 0)
1032                         return ret;
1033                 else if (ret)
1034                         raw_mode = true;
1035         }
1036
1037         if (oob_required)
1038                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1039                                                 !raw_mode, page);
1040
1041         sunxi_nfc_hw_ecc_disable(mtd);
1042
1043         return max_bitflips;
1044 }
1045
1046 static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
1047                                          struct nand_chip *chip,
1048                                          uint32_t data_offs, uint32_t readlen,
1049                                          uint8_t *bufpoi, int page)
1050 {
1051         struct nand_ecc_ctrl *ecc = &chip->ecc;
1052         int ret, i, cur_off = 0;
1053         unsigned int max_bitflips = 0;
1054
1055         sunxi_nfc_hw_ecc_enable(mtd);
1056
1057         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1058         for (i = data_offs / ecc->size;
1059              i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1060                 int data_off = i * ecc->size;
1061                 int oob_off = i * (ecc->bytes + 4);
1062                 u8 *data = bufpoi + data_off;
1063                 u8 *oob = chip->oob_poi + oob_off;
1064
1065                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
1066                         oob, oob_off + mtd->writesize,
1067                         &cur_off, &max_bitflips, !i, page);
1068                 if (ret < 0)
1069                         return ret;
1070         }
1071
1072         sunxi_nfc_hw_ecc_disable(mtd);
1073
1074         return max_bitflips;
1075 }
1076
1077 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
1078                                        struct nand_chip *chip,
1079                                        const uint8_t *buf, int oob_required,
1080                                        int page)
1081 {
1082         struct nand_ecc_ctrl *ecc = &chip->ecc;
1083         int ret, i, cur_off = 0;
1084
1085         sunxi_nfc_hw_ecc_enable(mtd);
1086
1087         for (i = 0; i < ecc->steps; i++) {
1088                 int data_off = i * ecc->size;
1089                 int oob_off = i * (ecc->bytes + 4);
1090                 const u8 *data = buf + data_off;
1091                 const u8 *oob = chip->oob_poi + oob_off;
1092
1093                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1094                                                    oob_off + mtd->writesize,
1095                                                    &cur_off, !i, page);
1096                 if (ret)
1097                         return ret;
1098         }
1099
1100         if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1101                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1102                                                  &cur_off, page);
1103
1104         sunxi_nfc_hw_ecc_disable(mtd);
1105
1106         return 0;
1107 }
1108
1109 static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
1110                                           struct nand_chip *chip,
1111                                           u32 data_offs, u32 data_len,
1112                                           const u8 *buf, int oob_required,
1113                                           int page)
1114 {
1115         struct nand_ecc_ctrl *ecc = &chip->ecc;
1116         int ret, i, cur_off = 0;
1117
1118         sunxi_nfc_hw_ecc_enable(mtd);
1119
1120         for (i = data_offs / ecc->size;
1121              i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1122                 int data_off = i * ecc->size;
1123                 int oob_off = i * (ecc->bytes + 4);
1124                 const u8 *data = buf + data_off;
1125                 const u8 *oob = chip->oob_poi + oob_off;
1126
1127                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1128                                                    oob_off + mtd->writesize,
1129                                                    &cur_off, !i, page);
1130                 if (ret)
1131                         return ret;
1132         }
1133
1134         sunxi_nfc_hw_ecc_disable(mtd);
1135
1136         return 0;
1137 }
1138
1139 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
1140                                                struct nand_chip *chip,
1141                                                uint8_t *buf, int oob_required,
1142                                                int page)
1143 {
1144         struct nand_ecc_ctrl *ecc = &chip->ecc;
1145         unsigned int max_bitflips = 0;
1146         int ret, i, cur_off = 0;
1147         bool raw_mode = false;
1148
1149         sunxi_nfc_hw_ecc_enable(mtd);
1150
1151         for (i = 0; i < ecc->steps; i++) {
1152                 int data_off = i * (ecc->size + ecc->bytes + 4);
1153                 int oob_off = data_off + ecc->size;
1154                 u8 *data = buf + (i * ecc->size);
1155                 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1156
1157                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1158                                                   oob_off, &cur_off,
1159                                                   &max_bitflips, !i, page);
1160                 if (ret < 0)
1161                         return ret;
1162                 else if (ret)
1163                         raw_mode = true;
1164         }
1165
1166         if (oob_required)
1167                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1168                                                 !raw_mode, page);
1169
1170         sunxi_nfc_hw_ecc_disable(mtd);
1171
1172         return max_bitflips;
1173 }
1174
1175 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
1176                                                 struct nand_chip *chip,
1177                                                 const uint8_t *buf,
1178                                                 int oob_required, int page)
1179 {
1180         struct nand_ecc_ctrl *ecc = &chip->ecc;
1181         int ret, i, cur_off = 0;
1182
1183         sunxi_nfc_hw_ecc_enable(mtd);
1184
1185         for (i = 0; i < ecc->steps; i++) {
1186                 int data_off = i * (ecc->size + ecc->bytes + 4);
1187                 int oob_off = data_off + ecc->size;
1188                 const u8 *data = buf + (i * ecc->size);
1189                 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1190
1191                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
1192                                                    oob, oob_off, &cur_off,
1193                                                    false, page);
1194                 if (ret)
1195                         return ret;
1196         }
1197
1198         if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1199                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1200                                                  &cur_off, page);
1201
1202         sunxi_nfc_hw_ecc_disable(mtd);
1203
1204         return 0;
1205 }
1206
1207 static const s32 tWB_lut[] = {6, 12, 16, 20};
1208 static const s32 tRHW_lut[] = {4, 8, 12, 20};
1209
1210 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1211                 u32 clk_period)
1212 {
1213         u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1214         int i;
1215
1216         for (i = 0; i < lut_size; i++) {
1217                 if (clk_cycles <= lut[i])
1218                         return i;
1219         }
1220
1221         /* Doesn't fit */
1222         return -EINVAL;
1223 }
1224
1225 #define sunxi_nand_lookup_timing(l, p, c) \
1226                         _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1227
1228 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1229                                        const struct nand_sdr_timings *timings)
1230 {
1231         u32 min_clk_period = 0;
1232         s32 tWB, tADL, tWHR, tRHW, tCAD;
1233
1234         /* T1 <=> tCLS */
1235         if (timings->tCLS_min > min_clk_period)
1236                 min_clk_period = timings->tCLS_min;
1237
1238         /* T2 <=> tCLH */
1239         if (timings->tCLH_min > min_clk_period)
1240                 min_clk_period = timings->tCLH_min;
1241
1242         /* T3 <=> tCS */
1243         if (timings->tCS_min > min_clk_period)
1244                 min_clk_period = timings->tCS_min;
1245
1246         /* T4 <=> tCH */
1247         if (timings->tCH_min > min_clk_period)
1248                 min_clk_period = timings->tCH_min;
1249
1250         /* T5 <=> tWP */
1251         if (timings->tWP_min > min_clk_period)
1252                 min_clk_period = timings->tWP_min;
1253
1254         /* T6 <=> tWH */
1255         if (timings->tWH_min > min_clk_period)
1256                 min_clk_period = timings->tWH_min;
1257
1258         /* T7 <=> tALS */
1259         if (timings->tALS_min > min_clk_period)
1260                 min_clk_period = timings->tALS_min;
1261
1262         /* T8 <=> tDS */
1263         if (timings->tDS_min > min_clk_period)
1264                 min_clk_period = timings->tDS_min;
1265
1266         /* T9 <=> tDH */
1267         if (timings->tDH_min > min_clk_period)
1268                 min_clk_period = timings->tDH_min;
1269
1270         /* T10 <=> tRR */
1271         if (timings->tRR_min > (min_clk_period * 3))
1272                 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1273
1274         /* T11 <=> tALH */
1275         if (timings->tALH_min > min_clk_period)
1276                 min_clk_period = timings->tALH_min;
1277
1278         /* T12 <=> tRP */
1279         if (timings->tRP_min > min_clk_period)
1280                 min_clk_period = timings->tRP_min;
1281
1282         /* T13 <=> tREH */
1283         if (timings->tREH_min > min_clk_period)
1284                 min_clk_period = timings->tREH_min;
1285
1286         /* T14 <=> tRC */
1287         if (timings->tRC_min > (min_clk_period * 2))
1288                 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1289
1290         /* T15 <=> tWC */
1291         if (timings->tWC_min > (min_clk_period * 2))
1292                 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1293
1294         /* T16 - T19 + tCAD */
1295         tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1296                                         min_clk_period);
1297         if (tWB < 0) {
1298                 dev_err(nfc->dev, "unsupported tWB\n");
1299                 return tWB;
1300         }
1301
1302         tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1303         if (tADL > 3) {
1304                 dev_err(nfc->dev, "unsupported tADL\n");
1305                 return -EINVAL;
1306         }
1307
1308         tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1309         if (tWHR > 3) {
1310                 dev_err(nfc->dev, "unsupported tWHR\n");
1311                 return -EINVAL;
1312         }
1313
1314         tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1315                                         min_clk_period);
1316         if (tRHW < 0) {
1317                 dev_err(nfc->dev, "unsupported tRHW\n");
1318                 return tRHW;
1319         }
1320
1321         /*
1322          * TODO: according to ONFI specs this value only applies for DDR NAND,
1323          * but Allwinner seems to set this to 0x7. Mimic them for now.
1324          */
1325         tCAD = 0x7;
1326
1327         /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1328         chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1329
1330         /*
1331          * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1332          * output cycle timings shall be used if the host drives tRC less than
1333          * 30 ns.
1334          */
1335         chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
1336
1337         /* Convert min_clk_period from picoseconds to nanoseconds */
1338         min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1339
1340         /*
1341          * Convert min_clk_period into a clk frequency, then get the
1342          * appropriate rate for the NAND controller IP given this formula
1343          * (specified in the datasheet):
1344          * nand clk_rate = min_clk_rate
1345          */
1346         chip->clk_rate = 1000000000L / min_clk_period;
1347
1348         return 0;
1349 }
1350
1351 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
1352 {
1353         struct mtd_info *mtd = nand_to_mtd(&chip->nand);
1354         const struct nand_sdr_timings *timings;
1355         int ret;
1356         int mode;
1357
1358         mode = onfi_get_async_timing_mode(&chip->nand);
1359         if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1360                 mode = chip->nand.onfi_timing_mode_default;
1361         } else {
1362                 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1363                 int i;
1364
1365                 mode = fls(mode) - 1;
1366                 if (mode < 0)
1367                         mode = 0;
1368
1369                 feature[0] = mode;
1370                 for (i = 0; i < chip->nsels; i++) {
1371                         chip->nand.select_chip(mtd, i);
1372                         ret = chip->nand.onfi_set_features(mtd,
1373                                                 &chip->nand,
1374                                                 ONFI_FEATURE_ADDR_TIMING_MODE,
1375                                                 feature);
1376                         chip->nand.select_chip(mtd, -1);
1377                         if (ret && ret != -ENOTSUPP)
1378                                 return ret;
1379                 }
1380         }
1381
1382         timings = onfi_async_timing_mode_to_sdr_timings(mode);
1383         if (IS_ERR(timings))
1384                 return PTR_ERR(timings);
1385
1386         return sunxi_nand_chip_set_timings(chip, timings);
1387 }
1388
1389 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1390                                               struct nand_ecc_ctrl *ecc)
1391 {
1392         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1393         struct sunxi_nand_hw_ecc *data;
1394         struct nand_ecclayout *layout;
1395         int nsectors;
1396         int ret;
1397         int i;
1398
1399         data = kzalloc(sizeof(*data), GFP_KERNEL);
1400         if (!data)
1401                 return -ENOMEM;
1402
1403         if (ecc->size != 512 && ecc->size != 1024)
1404                 return -EINVAL;
1405
1406         /* Prefer 1k ECC chunk over 512 ones */
1407         if (ecc->size == 512 && mtd->writesize > 512) {
1408                 ecc->size = 1024;
1409                 ecc->strength *= 2;
1410         }
1411
1412         /* Add ECC info retrieval from DT */
1413         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1414                 if (ecc->strength <= strengths[i]) {
1415                         /*
1416                          * Update ecc->strength value with the actual strength
1417                          * that will be used by the ECC engine.
1418                          */
1419                         ecc->strength = strengths[i];
1420                         break;
1421                 }
1422         }
1423
1424         if (i >= ARRAY_SIZE(strengths)) {
1425                 dev_err(nfc->dev, "unsupported strength\n");
1426                 ret = -ENOTSUPP;
1427                 goto err;
1428         }
1429
1430         data->mode = i;
1431
1432         /* HW ECC always request ECC bytes for 1024 bytes blocks */
1433         ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1434
1435         /* HW ECC always work with even numbers of ECC bytes */
1436         ecc->bytes = ALIGN(ecc->bytes, 2);
1437
1438         layout = &data->layout;
1439         nsectors = mtd->writesize / ecc->size;
1440
1441         if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1442                 ret = -EINVAL;
1443                 goto err;
1444         }
1445
1446         layout->eccbytes = (ecc->bytes * nsectors);
1447
1448         ecc->layout = layout;
1449         ecc->priv = data;
1450
1451         return 0;
1452
1453 err:
1454         kfree(data);
1455
1456         return ret;
1457 }
1458
1459 #ifndef __UBOOT__
1460 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1461 {
1462         kfree(ecc->priv);
1463 }
1464 #endif /* __UBOOT__ */
1465
1466 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1467                                        struct nand_ecc_ctrl *ecc)
1468 {
1469         struct nand_ecclayout *layout;
1470         int nsectors;
1471         int i, j;
1472         int ret;
1473
1474         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1475         if (ret)
1476                 return ret;
1477
1478         ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1479         ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1480         ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1481         ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1482         layout = ecc->layout;
1483         nsectors = mtd->writesize / ecc->size;
1484
1485         for (i = 0; i < nsectors; i++) {
1486                 if (i) {
1487                         layout->oobfree[i].offset =
1488                                 layout->oobfree[i - 1].offset +
1489                                 layout->oobfree[i - 1].length +
1490                                 ecc->bytes;
1491                         layout->oobfree[i].length = 4;
1492                 } else {
1493                         /*
1494                          * The first 2 bytes are used for BB markers, hence we
1495                          * only have 2 bytes available in the first user data
1496                          * section.
1497                          */
1498                         layout->oobfree[i].length = 2;
1499                         layout->oobfree[i].offset = 2;
1500                 }
1501
1502                 for (j = 0; j < ecc->bytes; j++)
1503                         layout->eccpos[(ecc->bytes * i) + j] =
1504                                         layout->oobfree[i].offset +
1505                                         layout->oobfree[i].length + j;
1506         }
1507
1508         if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1509                 layout->oobfree[nsectors].offset =
1510                                 layout->oobfree[nsectors - 1].offset +
1511                                 layout->oobfree[nsectors - 1].length +
1512                                 ecc->bytes;
1513                 layout->oobfree[nsectors].length = mtd->oobsize -
1514                                 ((ecc->bytes + 4) * nsectors);
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1521                                                 struct nand_ecc_ctrl *ecc)
1522 {
1523         struct nand_ecclayout *layout;
1524         int nsectors;
1525         int i;
1526         int ret;
1527
1528         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1529         if (ret)
1530                 return ret;
1531
1532         ecc->prepad = 4;
1533         ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1534         ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1535
1536         layout = ecc->layout;
1537         nsectors = mtd->writesize / ecc->size;
1538
1539         for (i = 0; i < (ecc->bytes * nsectors); i++)
1540                 layout->eccpos[i] = i;
1541
1542         layout->oobfree[0].length = mtd->oobsize - i;
1543         layout->oobfree[0].offset = i;
1544
1545         return 0;
1546 }
1547
1548 #ifndef __UBOOT__
1549 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1550 {
1551         switch (ecc->mode) {
1552         case NAND_ECC_HW:
1553         case NAND_ECC_HW_SYNDROME:
1554                 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1555                 break;
1556         case NAND_ECC_NONE:
1557                 kfree(ecc->layout);
1558         default:
1559                 break;
1560         }
1561 }
1562 #endif /* __UBOOT__ */
1563
1564 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
1565 {
1566         struct nand_chip *nand = mtd_to_nand(mtd);
1567         int ret;
1568
1569         if (!ecc->size) {
1570                 ecc->size = nand->ecc_step_ds;
1571                 ecc->strength = nand->ecc_strength_ds;
1572         }
1573
1574         if (!ecc->size || !ecc->strength)
1575                 return -EINVAL;
1576
1577         switch (ecc->mode) {
1578         case NAND_ECC_SOFT_BCH:
1579                 break;
1580         case NAND_ECC_HW:
1581                 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
1582                 if (ret)
1583                         return ret;
1584                 break;
1585         case NAND_ECC_HW_SYNDROME:
1586                 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
1587                 if (ret)
1588                         return ret;
1589                 break;
1590         case NAND_ECC_NONE:
1591                 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1592                 if (!ecc->layout)
1593                         return -ENOMEM;
1594                 ecc->layout->oobfree[0].length = mtd->oobsize;
1595         case NAND_ECC_SOFT:
1596                 break;
1597         default:
1598                 return -EINVAL;
1599         }
1600
1601         return 0;
1602 }
1603
1604 static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
1605 {
1606         const struct nand_sdr_timings *timings;
1607         const void *blob = gd->fdt_blob;
1608         struct sunxi_nand_chip *chip;
1609         struct mtd_info *mtd;
1610         struct nand_chip *nand;
1611         int nsels;
1612         int ret;
1613         int i;
1614         u32 cs[8], rb[8];
1615
1616         if (!fdt_getprop(blob, node, "reg", &nsels))
1617                 return -EINVAL;
1618
1619         nsels /= sizeof(u32);
1620         if (!nsels || nsels > 8) {
1621                 dev_err(dev, "invalid reg property size\n");
1622                 return -EINVAL;
1623         }
1624
1625         chip = kzalloc(sizeof(*chip) +
1626                        (nsels * sizeof(struct sunxi_nand_chip_sel)),
1627                        GFP_KERNEL);
1628         if (!chip) {
1629                 dev_err(dev, "could not allocate chip\n");
1630                 return -ENOMEM;
1631         }
1632
1633         chip->nsels = nsels;
1634         chip->selected = -1;
1635
1636         for (i = 0; i < nsels; i++) {
1637                 cs[i] = -1;
1638                 rb[i] = -1;
1639         }
1640
1641         ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
1642         if (ret) {
1643                 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1644                 return ret;
1645         }
1646
1647         ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
1648                                    nsels);
1649         if (ret) {
1650                 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1651                 return ret;
1652         }
1653
1654         for (i = 0; i < nsels; i++) {
1655                 int tmp = cs[i];
1656
1657                 if (tmp > NFC_MAX_CS) {
1658                         dev_err(dev,
1659                                 "invalid reg value: %u (max CS = 7)\n",
1660                                 tmp);
1661                         return -EINVAL;
1662                 }
1663
1664                 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1665                         dev_err(dev, "CS %d already assigned\n", tmp);
1666                         return -EINVAL;
1667                 }
1668
1669                 chip->sels[i].cs = tmp;
1670
1671                 tmp = rb[i];
1672                 if (tmp >= 0 && tmp < 2) {
1673                         chip->sels[i].rb.type = RB_NATIVE;
1674                         chip->sels[i].rb.info.nativeid = tmp;
1675                 } else {
1676                         ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
1677                                                 "rb-gpios", i,
1678                                                 &chip->sels[i].rb.info.gpio,
1679                                                 GPIOD_IS_IN);
1680                         if (ret)
1681                                 chip->sels[i].rb.type = RB_GPIO;
1682                         else
1683                                 chip->sels[i].rb.type = RB_NONE;
1684                 }
1685         }
1686
1687         timings = onfi_async_timing_mode_to_sdr_timings(0);
1688         if (IS_ERR(timings)) {
1689                 ret = PTR_ERR(timings);
1690                 dev_err(dev,
1691                         "could not retrieve timings for ONFI mode 0: %d\n",
1692                         ret);
1693                 return ret;
1694         }
1695
1696         ret = sunxi_nand_chip_set_timings(chip, timings);
1697         if (ret) {
1698                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1699                 return ret;
1700         }
1701
1702         nand = &chip->nand;
1703         /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1704         nand->chip_delay = 200;
1705         nand->controller = &nfc->controller;
1706         /*
1707          * Set the ECC mode to the default value in case nothing is specified
1708          * in the DT.
1709          */
1710         nand->ecc.mode = NAND_ECC_HW;
1711         nand->flash_node = node;
1712         nand->select_chip = sunxi_nfc_select_chip;
1713         nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1714         nand->read_buf = sunxi_nfc_read_buf;
1715         nand->write_buf = sunxi_nfc_write_buf;
1716         nand->read_byte = sunxi_nfc_read_byte;
1717
1718         mtd = nand_to_mtd(nand);
1719         ret = nand_scan_ident(mtd, nsels, NULL);
1720         if (ret)
1721                 return ret;
1722
1723         if (nand->bbt_options & NAND_BBT_USE_FLASH)
1724                 nand->bbt_options |= NAND_BBT_NO_OOB;
1725
1726         if (nand->options & NAND_NEED_SCRAMBLING)
1727                 nand->options |= NAND_NO_SUBPAGE_WRITE;
1728
1729         nand->options |= NAND_SUBPAGE_READ;
1730
1731         ret = sunxi_nand_chip_init_timings(chip);
1732         if (ret) {
1733                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1734                 return ret;
1735         }
1736
1737         ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
1738         if (ret) {
1739                 dev_err(dev, "ECC init failed: %d\n", ret);
1740                 return ret;
1741         }
1742
1743         ret = nand_scan_tail(mtd);
1744         if (ret) {
1745                 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1746                 return ret;
1747         }
1748
1749         ret = nand_register(devnum, mtd);
1750         if (ret) {
1751                 dev_err(dev, "failed to register mtd device: %d\n", ret);
1752                 return ret;
1753         }
1754
1755         list_add_tail(&chip->node, &nfc->chips);
1756
1757         return 0;
1758 }
1759
1760 static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
1761 {
1762         const void *blob = gd->fdt_blob;
1763         int nand_node;
1764         int ret, i = 0;
1765
1766         for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1767              nand_node = fdt_next_subnode(blob, nand_node))
1768                 i++;
1769
1770         if (i > 8) {
1771                 dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
1772                 return -EINVAL;
1773         }
1774
1775         i = 0;
1776         for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1777              nand_node = fdt_next_subnode(blob, nand_node)) {
1778                 ret = sunxi_nand_chip_init(nand_node, nfc, i++);
1779                 if (ret)
1780                         return ret;
1781         }
1782
1783         return 0;
1784 }
1785
1786 #ifndef __UBOOT__
1787 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1788 {
1789         struct sunxi_nand_chip *chip;
1790
1791         while (!list_empty(&nfc->chips)) {
1792                 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1793                                         node);
1794                 nand_release(&chip->mtd);
1795                 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1796                 list_del(&chip->node);
1797                 kfree(chip);
1798         }
1799 }
1800 #endif /* __UBOOT__ */
1801
1802 void sunxi_nand_init(void)
1803 {
1804         const void *blob = gd->fdt_blob;
1805         struct sunxi_nfc *nfc;
1806         fdt_addr_t regs;
1807         int node;
1808         int ret;
1809
1810         nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
1811         if (!nfc)
1812                 return;
1813
1814         spin_lock_init(&nfc->controller.lock);
1815         init_waitqueue_head(&nfc->controller.wq);
1816         INIT_LIST_HEAD(&nfc->chips);
1817
1818         node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
1819         if (node < 0) {
1820                 pr_err("unable to find nfc node in device tree\n");
1821                 goto err;
1822         }
1823
1824         if (!fdtdec_get_is_enabled(blob, node)) {
1825                 pr_err("nfc disabled in device tree\n");
1826                 goto err;
1827         }
1828
1829         regs = fdtdec_get_addr(blob, node, "reg");
1830         if (regs == FDT_ADDR_T_NONE) {
1831                 pr_err("unable to find nfc address in device tree\n");
1832                 goto err;
1833         }
1834
1835         nfc->regs = (void *)regs;
1836
1837         ret = sunxi_nfc_rst(nfc);
1838         if (ret)
1839                 goto err;
1840
1841         ret = sunxi_nand_chips_init(node, nfc);
1842         if (ret) {
1843                 dev_err(dev, "failed to init nand chips\n");
1844                 goto err;
1845         }
1846
1847         return;
1848
1849 err:
1850         kfree(nfc);
1851 }
1852
1853 MODULE_LICENSE("GPL v2");
1854 MODULE_AUTHOR("Boris BREZILLON");
1855 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");