drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2019
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <nand.h>
  12 #include <reset.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/ioport.h>
  17
  18 /* Bad block marker length */
  19 #define FMC2_BBM_LEN                    2
  20
  21 /* ECC step size */
  22 #define FMC2_ECC_STEP_SIZE              512
  23
  24 /* Command delay */
  25 #define FMC2_RB_DELAY_US                30
  26
  27 /* Max chip enable */
  28 #define FMC2_MAX_CE                     2
  29
  30 /* Timings */
  31 #define FMC2_THIZ                       1
  32 #define FMC2_TIO                        8000
  33 #define FMC2_TSYNC                      3000
  34 #define FMC2_PCR_TIMING_MASK            0xf
  35 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  36
  37 /* FMC2 Controller Registers */
  38 #define FMC2_BCR1                       0x0
  39 #define FMC2_PCR                        0x80
  40 #define FMC2_SR                         0x84
  41 #define FMC2_PMEM                       0x88
  42 #define FMC2_PATT                       0x8c
  43 #define FMC2_HECCR                      0x94
  44 #define FMC2_BCHISR                     0x254
  45 #define FMC2_BCHICR                     0x258
  46 #define FMC2_BCHPBR1                    0x260
  47 #define FMC2_BCHPBR2                    0x264
  48 #define FMC2_BCHPBR3                    0x268
  49 #define FMC2_BCHPBR4                    0x26c
  50 #define FMC2_BCHDSR0                    0x27c
  51 #define FMC2_BCHDSR1                    0x280
  52 #define FMC2_BCHDSR2                    0x284
  53 #define FMC2_BCHDSR3                    0x288
  54 #define FMC2_BCHDSR4                    0x28c
  55
  56 /* Register: FMC2_BCR1 */
  57 #define FMC2_BCR1_FMC2EN                BIT(31)
  58
  59 /* Register: FMC2_PCR */
  60 #define FMC2_PCR_PWAITEN                BIT(1)
  61 #define FMC2_PCR_PBKEN                  BIT(2)
  62 #define FMC2_PCR_PWID_MASK              GENMASK(5, 4)
  63 #define FMC2_PCR_PWID(x)                (((x) & 0x3) << 4)
  64 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  65 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  66 #define FMC2_PCR_ECCEN                  BIT(6)
  67 #define FMC2_PCR_ECCALG                 BIT(8)
  68 #define FMC2_PCR_TCLR_MASK              GENMASK(12, 9)
  69 #define FMC2_PCR_TCLR(x)                (((x) & 0xf) << 9)
  70 #define FMC2_PCR_TCLR_DEFAULT           0xf
  71 #define FMC2_PCR_TAR_MASK               GENMASK(16, 13)
  72 #define FMC2_PCR_TAR(x)                 (((x) & 0xf) << 13)
  73 #define FMC2_PCR_TAR_DEFAULT            0xf
  74 #define FMC2_PCR_ECCSS_MASK             GENMASK(19, 17)
  75 #define FMC2_PCR_ECCSS(x)               (((x) & 0x7) << 17)
  76 #define FMC2_PCR_ECCSS_512              1
  77 #define FMC2_PCR_ECCSS_2048             3
  78 #define FMC2_PCR_BCHECC                 BIT(24)
  79 #define FMC2_PCR_WEN                    BIT(25)
  80
  81 /* Register: FMC2_SR */
  82 #define FMC2_SR_NWRF                    BIT(6)
  83
  84 /* Register: FMC2_PMEM */
  85 #define FMC2_PMEM_MEMSET(x)             (((x) & 0xff) << 0)
  86 #define FMC2_PMEM_MEMWAIT(x)            (((x) & 0xff) << 8)
  87 #define FMC2_PMEM_MEMHOLD(x)            (((x) & 0xff) << 16)
  88 #define FMC2_PMEM_MEMHIZ(x)             (((x) & 0xff) << 24)
  89 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
  90
  91 /* Register: FMC2_PATT */
  92 #define FMC2_PATT_ATTSET(x)             (((x) & 0xff) << 0)
  93 #define FMC2_PATT_ATTWAIT(x)            (((x) & 0xff) << 8)
  94 #define FMC2_PATT_ATTHOLD(x)            (((x) & 0xff) << 16)
  95 #define FMC2_PATT_ATTHIZ(x)             (((x) & 0xff) << 24)
  96 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
  97
  98 /* Register: FMC2_BCHISR */
  99 #define FMC2_BCHISR_DERF                BIT(1)
 100 #define FMC2_BCHISR_EPBRF               BIT(4)
 101
 102 /* Register: FMC2_BCHICR */
 103 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 104
 105 /* Register: FMC2_BCHDSR0 */
 106 #define FMC2_BCHDSR0_DUE                BIT(0)
 107 #define FMC2_BCHDSR0_DEF                BIT(1)
 108 #define FMC2_BCHDSR0_DEN_MASK           GENMASK(7, 4)
 109 #define FMC2_BCHDSR0_DEN_SHIFT          4
 110
 111 /* Register: FMC2_BCHDSR1 */
 112 #define FMC2_BCHDSR1_EBP1_MASK          GENMASK(12, 0)
 113 #define FMC2_BCHDSR1_EBP2_MASK          GENMASK(28, 16)
 114 #define FMC2_BCHDSR1_EBP2_SHIFT         16
 115
 116 /* Register: FMC2_BCHDSR2 */
 117 #define FMC2_BCHDSR2_EBP3_MASK          GENMASK(12, 0)
 118 #define FMC2_BCHDSR2_EBP4_MASK          GENMASK(28, 16)
 119 #define FMC2_BCHDSR2_EBP4_SHIFT         16
 120
 121 /* Register: FMC2_BCHDSR3 */
 122 #define FMC2_BCHDSR3_EBP5_MASK          GENMASK(12, 0)
 123 #define FMC2_BCHDSR3_EBP6_MASK          GENMASK(28, 16)
 124 #define FMC2_BCHDSR3_EBP6_SHIFT         16
 125
 126 /* Register: FMC2_BCHDSR4 */
 127 #define FMC2_BCHDSR4_EBP7_MASK          GENMASK(12, 0)
 128 #define FMC2_BCHDSR4_EBP8_MASK          GENMASK(28, 16)
 129 #define FMC2_BCHDSR4_EBP8_SHIFT         16
 130
 131 #define FMC2_NSEC_PER_SEC               1000000000L
 132
 133 enum stm32_fmc2_ecc {
 134         FMC2_ECC_HAM = 1,
 135         FMC2_ECC_BCH4 = 4,
 136         FMC2_ECC_BCH8 = 8
 137 };
 138
 139 struct stm32_fmc2_timings {
 140         u8 tclr;
 141         u8 tar;
 142         u8 thiz;
 143         u8 twait;
 144         u8 thold_mem;
 145         u8 tset_mem;
 146         u8 thold_att;
 147         u8 tset_att;
 148 };
 149
 150 struct stm32_fmc2_nand {
 151         struct nand_chip chip;
 152         struct stm32_fmc2_timings timings;
 153         int ncs;
 154         int cs_used[FMC2_MAX_CE];
 155 };
 156
 157 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 158 {
 159         return container_of(chip, struct stm32_fmc2_nand, chip);
 160 }
 161
 162 struct stm32_fmc2_nfc {
 163         struct nand_hw_control base;
 164         struct stm32_fmc2_nand nand;
 165         struct nand_ecclayout ecclayout;
 166         void __iomem *io_base;
 167         void __iomem *data_base[FMC2_MAX_CE];
 168         void __iomem *cmd_base[FMC2_MAX_CE];
 169         void __iomem *addr_base[FMC2_MAX_CE];
 170         struct clk clk;
 171
 172         u8 cs_assigned;
 173         int cs_sel;
 174 };
 175
 176 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
 177 {
 178         return container_of(base, struct stm32_fmc2_nfc, base);
 179 }
 180
 181 /* Timings configuration */
 182 static void stm32_fmc2_timings_init(struct nand_chip *chip)
 183 {
 184         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 185         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 186         struct stm32_fmc2_timings *timings = &nand->timings;
 187         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 188         u32 pmem, patt;
 189
 190         /* Set tclr/tar timings */
 191         pcr &= ~FMC2_PCR_TCLR_MASK;
 192         pcr |= FMC2_PCR_TCLR(timings->tclr);
 193         pcr &= ~FMC2_PCR_TAR_MASK;
 194         pcr |= FMC2_PCR_TAR(timings->tar);
 195
 196         /* Set tset/twait/thold/thiz timings in common bank */
 197         pmem = FMC2_PMEM_MEMSET(timings->tset_mem);
 198         pmem |= FMC2_PMEM_MEMWAIT(timings->twait);
 199         pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem);
 200         pmem |= FMC2_PMEM_MEMHIZ(timings->thiz);
 201
 202         /* Set tset/twait/thold/thiz timings in attribut bank */
 203         patt = FMC2_PATT_ATTSET(timings->tset_att);
 204         patt |= FMC2_PATT_ATTWAIT(timings->twait);
 205         patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
 206         patt |= FMC2_PATT_ATTHIZ(timings->thiz);
 207
 208         writel(pcr, fmc2->io_base + FMC2_PCR);
 209         writel(pmem, fmc2->io_base + FMC2_PMEM);
 210         writel(patt, fmc2->io_base + FMC2_PATT);
 211 }
 212
 213 /* Controller configuration */
 214 static void stm32_fmc2_setup(struct nand_chip *chip)
 215 {
 216         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 217         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 218
 219         /* Configure ECC algorithm (default configuration is Hamming) */
 220         pcr &= ~FMC2_PCR_ECCALG;
 221         pcr &= ~FMC2_PCR_BCHECC;
 222         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 223                 pcr |= FMC2_PCR_ECCALG;
 224                 pcr |= FMC2_PCR_BCHECC;
 225         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 226                 pcr |= FMC2_PCR_ECCALG;
 227         }
 228
 229         /* Set buswidth */
 230         pcr &= ~FMC2_PCR_PWID_MASK;
 231         if (chip->options & NAND_BUSWIDTH_16)
 232                 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
 233
 234         /* Set ECC sector size */
 235         pcr &= ~FMC2_PCR_ECCSS_MASK;
 236         pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
 237
 238         writel(pcr, fmc2->io_base + FMC2_PCR);
 239 }
 240
 241 /* Select target */
 242 static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr)
 243 {
 244         struct nand_chip *chip = mtd_to_nand(mtd);
 245         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 246         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 247
 248         if (chipnr < 0 || chipnr >= nand->ncs)
 249                 return;
 250
 251         if (nand->cs_used[chipnr] == fmc2->cs_sel)
 252                 return;
 253
 254         fmc2->cs_sel = nand->cs_used[chipnr];
 255         chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel];
 256         chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel];
 257
 258         /* FMC2 setup routine */
 259         stm32_fmc2_setup(chip);
 260
 261         /* Apply timings */
 262         stm32_fmc2_timings_init(chip);
 263 }
 264
 265 /* Set bus width to 16-bit or 8-bit */
 266 static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
 267 {
 268         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 269
 270         pcr &= ~FMC2_PCR_PWID_MASK;
 271         if (set)
 272                 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
 273         writel(pcr, fmc2->io_base + FMC2_PCR);
 274 }
 275
 276 /* Enable/disable ECC */
 277 static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
 278 {
 279         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 280
 281         pcr &= ~FMC2_PCR_ECCEN;
 282         if (enable)
 283                 pcr |= FMC2_PCR_ECCEN;
 284         writel(pcr, fmc2->io_base + FMC2_PCR);
 285 }
 286
 287 /* Clear irq sources in case of bch is used */
 288 static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
 289 {
 290         writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
 291 }
 292
 293 /* Send command and address cycles */
 294 static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd,
 295                                 unsigned int ctrl)
 296 {
 297         struct nand_chip *chip = mtd_to_nand(mtd);
 298         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 299
 300         if (cmd == NAND_CMD_NONE)
 301                 return;
 302
 303         if (ctrl & NAND_CLE) {
 304                 writeb(cmd, fmc2->cmd_base[fmc2->cs_sel]);
 305                 return;
 306         }
 307
 308         writeb(cmd, fmc2->addr_base[fmc2->cs_sel]);
 309 }
 310
 311 /*
 312  * Enable ECC logic and reset syndrome/parity bits previously calculated
 313  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 314  */
 315 static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode)
 316 {
 317         struct nand_chip *chip = mtd_to_nand(mtd);
 318         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 319
 320         stm32_fmc2_set_ecc(fmc2, false);
 321
 322         if (chip->ecc.strength != FMC2_ECC_HAM) {
 323                 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 324
 325                 if (mode == NAND_ECC_WRITE)
 326                         pcr |= FMC2_PCR_WEN;
 327                 else
 328                         pcr &= ~FMC2_PCR_WEN;
 329                 writel(pcr, fmc2->io_base + FMC2_PCR);
 330
 331                 stm32_fmc2_clear_bch_irq(fmc2);
 332         }
 333
 334         stm32_fmc2_set_ecc(fmc2, true);
 335 }
 336
 337 /*
 338  * ECC Hamming calculation
 339  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 340  * max of 1-bit)
 341  */
 342 static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data,
 343                                     u8 *ecc)
 344 {
 345         struct nand_chip *chip = mtd_to_nand(mtd);
 346         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 347         u32 heccr, sr;
 348         int ret;
 349
 350         ret = readl_poll_timeout(fmc2->io_base + FMC2_SR, sr,
 351                                  sr & FMC2_SR_NWRF, 10000);
 352         if (ret < 0) {
 353                 pr_err("Ham timeout\n");
 354                 return ret;
 355         }
 356
 357         heccr = readl(fmc2->io_base + FMC2_HECCR);
 358
 359         ecc[0] = heccr;
 360         ecc[1] = heccr >> 8;
 361         ecc[2] = heccr >> 16;
 362
 363         /* Disable ecc */
 364         stm32_fmc2_set_ecc(fmc2, false);
 365
 366         return 0;
 367 }
 368
 369 static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat,
 370                                   u8 *read_ecc, u8 *calc_ecc)
 371 {
 372         u8 bit_position = 0, b0, b1, b2;
 373         u32 byte_addr = 0, b;
 374         u32 i, shifting = 1;
 375
 376         /* Indicate which bit and byte is faulty (if any) */
 377         b0 = read_ecc[0] ^ calc_ecc[0];
 378         b1 = read_ecc[1] ^ calc_ecc[1];
 379         b2 = read_ecc[2] ^ calc_ecc[2];
 380         b = b0 | (b1 << 8) | (b2 << 16);
 381
 382         /* No errors */
 383         if (likely(!b))
 384                 return 0;
 385
 386         /* Calculate bit position */
 387         for (i = 0; i < 3; i++) {
 388                 switch (b % 4) {
 389                 case 2:
 390                         bit_position += shifting;
 391                 case 1:
 392                         break;
 393                 default:
 394                         return -EBADMSG;
 395                 }
 396                 shifting <<= 1;
 397                 b >>= 2;
 398         }
 399
 400         /* Calculate byte position */
 401         shifting = 1;
 402         for (i = 0; i < 9; i++) {
 403                 switch (b % 4) {
 404                 case 2:
 405                         byte_addr += shifting;
 406                 case 1:
 407                         break;
 408                 default:
 409                         return -EBADMSG;
 410                 }
 411                 shifting <<= 1;
 412                 b >>= 2;
 413         }
 414
 415         /* Flip the bit */
 416         dat[byte_addr] ^= (1 << bit_position);
 417
 418         return 1;
 419 }
 420
 421 /*
 422  * ECC BCH calculation and correction
 423  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 424  * max of 4-bit/8-bit)
 425  */
 426
 427 static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
 428                                     u8 *ecc)
 429 {
 430         struct nand_chip *chip = mtd_to_nand(mtd);
 431         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 432         u32 bchpbr, bchisr;
 433         int ret;
 434
 435         /* Wait until the BCH code is ready */
 436         ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
 437                                  bchisr & FMC2_BCHISR_EPBRF, 10000);
 438         if (ret < 0) {
 439                 pr_err("Bch timeout\n");
 440                 return ret;
 441         }
 442
 443         /* Read parity bits */
 444         bchpbr = readl(fmc2->io_base + FMC2_BCHPBR1);
 445         ecc[0] = bchpbr;
 446         ecc[1] = bchpbr >> 8;
 447         ecc[2] = bchpbr >> 16;
 448         ecc[3] = bchpbr >> 24;
 449
 450         bchpbr = readl(fmc2->io_base + FMC2_BCHPBR2);
 451         ecc[4] = bchpbr;
 452         ecc[5] = bchpbr >> 8;
 453         ecc[6] = bchpbr >> 16;
 454
 455         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 456                 ecc[7] = bchpbr >> 24;
 457
 458                 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR3);
 459                 ecc[8] = bchpbr;
 460                 ecc[9] = bchpbr >> 8;
 461                 ecc[10] = bchpbr >> 16;
 462                 ecc[11] = bchpbr >> 24;
 463
 464                 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR4);
 465                 ecc[12] = bchpbr;
 466         }
 467
 468         /* Disable ecc */
 469         stm32_fmc2_set_ecc(fmc2, false);
 470
 471         return 0;
 472 }
 473
 474 /* BCH algorithm correction */
 475 static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
 476                                   u8 *read_ecc, u8 *calc_ecc)
 477 {
 478         struct nand_chip *chip = mtd_to_nand(mtd);
 479         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 480         u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
 481         u16 pos[8];
 482         int i, ret, den, eccsize = chip->ecc.size;
 483         unsigned int nb_errs = 0;
 484
 485         /* Wait until the decoding error is ready */
 486         ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
 487                                  bchisr & FMC2_BCHISR_DERF, 10000);
 488         if (ret < 0) {
 489                 pr_err("Bch timeout\n");
 490                 return ret;
 491         }
 492
 493         bchdsr0 = readl(fmc2->io_base + FMC2_BCHDSR0);
 494         bchdsr1 = readl(fmc2->io_base + FMC2_BCHDSR1);
 495         bchdsr2 = readl(fmc2->io_base + FMC2_BCHDSR2);
 496         bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3);
 497         bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4);
 498
 499         /* Disable ECC */
 500         stm32_fmc2_set_ecc(fmc2, false);
 501
 502         /* No errors found */
 503         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 504                 return 0;
 505
 506         /* Too many errors detected */
 507         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 508                 return -EBADMSG;
 509
 510         pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
 511         pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
 512         pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
 513         pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
 514         pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
 515         pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
 516         pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
 517         pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
 518
 519         den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
 520         for (i = 0; i < den; i++) {
 521                 if (pos[i] < eccsize * 8) {
 522                         __change_bit(pos[i], (unsigned long *)dat);
 523                         nb_errs++;
 524                 }
 525         }
 526
 527         return nb_errs;
 528 }
 529
 530 static int stm32_fmc2_read_page(struct mtd_info *mtd,
 531                                 struct nand_chip *chip, u8 *buf,
 532                                 int oob_required, int page)
 533 {
 534         int i, s, stat, eccsize = chip->ecc.size;
 535         int eccbytes = chip->ecc.bytes;
 536         int eccsteps = chip->ecc.steps;
 537         int eccstrength = chip->ecc.strength;
 538         u8 *p = buf;
 539         u8 *ecc_calc = chip->buffers->ecccalc;
 540         u8 *ecc_code = chip->buffers->ecccode;
 541         unsigned int max_bitflips = 0;
 542
 543         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 544              s++, i += eccbytes, p += eccsize) {
 545                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 546
 547                 /* Read the nand page sector (512 bytes) */
 548                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
 549                 chip->read_buf(mtd, p, eccsize);
 550
 551                 /* Read the corresponding ECC bytes */
 552                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
 553                 chip->read_buf(mtd, ecc_code, eccbytes);
 554
 555                 /* Correct the data */
 556                 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
 557                 if (stat == -EBADMSG)
 558                         /* Check for empty pages with bitflips */
 559                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 560                                                            ecc_code, eccbytes,
 561                                                            NULL, 0,
 562                                                            eccstrength);
 563
 564                 if (stat < 0) {
 565                         mtd->ecc_stats.failed++;
 566                 } else {
 567                         mtd->ecc_stats.corrected += stat;
 568                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 569                 }
 570         }
 571
 572         /* Read oob */
 573         if (oob_required) {
 574                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 575                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 576         }
 577
 578         return max_bitflips;
 579 }
 580
 581 /* Controller initialization */
 582 static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
 583 {
 584         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 585         u32 bcr1 = readl(fmc2->io_base + FMC2_BCR1);
 586
 587         /* Set CS used to undefined */
 588         fmc2->cs_sel = -1;
 589
 590         /* Enable wait feature and nand flash memory bank */
 591         pcr |= FMC2_PCR_PWAITEN;
 592         pcr |= FMC2_PCR_PBKEN;
 593
 594         /* Set buswidth to 8 bits mode for identification */
 595         pcr &= ~FMC2_PCR_PWID_MASK;
 596
 597         /* ECC logic is disabled */
 598         pcr &= ~FMC2_PCR_ECCEN;
 599
 600         /* Default mode */
 601         pcr &= ~FMC2_PCR_ECCALG;
 602         pcr &= ~FMC2_PCR_BCHECC;
 603         pcr &= ~FMC2_PCR_WEN;
 604
 605         /* Set default ECC sector size */
 606         pcr &= ~FMC2_PCR_ECCSS_MASK;
 607         pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
 608
 609         /* Set default tclr/tar timings */
 610         pcr &= ~FMC2_PCR_TCLR_MASK;
 611         pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
 612         pcr &= ~FMC2_PCR_TAR_MASK;
 613         pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
 614
 615         /* Enable FMC2 controller */
 616         bcr1 |= FMC2_BCR1_FMC2EN;
 617
 618         writel(bcr1, fmc2->io_base + FMC2_BCR1);
 619         writel(pcr, fmc2->io_base + FMC2_PCR);
 620         writel(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
 621         writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
 622 }
 623
 624 /* Controller timings */
 625 static void stm32_fmc2_calc_timings(struct nand_chip *chip,
 626                                     const struct nand_sdr_timings *sdrt)
 627 {
 628         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 629         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 630         struct stm32_fmc2_timings *tims = &nand->timings;
 631         unsigned long hclk = clk_get_rate(&fmc2->clk);
 632         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 633         unsigned long timing, tar, tclr, thiz, twait;
 634         unsigned long tset_mem, tset_att, thold_mem, thold_att;
 635
 636         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
 637         timing = DIV_ROUND_UP(tar, hclkp) - 1;
 638         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 639
 640         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
 641         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
 642         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 643
 644         tims->thiz = FMC2_THIZ;
 645         thiz = (tims->thiz + 1) * hclkp;
 646
 647         /*
 648          * tWAIT > tRP
 649          * tWAIT > tWP
 650          * tWAIT > tREA + tIO
 651          */
 652         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
 653         twait = max_t(unsigned long, twait, sdrt->tWP_min);
 654         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
 655         timing = DIV_ROUND_UP(twait, hclkp);
 656         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 657
 658         /*
 659          * tSETUP_MEM > tCS - tWAIT
 660          * tSETUP_MEM > tALS - tWAIT
 661          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
 662          */
 663         tset_mem = hclkp;
 664         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
 665                 tset_mem = sdrt->tCS_min - twait;
 666         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
 667                 tset_mem = sdrt->tALS_min - twait;
 668         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 669             (tset_mem < sdrt->tDS_min - (twait - thiz)))
 670                 tset_mem = sdrt->tDS_min - (twait - thiz);
 671         timing = DIV_ROUND_UP(tset_mem, hclkp);
 672         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 673
 674         /*
 675          * tHOLD_MEM > tCH
 676          * tHOLD_MEM > tREH - tSETUP_MEM
 677          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
 678          */
 679         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
 680         if (sdrt->tREH_min > tset_mem &&
 681             (thold_mem < sdrt->tREH_min - tset_mem))
 682                 thold_mem = sdrt->tREH_min - tset_mem;
 683         if ((sdrt->tRC_min > tset_mem + twait) &&
 684             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
 685                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
 686         if ((sdrt->tWC_min > tset_mem + twait) &&
 687             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
 688                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
 689         timing = DIV_ROUND_UP(thold_mem, hclkp);
 690         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 691
 692         /*
 693          * tSETUP_ATT > tCS - tWAIT
 694          * tSETUP_ATT > tCLS - tWAIT
 695          * tSETUP_ATT > tALS - tWAIT
 696          * tSETUP_ATT > tRHW - tHOLD_MEM
 697          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
 698          */
 699         tset_att = hclkp;
 700         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
 701                 tset_att = sdrt->tCS_min - twait;
 702         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
 703                 tset_att = sdrt->tCLS_min - twait;
 704         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
 705                 tset_att = sdrt->tALS_min - twait;
 706         if (sdrt->tRHW_min > thold_mem &&
 707             (tset_att < sdrt->tRHW_min - thold_mem))
 708                 tset_att = sdrt->tRHW_min - thold_mem;
 709         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 710             (tset_att < sdrt->tDS_min - (twait - thiz)))
 711                 tset_att = sdrt->tDS_min - (twait - thiz);
 712         timing = DIV_ROUND_UP(tset_att, hclkp);
 713         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 714
 715         /*
 716          * tHOLD_ATT > tALH
 717          * tHOLD_ATT > tCH
 718          * tHOLD_ATT > tCLH
 719          * tHOLD_ATT > tCOH
 720          * tHOLD_ATT > tDH
 721          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
 722          * tHOLD_ATT > tADL - tSETUP_MEM
 723          * tHOLD_ATT > tWH - tSETUP_MEM
 724          * tHOLD_ATT > tWHR - tSETUP_MEM
 725          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
 726          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
 727          */
 728         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
 729         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
 730         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
 731         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
 732         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
 733         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
 734             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
 735                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
 736         if (sdrt->tADL_min > tset_mem &&
 737             (thold_att < sdrt->tADL_min - tset_mem))
 738                 thold_att = sdrt->tADL_min - tset_mem;
 739         if (sdrt->tWH_min > tset_mem &&
 740             (thold_att < sdrt->tWH_min - tset_mem))
 741                 thold_att = sdrt->tWH_min - tset_mem;
 742         if (sdrt->tWHR_min > tset_mem &&
 743             (thold_att < sdrt->tWHR_min - tset_mem))
 744                 thold_att = sdrt->tWHR_min - tset_mem;
 745         if ((sdrt->tRC_min > tset_att + twait) &&
 746             (thold_att < sdrt->tRC_min - (tset_att + twait)))
 747                 thold_att = sdrt->tRC_min - (tset_att + twait);
 748         if ((sdrt->tWC_min > tset_att + twait) &&
 749             (thold_att < sdrt->tWC_min - (tset_att + twait)))
 750                 thold_att = sdrt->tWC_min - (tset_att + twait);
 751         timing = DIV_ROUND_UP(thold_att, hclkp);
 752         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 753 }
 754
 755 static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
 756                                       const struct nand_data_interface *conf)
 757 {
 758         struct nand_chip *chip = mtd_to_nand(mtd);
 759         const struct nand_sdr_timings *sdrt;
 760
 761         sdrt = nand_get_sdr_timings(conf);
 762         if (IS_ERR(sdrt))
 763                 return PTR_ERR(sdrt);
 764
 765         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
 766                 return 0;
 767
 768         stm32_fmc2_calc_timings(chip, sdrt);
 769
 770         /* Apply timings */
 771         stm32_fmc2_timings_init(chip);
 772
 773         return 0;
 774 }
 775
 776 /* NAND callbacks setup */
 777 static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
 778 {
 779         chip->ecc.hwctl = stm32_fmc2_hwctl;
 780
 781         /*
 782          * Specific callbacks to read/write a page depending on
 783          * the algo used (Hamming, BCH).
 784          */
 785         if (chip->ecc.strength == FMC2_ECC_HAM) {
 786                 /* Hamming is used */
 787                 chip->ecc.calculate = stm32_fmc2_ham_calculate;
 788                 chip->ecc.correct = stm32_fmc2_ham_correct;
 789                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
 790                 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
 791                 return;
 792         }
 793
 794         /* BCH is used */
 795         chip->ecc.read_page = stm32_fmc2_read_page;
 796         chip->ecc.calculate = stm32_fmc2_bch_calculate;
 797         chip->ecc.correct = stm32_fmc2_bch_correct;
 798
 799         if (chip->ecc.strength == FMC2_ECC_BCH8)
 800                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
 801         else
 802                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
 803 }
 804
 805 /* FMC2 caps */
 806 static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
 807 {
 808         /* Hamming */
 809         if (strength == FMC2_ECC_HAM)
 810                 return 4;
 811
 812         /* BCH8 */
 813         if (strength == FMC2_ECC_BCH8)
 814                 return 14;
 815
 816         /* BCH4 */
 817         return 8;
 818 }
 819
 820 NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
 821                      FMC2_ECC_STEP_SIZE,
 822                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
 823
 824 /* FMC2 probe */
 825 static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
 826                                   ofnode node)
 827 {
 828         struct stm32_fmc2_nand *nand = &fmc2->nand;
 829         u32 cs[FMC2_MAX_CE];
 830         int ret, i;
 831
 832         if (!ofnode_get_property(node, "reg", &nand->ncs))
 833                 return -EINVAL;
 834
 835         nand->ncs /= sizeof(u32);
 836         if (!nand->ncs) {
 837                 pr_err("Invalid reg property size\n");
 838                 return -EINVAL;
 839         }
 840
 841         ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
 842         if (ret < 0) {
 843                 pr_err("Could not retrieve reg property\n");
 844                 return -EINVAL;
 845         }
 846
 847         for (i = 0; i < nand->ncs; i++) {
 848                 if (cs[i] > FMC2_MAX_CE) {
 849                         pr_err("Invalid reg value: %d\n",
 850                                nand->cs_used[i]);
 851                         return -EINVAL;
 852                 }
 853
 854                 if (fmc2->cs_assigned & BIT(cs[i])) {
 855                         pr_err("Cs already assigned: %d\n",
 856                                nand->cs_used[i]);
 857                         return -EINVAL;
 858                 }
 859
 860                 fmc2->cs_assigned |= BIT(cs[i]);
 861                 nand->cs_used[i] = cs[i];
 862         }
 863
 864         nand->chip.flash_node = ofnode_to_offset(node);
 865
 866         return 0;
 867 }
 868
 869 static int stm32_fmc2_parse_dt(struct udevice *dev,
 870                                struct stm32_fmc2_nfc *fmc2)
 871 {
 872         ofnode child;
 873         int ret, nchips = 0;
 874
 875         dev_for_each_subnode(child, dev)
 876                 nchips++;
 877
 878         if (!nchips) {
 879                 pr_err("NAND chip not defined\n");
 880                 return -EINVAL;
 881         }
 882
 883         if (nchips > 1) {
 884                 pr_err("Too many NAND chips defined\n");
 885                 return -EINVAL;
 886         }
 887
 888         dev_for_each_subnode(child, dev) {
 889                 ret = stm32_fmc2_parse_child(fmc2, child);
 890                 if (ret)
 891                         return ret;
 892         }
 893
 894         return 0;
 895 }
 896
 897 static int stm32_fmc2_probe(struct udevice *dev)
 898 {
 899         struct stm32_fmc2_nfc *fmc2 = dev_get_priv(dev);
 900         struct stm32_fmc2_nand *nand = &fmc2->nand;
 901         struct nand_chip *chip = &nand->chip;
 902         struct mtd_info *mtd = &chip->mtd;
 903         struct nand_ecclayout *ecclayout;
 904         struct resource resource;
 905         struct reset_ctl reset;
 906         int oob_index, chip_cs, mem_region, ret;
 907         unsigned int i;
 908
 909         spin_lock_init(&fmc2->controller.lock);
 910         init_waitqueue_head(&fmc2->controller.wq);
 911
 912         ret = stm32_fmc2_parse_dt(dev, fmc2);
 913         if (ret)
 914                 return ret;
 915
 916         /* Get resources */
 917         ret = dev_read_resource(dev, 0, &resource);
 918         if (ret) {
 919                 pr_err("Resource io_base not found");
 920                 return ret;
 921         }
 922         fmc2->io_base = (void __iomem *)resource.start;
 923
 924         for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
 925              chip_cs++, mem_region += 3) {
 926                 if (!(fmc2->cs_assigned & BIT(chip_cs)))
 927                         continue;
 928
 929                 ret = dev_read_resource(dev, mem_region, &resource);
 930                 if (ret) {
 931                         pr_err("Resource data_base not found for cs%d",
 932                                chip_cs);
 933                         return ret;
 934                 }
 935                 fmc2->data_base[chip_cs] = (void __iomem *)resource.start;
 936
 937                 ret = dev_read_resource(dev, mem_region + 1, &resource);
 938                 if (ret) {
 939                         pr_err("Resource cmd_base not found for cs%d",
 940                                chip_cs);
 941                         return ret;
 942                 }
 943                 fmc2->cmd_base[chip_cs] = (void __iomem *)resource.start;
 944
 945                 ret = dev_read_resource(dev, mem_region + 2, &resource);
 946                 if (ret) {
 947                         pr_err("Resource addr_base not found for cs%d",
 948                                chip_cs);
 949                         return ret;
 950                 }
 951                 fmc2->addr_base[chip_cs] = (void __iomem *)resource.start;
 952         }
 953
 954         /* Enable the clock */
 955         ret = clk_get_by_index(dev, 0, &fmc2->clk);
 956         if (ret)
 957                 return ret;
 958
 959         ret = clk_enable(&fmc2->clk);
 960         if (ret)
 961                 return ret;
 962
 963         /* Reset */
 964         ret = reset_get_by_index(dev, 0, &reset);
 965         if (!ret) {
 966                 reset_assert(&reset);
 967                 udelay(2);
 968                 reset_deassert(&reset);
 969         }
 970
 971         /* FMC2 init routine */
 972         stm32_fmc2_init(fmc2);
 973
 974         chip->controller = &fmc2->base;
 975         chip->select_chip = stm32_fmc2_select_chip;
 976         chip->setup_data_interface = stm32_fmc2_setup_interface;
 977         chip->cmd_ctrl = stm32_fmc2_cmd_ctrl;
 978         chip->chip_delay = FMC2_RB_DELAY_US;
 979         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 980                          NAND_USE_BOUNCE_BUFFER;
 981
 982         /* Default ECC settings */
 983         chip->ecc.mode = NAND_ECC_HW;
 984         chip->ecc.size = FMC2_ECC_STEP_SIZE;
 985         chip->ecc.strength = FMC2_ECC_BCH8;
 986
 987         /* Scan to find existence of the device */
 988         ret = nand_scan_ident(mtd, nand->ncs, NULL);
 989         if (ret)
 990                 return ret;
 991
 992         /*
 993          * Only NAND_ECC_HW mode is actually supported
 994          * Hamming => ecc.strength = 1
 995          * BCH4 => ecc.strength = 4
 996          * BCH8 => ecc.strength = 8
 997          * ECC sector size = 512
 998          */
 999         if (chip->ecc.mode != NAND_ECC_HW) {
1000                 pr_err("Nand_ecc_mode is not well defined in the DT\n");
1001                 return -EINVAL;
1002         }
1003
1004         ret = nand_check_ecc_caps(chip, &stm32_fmc2_ecc_caps,
1005                                   mtd->oobsize - FMC2_BBM_LEN);
1006         if (ret) {
1007                 pr_err("No valid ECC settings set\n");
1008                 return ret;
1009         }
1010
1011         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1012                 chip->bbt_options |= NAND_BBT_NO_OOB;
1013
1014         /* NAND callbacks setup */
1015         stm32_fmc2_nand_callbacks_setup(chip);
1016
1017         /* Define ECC layout */
1018         ecclayout = &fmc2->ecclayout;
1019         ecclayout->eccbytes = chip->ecc.bytes *
1020                               (mtd->writesize / chip->ecc.size);
1021         oob_index = FMC2_BBM_LEN;
1022         for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1023                 ecclayout->eccpos[i] = oob_index;
1024         ecclayout->oobfree->offset = oob_index;
1025         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1026         chip->ecc.layout = ecclayout;
1027
1028         /* Configure bus width to 16-bit */
1029         if (chip->options & NAND_BUSWIDTH_16)
1030                 stm32_fmc2_set_buswidth_16(fmc2, true);
1031
1032         /* Scan the device to fill MTD data-structures */
1033         ret = nand_scan_tail(mtd);
1034         if (ret)
1035                 return ret;
1036
1037         return nand_register(0, mtd);
1038 }
1039
1040 static const struct udevice_id stm32_fmc2_match[] = {
1041         { .compatible = "st,stm32mp15-fmc2" },
1042         { /* Sentinel */ }
1043 };
1044
1045 U_BOOT_DRIVER(stm32_fmc2_nand) = {
1046         .name = "stm32_fmc2_nand",
1047         .id = UCLASS_MTD,
1048         .of_match = stm32_fmc2_match,
1049         .probe = stm32_fmc2_probe,
1050         .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
1051 };
1052
1053 void board_nand_init(void)
1054 {
1055         struct udevice *dev;
1056         int ret;
1057
1058         ret = uclass_get_device_by_driver(UCLASS_MTD,
1059                                           DM_GET_DRIVER(stm32_fmc2_nand),
1060                                           &dev);
1061         if (ret && ret != -ENODEV)
1062                 pr_err("Failed to initialize STM32 FMC2 NAND controller. (error %d)\n",
1063                        ret);
1064 }