drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2019
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <nand.h>
  12 #include <reset.h>
  13 #include <linux/err.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/ioport.h>
  16
  17 /* Bad block marker length */
  18 #define FMC2_BBM_LEN                    2
  19
  20 /* ECC step size */
  21 #define FMC2_ECC_STEP_SIZE              512
  22
  23 /* Command delay */
  24 #define FMC2_RB_DELAY_US                30
  25
  26 /* Max chip enable */
  27 #define FMC2_MAX_CE                     2
  28
  29 /* Timings */
  30 #define FMC2_THIZ                       1
  31 #define FMC2_TIO                        8000
  32 #define FMC2_TSYNC                      3000
  33 #define FMC2_PCR_TIMING_MASK            0xf
  34 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  35
  36 /* FMC2 Controller Registers */
  37 #define FMC2_BCR1                       0x0
  38 #define FMC2_PCR                        0x80
  39 #define FMC2_SR                         0x84
  40 #define FMC2_PMEM                       0x88
  41 #define FMC2_PATT                       0x8c
  42 #define FMC2_HECCR                      0x94
  43 #define FMC2_BCHISR                     0x254
  44 #define FMC2_BCHICR                     0x258
  45 #define FMC2_BCHPBR1                    0x260
  46 #define FMC2_BCHPBR2                    0x264
  47 #define FMC2_BCHPBR3                    0x268
  48 #define FMC2_BCHPBR4                    0x26c
  49 #define FMC2_BCHDSR0                    0x27c
  50 #define FMC2_BCHDSR1                    0x280
  51 #define FMC2_BCHDSR2                    0x284
  52 #define FMC2_BCHDSR3                    0x288
  53 #define FMC2_BCHDSR4                    0x28c
  54
  55 /* Register: FMC2_BCR1 */
  56 #define FMC2_BCR1_FMC2EN                BIT(31)
  57
  58 /* Register: FMC2_PCR */
  59 #define FMC2_PCR_PWAITEN                BIT(1)
  60 #define FMC2_PCR_PBKEN                  BIT(2)
  61 #define FMC2_PCR_PWID_MASK              GENMASK(5, 4)
  62 #define FMC2_PCR_PWID(x)                (((x) & 0x3) << 4)
  63 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  64 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  65 #define FMC2_PCR_ECCEN                  BIT(6)
  66 #define FMC2_PCR_ECCALG                 BIT(8)
  67 #define FMC2_PCR_TCLR_MASK              GENMASK(12, 9)
  68 #define FMC2_PCR_TCLR(x)                (((x) & 0xf) << 9)
  69 #define FMC2_PCR_TCLR_DEFAULT           0xf
  70 #define FMC2_PCR_TAR_MASK               GENMASK(16, 13)
  71 #define FMC2_PCR_TAR(x)                 (((x) & 0xf) << 13)
  72 #define FMC2_PCR_TAR_DEFAULT            0xf
  73 #define FMC2_PCR_ECCSS_MASK             GENMASK(19, 17)
  74 #define FMC2_PCR_ECCSS(x)               (((x) & 0x7) << 17)
  75 #define FMC2_PCR_ECCSS_512              1
  76 #define FMC2_PCR_ECCSS_2048             3
  77 #define FMC2_PCR_BCHECC                 BIT(24)
  78 #define FMC2_PCR_WEN                    BIT(25)
  79
  80 /* Register: FMC2_SR */
  81 #define FMC2_SR_NWRF                    BIT(6)
  82
  83 /* Register: FMC2_PMEM */
  84 #define FMC2_PMEM_MEMSET(x)             (((x) & 0xff) << 0)
  85 #define FMC2_PMEM_MEMWAIT(x)            (((x) & 0xff) << 8)
  86 #define FMC2_PMEM_MEMHOLD(x)            (((x) & 0xff) << 16)
  87 #define FMC2_PMEM_MEMHIZ(x)             (((x) & 0xff) << 24)
  88 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
  89
  90 /* Register: FMC2_PATT */
  91 #define FMC2_PATT_ATTSET(x)             (((x) & 0xff) << 0)
  92 #define FMC2_PATT_ATTWAIT(x)            (((x) & 0xff) << 8)
  93 #define FMC2_PATT_ATTHOLD(x)            (((x) & 0xff) << 16)
  94 #define FMC2_PATT_ATTHIZ(x)             (((x) & 0xff) << 24)
  95 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
  96
  97 /* Register: FMC2_BCHISR */
  98 #define FMC2_BCHISR_DERF                BIT(1)
  99 #define FMC2_BCHISR_EPBRF               BIT(4)
 100
 101 /* Register: FMC2_BCHICR */
 102 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 103
 104 /* Register: FMC2_BCHDSR0 */
 105 #define FMC2_BCHDSR0_DUE                BIT(0)
 106 #define FMC2_BCHDSR0_DEF                BIT(1)
 107 #define FMC2_BCHDSR0_DEN_MASK           GENMASK(7, 4)
 108 #define FMC2_BCHDSR0_DEN_SHIFT          4
 109
 110 /* Register: FMC2_BCHDSR1 */
 111 #define FMC2_BCHDSR1_EBP1_MASK          GENMASK(12, 0)
 112 #define FMC2_BCHDSR1_EBP2_MASK          GENMASK(28, 16)
 113 #define FMC2_BCHDSR1_EBP2_SHIFT         16
 114
 115 /* Register: FMC2_BCHDSR2 */
 116 #define FMC2_BCHDSR2_EBP3_MASK          GENMASK(12, 0)
 117 #define FMC2_BCHDSR2_EBP4_MASK          GENMASK(28, 16)
 118 #define FMC2_BCHDSR2_EBP4_SHIFT         16
 119
 120 /* Register: FMC2_BCHDSR3 */
 121 #define FMC2_BCHDSR3_EBP5_MASK          GENMASK(12, 0)
 122 #define FMC2_BCHDSR3_EBP6_MASK          GENMASK(28, 16)
 123 #define FMC2_BCHDSR3_EBP6_SHIFT         16
 124
 125 /* Register: FMC2_BCHDSR4 */
 126 #define FMC2_BCHDSR4_EBP7_MASK          GENMASK(12, 0)
 127 #define FMC2_BCHDSR4_EBP8_MASK          GENMASK(28, 16)
 128 #define FMC2_BCHDSR4_EBP8_SHIFT         16
 129
 130 #define FMC2_NSEC_PER_SEC               1000000000L
 131
 132 enum stm32_fmc2_ecc {
 133         FMC2_ECC_HAM = 1,
 134         FMC2_ECC_BCH4 = 4,
 135         FMC2_ECC_BCH8 = 8
 136 };
 137
 138 struct stm32_fmc2_timings {
 139         u8 tclr;
 140         u8 tar;
 141         u8 thiz;
 142         u8 twait;
 143         u8 thold_mem;
 144         u8 tset_mem;
 145         u8 thold_att;
 146         u8 tset_att;
 147 };
 148
 149 struct stm32_fmc2_nand {
 150         struct nand_chip chip;
 151         struct stm32_fmc2_timings timings;
 152         int ncs;
 153         int cs_used[FMC2_MAX_CE];
 154 };
 155
 156 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 157 {
 158         return container_of(chip, struct stm32_fmc2_nand, chip);
 159 }
 160
 161 struct stm32_fmc2_nfc {
 162         struct nand_hw_control base;
 163         struct stm32_fmc2_nand nand;
 164         struct nand_ecclayout ecclayout;
 165         void __iomem *io_base;
 166         void __iomem *data_base[FMC2_MAX_CE];
 167         void __iomem *cmd_base[FMC2_MAX_CE];
 168         void __iomem *addr_base[FMC2_MAX_CE];
 169         struct clk clk;
 170
 171         u8 cs_assigned;
 172         int cs_sel;
 173 };
 174
 175 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
 176 {
 177         return container_of(base, struct stm32_fmc2_nfc, base);
 178 }
 179
 180 /* Timings configuration */
 181 static void stm32_fmc2_timings_init(struct nand_chip *chip)
 182 {
 183         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 184         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 185         struct stm32_fmc2_timings *timings = &nand->timings;
 186         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 187         u32 pmem, patt;
 188
 189         /* Set tclr/tar timings */
 190         pcr &= ~FMC2_PCR_TCLR_MASK;
 191         pcr |= FMC2_PCR_TCLR(timings->tclr);
 192         pcr &= ~FMC2_PCR_TAR_MASK;
 193         pcr |= FMC2_PCR_TAR(timings->tar);
 194
 195         /* Set tset/twait/thold/thiz timings in common bank */
 196         pmem = FMC2_PMEM_MEMSET(timings->tset_mem);
 197         pmem |= FMC2_PMEM_MEMWAIT(timings->twait);
 198         pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem);
 199         pmem |= FMC2_PMEM_MEMHIZ(timings->thiz);
 200
 201         /* Set tset/twait/thold/thiz timings in attribut bank */
 202         patt = FMC2_PATT_ATTSET(timings->tset_att);
 203         patt |= FMC2_PATT_ATTWAIT(timings->twait);
 204         patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
 205         patt |= FMC2_PATT_ATTHIZ(timings->thiz);
 206
 207         writel(pcr, fmc2->io_base + FMC2_PCR);
 208         writel(pmem, fmc2->io_base + FMC2_PMEM);
 209         writel(patt, fmc2->io_base + FMC2_PATT);
 210 }
 211
 212 /* Controller configuration */
 213 static void stm32_fmc2_setup(struct nand_chip *chip)
 214 {
 215         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 216         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 217
 218         /* Configure ECC algorithm (default configuration is Hamming) */
 219         pcr &= ~FMC2_PCR_ECCALG;
 220         pcr &= ~FMC2_PCR_BCHECC;
 221         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 222                 pcr |= FMC2_PCR_ECCALG;
 223                 pcr |= FMC2_PCR_BCHECC;
 224         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 225                 pcr |= FMC2_PCR_ECCALG;
 226         }
 227
 228         /* Set buswidth */
 229         pcr &= ~FMC2_PCR_PWID_MASK;
 230         if (chip->options & NAND_BUSWIDTH_16)
 231                 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
 232
 233         /* Set ECC sector size */
 234         pcr &= ~FMC2_PCR_ECCSS_MASK;
 235         pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
 236
 237         writel(pcr, fmc2->io_base + FMC2_PCR);
 238 }
 239
 240 /* Select target */
 241 static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr)
 242 {
 243         struct nand_chip *chip = mtd_to_nand(mtd);
 244         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 245         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 246
 247         if (chipnr < 0 || chipnr >= nand->ncs)
 248                 return;
 249
 250         if (nand->cs_used[chipnr] == fmc2->cs_sel)
 251                 return;
 252
 253         fmc2->cs_sel = nand->cs_used[chipnr];
 254         chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel];
 255         chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel];
 256
 257         /* FMC2 setup routine */
 258         stm32_fmc2_setup(chip);
 259
 260         /* Apply timings */
 261         stm32_fmc2_timings_init(chip);
 262 }
 263
 264 /* Set bus width to 16-bit or 8-bit */
 265 static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
 266 {
 267         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 268
 269         pcr &= ~FMC2_PCR_PWID_MASK;
 270         if (set)
 271                 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
 272         writel(pcr, fmc2->io_base + FMC2_PCR);
 273 }
 274
 275 /* Enable/disable ECC */
 276 static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
 277 {
 278         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 279
 280         pcr &= ~FMC2_PCR_ECCEN;
 281         if (enable)
 282                 pcr |= FMC2_PCR_ECCEN;
 283         writel(pcr, fmc2->io_base + FMC2_PCR);
 284 }
 285
 286 /* Clear irq sources in case of bch is used */
 287 static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
 288 {
 289         writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
 290 }
 291
 292 /* Send command and address cycles */
 293 static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd,
 294                                 unsigned int ctrl)
 295 {
 296         struct nand_chip *chip = mtd_to_nand(mtd);
 297         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 298
 299         if (cmd == NAND_CMD_NONE)
 300                 return;
 301
 302         if (ctrl & NAND_CLE) {
 303                 writeb(cmd, fmc2->cmd_base[fmc2->cs_sel]);
 304                 return;
 305         }
 306
 307         writeb(cmd, fmc2->addr_base[fmc2->cs_sel]);
 308 }
 309
 310 /*
 311  * Enable ECC logic and reset syndrome/parity bits previously calculated
 312  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 313  */
 314 static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode)
 315 {
 316         struct nand_chip *chip = mtd_to_nand(mtd);
 317         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 318
 319         stm32_fmc2_set_ecc(fmc2, false);
 320
 321         if (chip->ecc.strength != FMC2_ECC_HAM) {
 322                 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 323
 324                 if (mode == NAND_ECC_WRITE)
 325                         pcr |= FMC2_PCR_WEN;
 326                 else
 327                         pcr &= ~FMC2_PCR_WEN;
 328                 writel(pcr, fmc2->io_base + FMC2_PCR);
 329
 330                 stm32_fmc2_clear_bch_irq(fmc2);
 331         }
 332
 333         stm32_fmc2_set_ecc(fmc2, true);
 334 }
 335
 336 /*
 337  * ECC Hamming calculation
 338  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 339  * max of 1-bit)
 340  */
 341 static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data,
 342                                     u8 *ecc)
 343 {
 344         struct nand_chip *chip = mtd_to_nand(mtd);
 345         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 346         u32 heccr, sr;
 347         int ret;
 348
 349         ret = readl_poll_timeout(fmc2->io_base + FMC2_SR, sr,
 350                                  sr & FMC2_SR_NWRF, 10000);
 351         if (ret < 0) {
 352                 pr_err("Ham timeout\n");
 353                 return ret;
 354         }
 355
 356         heccr = readl(fmc2->io_base + FMC2_HECCR);
 357
 358         ecc[0] = heccr;
 359         ecc[1] = heccr >> 8;
 360         ecc[2] = heccr >> 16;
 361
 362         /* Disable ecc */
 363         stm32_fmc2_set_ecc(fmc2, false);
 364
 365         return 0;
 366 }
 367
 368 static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat,
 369                                   u8 *read_ecc, u8 *calc_ecc)
 370 {
 371         u8 bit_position = 0, b0, b1, b2;
 372         u32 byte_addr = 0, b;
 373         u32 i, shifting = 1;
 374
 375         /* Indicate which bit and byte is faulty (if any) */
 376         b0 = read_ecc[0] ^ calc_ecc[0];
 377         b1 = read_ecc[1] ^ calc_ecc[1];
 378         b2 = read_ecc[2] ^ calc_ecc[2];
 379         b = b0 | (b1 << 8) | (b2 << 16);
 380
 381         /* No errors */
 382         if (likely(!b))
 383                 return 0;
 384
 385         /* Calculate bit position */
 386         for (i = 0; i < 3; i++) {
 387                 switch (b % 4) {
 388                 case 2:
 389                         bit_position += shifting;
 390                 case 1:
 391                         break;
 392                 default:
 393                         return -EBADMSG;
 394                 }
 395                 shifting <<= 1;
 396                 b >>= 2;
 397         }
 398
 399         /* Calculate byte position */
 400         shifting = 1;
 401         for (i = 0; i < 9; i++) {
 402                 switch (b % 4) {
 403                 case 2:
 404                         byte_addr += shifting;
 405                 case 1:
 406                         break;
 407                 default:
 408                         return -EBADMSG;
 409                 }
 410                 shifting <<= 1;
 411                 b >>= 2;
 412         }
 413
 414         /* Flip the bit */
 415         dat[byte_addr] ^= (1 << bit_position);
 416
 417         return 1;
 418 }
 419
 420 /*
 421  * ECC BCH calculation and correction
 422  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 423  * max of 4-bit/8-bit)
 424  */
 425
 426 static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
 427                                     u8 *ecc)
 428 {
 429         struct nand_chip *chip = mtd_to_nand(mtd);
 430         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 431         u32 bchpbr, bchisr;
 432         int ret;
 433
 434         /* Wait until the BCH code is ready */
 435         ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
 436                                  bchisr & FMC2_BCHISR_EPBRF, 10000);
 437         if (ret < 0) {
 438                 pr_err("Bch timeout\n");
 439                 return ret;
 440         }
 441
 442         /* Read parity bits */
 443         bchpbr = readl(fmc2->io_base + FMC2_BCHPBR1);
 444         ecc[0] = bchpbr;
 445         ecc[1] = bchpbr >> 8;
 446         ecc[2] = bchpbr >> 16;
 447         ecc[3] = bchpbr >> 24;
 448
 449         bchpbr = readl(fmc2->io_base + FMC2_BCHPBR2);
 450         ecc[4] = bchpbr;
 451         ecc[5] = bchpbr >> 8;
 452         ecc[6] = bchpbr >> 16;
 453
 454         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 455                 ecc[7] = bchpbr >> 24;
 456
 457                 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR3);
 458                 ecc[8] = bchpbr;
 459                 ecc[9] = bchpbr >> 8;
 460                 ecc[10] = bchpbr >> 16;
 461                 ecc[11] = bchpbr >> 24;
 462
 463                 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR4);
 464                 ecc[12] = bchpbr;
 465         }
 466
 467         /* Disable ecc */
 468         stm32_fmc2_set_ecc(fmc2, false);
 469
 470         return 0;
 471 }
 472
 473 /* BCH algorithm correction */
 474 static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
 475                                   u8 *read_ecc, u8 *calc_ecc)
 476 {
 477         struct nand_chip *chip = mtd_to_nand(mtd);
 478         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 479         u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
 480         u16 pos[8];
 481         int i, ret, den, eccsize = chip->ecc.size;
 482         unsigned int nb_errs = 0;
 483
 484         /* Wait until the decoding error is ready */
 485         ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
 486                                  bchisr & FMC2_BCHISR_DERF, 10000);
 487         if (ret < 0) {
 488                 pr_err("Bch timeout\n");
 489                 return ret;
 490         }
 491
 492         bchdsr0 = readl(fmc2->io_base + FMC2_BCHDSR0);
 493         bchdsr1 = readl(fmc2->io_base + FMC2_BCHDSR1);
 494         bchdsr2 = readl(fmc2->io_base + FMC2_BCHDSR2);
 495         bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3);
 496         bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4);
 497
 498         /* Disable ECC */
 499         stm32_fmc2_set_ecc(fmc2, false);
 500
 501         /* No errors found */
 502         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 503                 return 0;
 504
 505         /* Too many errors detected */
 506         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 507                 return -EBADMSG;
 508
 509         pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
 510         pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
 511         pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
 512         pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
 513         pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
 514         pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
 515         pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
 516         pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
 517
 518         den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
 519         for (i = 0; i < den; i++) {
 520                 if (pos[i] < eccsize * 8) {
 521                         __change_bit(pos[i], (unsigned long *)dat);
 522                         nb_errs++;
 523                 }
 524         }
 525
 526         return nb_errs;
 527 }
 528
 529 static int stm32_fmc2_read_page(struct mtd_info *mtd,
 530                                 struct nand_chip *chip, u8 *buf,
 531                                 int oob_required, int page)
 532 {
 533         int i, s, stat, eccsize = chip->ecc.size;
 534         int eccbytes = chip->ecc.bytes;
 535         int eccsteps = chip->ecc.steps;
 536         int eccstrength = chip->ecc.strength;
 537         u8 *p = buf;
 538         u8 *ecc_calc = chip->buffers->ecccalc;
 539         u8 *ecc_code = chip->buffers->ecccode;
 540         unsigned int max_bitflips = 0;
 541
 542         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 543              s++, i += eccbytes, p += eccsize) {
 544                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 545
 546                 /* Read the nand page sector (512 bytes) */
 547                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
 548                 chip->read_buf(mtd, p, eccsize);
 549
 550                 /* Read the corresponding ECC bytes */
 551                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
 552                 chip->read_buf(mtd, ecc_code, eccbytes);
 553
 554                 /* Correct the data */
 555                 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
 556                 if (stat == -EBADMSG)
 557                         /* Check for empty pages with bitflips */
 558                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 559                                                            ecc_code, eccbytes,
 560                                                            NULL, 0,
 561                                                            eccstrength);
 562
 563                 if (stat < 0) {
 564                         mtd->ecc_stats.failed++;
 565                 } else {
 566                         mtd->ecc_stats.corrected += stat;
 567                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 568                 }
 569         }
 570
 571         /* Read oob */
 572         if (oob_required) {
 573                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 574                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 575         }
 576
 577         return max_bitflips;
 578 }
 579
 580 /* Controller initialization */
 581 static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
 582 {
 583         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 584         u32 bcr1 = readl(fmc2->io_base + FMC2_BCR1);
 585
 586         /* Set CS used to undefined */
 587         fmc2->cs_sel = -1;
 588
 589         /* Enable wait feature and nand flash memory bank */
 590         pcr |= FMC2_PCR_PWAITEN;
 591         pcr |= FMC2_PCR_PBKEN;
 592
 593         /* Set buswidth to 8 bits mode for identification */
 594         pcr &= ~FMC2_PCR_PWID_MASK;
 595
 596         /* ECC logic is disabled */
 597         pcr &= ~FMC2_PCR_ECCEN;
 598
 599         /* Default mode */
 600         pcr &= ~FMC2_PCR_ECCALG;
 601         pcr &= ~FMC2_PCR_BCHECC;
 602         pcr &= ~FMC2_PCR_WEN;
 603
 604         /* Set default ECC sector size */
 605         pcr &= ~FMC2_PCR_ECCSS_MASK;
 606         pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
 607
 608         /* Set default tclr/tar timings */
 609         pcr &= ~FMC2_PCR_TCLR_MASK;
 610         pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
 611         pcr &= ~FMC2_PCR_TAR_MASK;
 612         pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
 613
 614         /* Enable FMC2 controller */
 615         bcr1 |= FMC2_BCR1_FMC2EN;
 616
 617         writel(bcr1, fmc2->io_base + FMC2_BCR1);
 618         writel(pcr, fmc2->io_base + FMC2_PCR);
 619         writel(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
 620         writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
 621 }
 622
 623 /* Controller timings */
 624 static void stm32_fmc2_calc_timings(struct nand_chip *chip,
 625                                     const struct nand_sdr_timings *sdrt)
 626 {
 627         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 628         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 629         struct stm32_fmc2_timings *tims = &nand->timings;
 630         unsigned long hclk = clk_get_rate(&fmc2->clk);
 631         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 632         unsigned long timing, tar, tclr, thiz, twait;
 633         unsigned long tset_mem, tset_att, thold_mem, thold_att;
 634
 635         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
 636         timing = DIV_ROUND_UP(tar, hclkp) - 1;
 637         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 638
 639         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
 640         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
 641         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 642
 643         tims->thiz = FMC2_THIZ;
 644         thiz = (tims->thiz + 1) * hclkp;
 645
 646         /*
 647          * tWAIT > tRP
 648          * tWAIT > tWP
 649          * tWAIT > tREA + tIO
 650          */
 651         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
 652         twait = max_t(unsigned long, twait, sdrt->tWP_min);
 653         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
 654         timing = DIV_ROUND_UP(twait, hclkp);
 655         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 656
 657         /*
 658          * tSETUP_MEM > tCS - tWAIT
 659          * tSETUP_MEM > tALS - tWAIT
 660          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
 661          */
 662         tset_mem = hclkp;
 663         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
 664                 tset_mem = sdrt->tCS_min - twait;
 665         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
 666                 tset_mem = sdrt->tALS_min - twait;
 667         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 668             (tset_mem < sdrt->tDS_min - (twait - thiz)))
 669                 tset_mem = sdrt->tDS_min - (twait - thiz);
 670         timing = DIV_ROUND_UP(tset_mem, hclkp);
 671         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 672
 673         /*
 674          * tHOLD_MEM > tCH
 675          * tHOLD_MEM > tREH - tSETUP_MEM
 676          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
 677          */
 678         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
 679         if (sdrt->tREH_min > tset_mem &&
 680             (thold_mem < sdrt->tREH_min - tset_mem))
 681                 thold_mem = sdrt->tREH_min - tset_mem;
 682         if ((sdrt->tRC_min > tset_mem + twait) &&
 683             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
 684                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
 685         if ((sdrt->tWC_min > tset_mem + twait) &&
 686             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
 687                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
 688         timing = DIV_ROUND_UP(thold_mem, hclkp);
 689         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 690
 691         /*
 692          * tSETUP_ATT > tCS - tWAIT
 693          * tSETUP_ATT > tCLS - tWAIT
 694          * tSETUP_ATT > tALS - tWAIT
 695          * tSETUP_ATT > tRHW - tHOLD_MEM
 696          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
 697          */
 698         tset_att = hclkp;
 699         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
 700                 tset_att = sdrt->tCS_min - twait;
 701         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
 702                 tset_att = sdrt->tCLS_min - twait;
 703         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
 704                 tset_att = sdrt->tALS_min - twait;
 705         if (sdrt->tRHW_min > thold_mem &&
 706             (tset_att < sdrt->tRHW_min - thold_mem))
 707                 tset_att = sdrt->tRHW_min - thold_mem;
 708         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 709             (tset_att < sdrt->tDS_min - (twait - thiz)))
 710                 tset_att = sdrt->tDS_min - (twait - thiz);
 711         timing = DIV_ROUND_UP(tset_att, hclkp);
 712         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 713
 714         /*
 715          * tHOLD_ATT > tALH
 716          * tHOLD_ATT > tCH
 717          * tHOLD_ATT > tCLH
 718          * tHOLD_ATT > tCOH
 719          * tHOLD_ATT > tDH
 720          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
 721          * tHOLD_ATT > tADL - tSETUP_MEM
 722          * tHOLD_ATT > tWH - tSETUP_MEM
 723          * tHOLD_ATT > tWHR - tSETUP_MEM
 724          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
 725          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
 726          */
 727         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
 728         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
 729         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
 730         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
 731         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
 732         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
 733             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
 734                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
 735         if (sdrt->tADL_min > tset_mem &&
 736             (thold_att < sdrt->tADL_min - tset_mem))
 737                 thold_att = sdrt->tADL_min - tset_mem;
 738         if (sdrt->tWH_min > tset_mem &&
 739             (thold_att < sdrt->tWH_min - tset_mem))
 740                 thold_att = sdrt->tWH_min - tset_mem;
 741         if (sdrt->tWHR_min > tset_mem &&
 742             (thold_att < sdrt->tWHR_min - tset_mem))
 743                 thold_att = sdrt->tWHR_min - tset_mem;
 744         if ((sdrt->tRC_min > tset_att + twait) &&
 745             (thold_att < sdrt->tRC_min - (tset_att + twait)))
 746                 thold_att = sdrt->tRC_min - (tset_att + twait);
 747         if ((sdrt->tWC_min > tset_att + twait) &&
 748             (thold_att < sdrt->tWC_min - (tset_att + twait)))
 749                 thold_att = sdrt->tWC_min - (tset_att + twait);
 750         timing = DIV_ROUND_UP(thold_att, hclkp);
 751         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 752 }
 753
 754 static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
 755                                       const struct nand_data_interface *conf)
 756 {
 757         struct nand_chip *chip = mtd_to_nand(mtd);
 758         const struct nand_sdr_timings *sdrt;
 759
 760         sdrt = nand_get_sdr_timings(conf);
 761         if (IS_ERR(sdrt))
 762                 return PTR_ERR(sdrt);
 763
 764         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
 765                 return 0;
 766
 767         stm32_fmc2_calc_timings(chip, sdrt);
 768
 769         /* Apply timings */
 770         stm32_fmc2_timings_init(chip);
 771
 772         return 0;
 773 }
 774
 775 /* NAND callbacks setup */
 776 static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
 777 {
 778         chip->ecc.hwctl = stm32_fmc2_hwctl;
 779
 780         /*
 781          * Specific callbacks to read/write a page depending on
 782          * the algo used (Hamming, BCH).
 783          */
 784         if (chip->ecc.strength == FMC2_ECC_HAM) {
 785                 /* Hamming is used */
 786                 chip->ecc.calculate = stm32_fmc2_ham_calculate;
 787                 chip->ecc.correct = stm32_fmc2_ham_correct;
 788                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
 789                 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
 790                 return;
 791         }
 792
 793         /* BCH is used */
 794         chip->ecc.read_page = stm32_fmc2_read_page;
 795         chip->ecc.calculate = stm32_fmc2_bch_calculate;
 796         chip->ecc.correct = stm32_fmc2_bch_correct;
 797
 798         if (chip->ecc.strength == FMC2_ECC_BCH8)
 799                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
 800         else
 801                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
 802 }
 803
 804 /* FMC2 caps */
 805 static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
 806 {
 807         /* Hamming */
 808         if (strength == FMC2_ECC_HAM)
 809                 return 4;
 810
 811         /* BCH8 */
 812         if (strength == FMC2_ECC_BCH8)
 813                 return 14;
 814
 815         /* BCH4 */
 816         return 8;
 817 }
 818
 819 NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
 820                      FMC2_ECC_STEP_SIZE,
 821                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
 822
 823 /* FMC2 probe */
 824 static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
 825                                   ofnode node)
 826 {
 827         struct stm32_fmc2_nand *nand = &fmc2->nand;
 828         u32 cs[FMC2_MAX_CE];
 829         int ret, i;
 830
 831         if (!ofnode_get_property(node, "reg", &nand->ncs))
 832                 return -EINVAL;
 833
 834         nand->ncs /= sizeof(u32);
 835         if (!nand->ncs) {
 836                 pr_err("Invalid reg property size\n");
 837                 return -EINVAL;
 838         }
 839
 840         ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
 841         if (ret < 0) {
 842                 pr_err("Could not retrieve reg property\n");
 843                 return -EINVAL;
 844         }
 845
 846         for (i = 0; i < nand->ncs; i++) {
 847                 if (cs[i] > FMC2_MAX_CE) {
 848                         pr_err("Invalid reg value: %d\n",
 849                                nand->cs_used[i]);
 850                         return -EINVAL;
 851                 }
 852
 853                 if (fmc2->cs_assigned & BIT(cs[i])) {
 854                         pr_err("Cs already assigned: %d\n",
 855                                nand->cs_used[i]);
 856                         return -EINVAL;
 857                 }
 858
 859                 fmc2->cs_assigned |= BIT(cs[i]);
 860                 nand->cs_used[i] = cs[i];
 861         }
 862
 863         nand->chip.flash_node = ofnode_to_offset(node);
 864
 865         return 0;
 866 }
 867
 868 static int stm32_fmc2_parse_dt(struct udevice *dev,
 869                                struct stm32_fmc2_nfc *fmc2)
 870 {
 871         ofnode child;
 872         int ret, nchips = 0;
 873
 874         dev_for_each_subnode(child, dev)
 875                 nchips++;
 876
 877         if (!nchips) {
 878                 pr_err("NAND chip not defined\n");
 879                 return -EINVAL;
 880         }
 881
 882         if (nchips > 1) {
 883                 pr_err("Too many NAND chips defined\n");
 884                 return -EINVAL;
 885         }
 886
 887         dev_for_each_subnode(child, dev) {
 888                 ret = stm32_fmc2_parse_child(fmc2, child);
 889                 if (ret)
 890                         return ret;
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int stm32_fmc2_probe(struct udevice *dev)
 897 {
 898         struct stm32_fmc2_nfc *fmc2 = dev_get_priv(dev);
 899         struct stm32_fmc2_nand *nand = &fmc2->nand;
 900         struct nand_chip *chip = &nand->chip;
 901         struct mtd_info *mtd = &chip->mtd;
 902         struct nand_ecclayout *ecclayout;
 903         struct resource resource;
 904         struct reset_ctl reset;
 905         int oob_index, chip_cs, mem_region, ret;
 906         unsigned int i;
 907
 908         spin_lock_init(&fmc2->controller.lock);
 909         init_waitqueue_head(&fmc2->controller.wq);
 910
 911         ret = stm32_fmc2_parse_dt(dev, fmc2);
 912         if (ret)
 913                 return ret;
 914
 915         /* Get resources */
 916         ret = dev_read_resource(dev, 0, &resource);
 917         if (ret) {
 918                 pr_err("Resource io_base not found");
 919                 return ret;
 920         }
 921         fmc2->io_base = (void __iomem *)resource.start;
 922
 923         for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
 924              chip_cs++, mem_region += 3) {
 925                 if (!(fmc2->cs_assigned & BIT(chip_cs)))
 926                         continue;
 927
 928                 ret = dev_read_resource(dev, mem_region, &resource);
 929                 if (ret) {
 930                         pr_err("Resource data_base not found for cs%d",
 931                                chip_cs);
 932                         return ret;
 933                 }
 934                 fmc2->data_base[chip_cs] = (void __iomem *)resource.start;
 935
 936                 ret = dev_read_resource(dev, mem_region + 1, &resource);
 937                 if (ret) {
 938                         pr_err("Resource cmd_base not found for cs%d",
 939                                chip_cs);
 940                         return ret;
 941                 }
 942                 fmc2->cmd_base[chip_cs] = (void __iomem *)resource.start;
 943
 944                 ret = dev_read_resource(dev, mem_region + 2, &resource);
 945                 if (ret) {
 946                         pr_err("Resource addr_base not found for cs%d",
 947                                chip_cs);
 948                         return ret;
 949                 }
 950                 fmc2->addr_base[chip_cs] = (void __iomem *)resource.start;
 951         }
 952
 953         /* Enable the clock */
 954         ret = clk_get_by_index(dev, 0, &fmc2->clk);
 955         if (ret)
 956                 return ret;
 957
 958         ret = clk_enable(&fmc2->clk);
 959         if (ret)
 960                 return ret;
 961
 962         /* Reset */
 963         ret = reset_get_by_index(dev, 0, &reset);
 964         if (!ret) {
 965                 reset_assert(&reset);
 966                 udelay(2);
 967                 reset_deassert(&reset);
 968         }
 969
 970         /* FMC2 init routine */
 971         stm32_fmc2_init(fmc2);
 972
 973         chip->controller = &fmc2->base;
 974         chip->select_chip = stm32_fmc2_select_chip;
 975         chip->setup_data_interface = stm32_fmc2_setup_interface;
 976         chip->cmd_ctrl = stm32_fmc2_cmd_ctrl;
 977         chip->chip_delay = FMC2_RB_DELAY_US;
 978         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 979                          NAND_USE_BOUNCE_BUFFER;
 980
 981         /* Default ECC settings */
 982         chip->ecc.mode = NAND_ECC_HW;
 983         chip->ecc.size = FMC2_ECC_STEP_SIZE;
 984         chip->ecc.strength = FMC2_ECC_BCH8;
 985
 986         /* Scan to find existence of the device */
 987         ret = nand_scan_ident(mtd, nand->ncs, NULL);
 988         if (ret)
 989                 return ret;
 990
 991         /*
 992          * Only NAND_ECC_HW mode is actually supported
 993          * Hamming => ecc.strength = 1
 994          * BCH4 => ecc.strength = 4
 995          * BCH8 => ecc.strength = 8
 996          * ECC sector size = 512
 997          */
 998         if (chip->ecc.mode != NAND_ECC_HW) {
 999                 pr_err("Nand_ecc_mode is not well defined in the DT\n");
1000                 return -EINVAL;
1001         }
1002
1003         ret = nand_check_ecc_caps(chip, &stm32_fmc2_ecc_caps,
1004                                   mtd->oobsize - FMC2_BBM_LEN);
1005         if (ret) {
1006                 pr_err("No valid ECC settings set\n");
1007                 return ret;
1008         }
1009
1010         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1011                 chip->bbt_options |= NAND_BBT_NO_OOB;
1012
1013         /* NAND callbacks setup */
1014         stm32_fmc2_nand_callbacks_setup(chip);
1015
1016         /* Define ECC layout */
1017         ecclayout = &fmc2->ecclayout;
1018         ecclayout->eccbytes = chip->ecc.bytes *
1019                               (mtd->writesize / chip->ecc.size);
1020         oob_index = FMC2_BBM_LEN;
1021         for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1022                 ecclayout->eccpos[i] = oob_index;
1023         ecclayout->oobfree->offset = oob_index;
1024         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1025         chip->ecc.layout = ecclayout;
1026
1027         /* Configure bus width to 16-bit */
1028         if (chip->options & NAND_BUSWIDTH_16)
1029                 stm32_fmc2_set_buswidth_16(fmc2, true);
1030
1031         /* Scan the device to fill MTD data-structures */
1032         ret = nand_scan_tail(mtd);
1033         if (ret)
1034                 return ret;
1035
1036         return nand_register(0, mtd);
1037 }
1038
1039 static const struct udevice_id stm32_fmc2_match[] = {
1040         { .compatible = "st,stm32mp15-fmc2" },
1041         { /* Sentinel */ }
1042 };
1043
1044 U_BOOT_DRIVER(stm32_fmc2_nand) = {
1045         .name = "stm32_fmc2_nand",
1046         .id = UCLASS_MTD,
1047         .of_match = stm32_fmc2_match,
1048         .probe = stm32_fmc2_probe,
1049         .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
1050 };
1051
1052 void board_nand_init(void)
1053 {
1054         struct udevice *dev;
1055         int ret;
1056
1057         ret = uclass_get_device_by_driver(UCLASS_MTD,
1058                                           DM_GET_DRIVER(stm32_fmc2_nand),
1059                                           &dev);
1060         if (ret && ret != -ENODEV)
1061                 pr_err("Failed to initialize STM32 FMC2 NAND controller. (error %d)\n",
1062                        ret);
1063 }