drivers/mtd/nand/raw/mxc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   4  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   5  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <nand.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <asm/io.h>
  14 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  15         defined(CONFIG_MX51) || defined(CONFIG_MX53)
  16 #include <asm/arch/imx-regs.h>
  17 #endif
  18 #include "mxc_nand.h"
  19
  20 #define DRIVER_NAME "mxc_nand"
  21
  22 struct mxc_nand_host {
  23         struct nand_chip                *nand;
  24
  25         struct mxc_nand_regs __iomem    *regs;
  26 #ifdef MXC_NFC_V3_2
  27         struct mxc_nand_ip_regs __iomem *ip_regs;
  28 #endif
  29         int                             spare_only;
  30         int                             status_request;
  31         int                             pagesize_2k;
  32         int                             clk_act;
  33         uint16_t                        col_addr;
  34         unsigned int                    page_addr;
  35 };
  36
  37 static struct mxc_nand_host mxc_host;
  38 static struct mxc_nand_host *host = &mxc_host;
  39
  40 /* Define delays in microsec for NAND device operations */
  41 #define TROP_US_DELAY   2000
  42 /* Macros to get byte and bit positions of ECC */
  43 #define COLPOS(x)  ((x) >> 3)
  44 #define BITPOS(x) ((x) & 0xf)
  45
  46 /* Define single bit Error positions in Main & Spare area */
  47 #define MAIN_SINGLEBIT_ERROR 0x4
  48 #define SPARE_SINGLEBIT_ERROR 0x1
  49
  50 /* OOB placement block for use with hardware ecc generation */
  51 #if defined(MXC_NFC_V1)
  52 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  53 static struct nand_ecclayout nand_hw_eccoob = {
  54         .eccbytes = 5,
  55         .eccpos = {6, 7, 8, 9, 10},
  56         .oobfree = { {0, 5}, {11, 5}, }
  57 };
  58 #else
  59 static struct nand_ecclayout nand_hw_eccoob2k = {
  60         .eccbytes = 20,
  61         .eccpos = {
  62                 6, 7, 8, 9, 10,
  63                 22, 23, 24, 25, 26,
  64                 38, 39, 40, 41, 42,
  65                 54, 55, 56, 57, 58,
  66         },
  67         .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  68 };
  69 #endif
  70 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  71 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  72 static struct nand_ecclayout nand_hw_eccoob = {
  73         .eccbytes = 9,
  74         .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  75         .oobfree = { {2, 5} }
  76 };
  77 #else
  78 static struct nand_ecclayout nand_hw_eccoob2k = {
  79         .eccbytes = 36,
  80         .eccpos = {
  81                 7, 8, 9, 10, 11, 12, 13, 14, 15,
  82                 23, 24, 25, 26, 27, 28, 29, 30, 31,
  83                 39, 40, 41, 42, 43, 44, 45, 46, 47,
  84                 55, 56, 57, 58, 59, 60, 61, 62, 63,
  85         },
  86         .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  87 };
  88 #endif
  89 #endif
  90
  91 static int is_16bit_nand(void)
  92 {
  93 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  94         return 1;
  95 #else
  96         return 0;
  97 #endif
  98 }
  99
 100 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
 101 {
 102         uint32_t *d = dest;
 103
 104         size >>= 2;
 105         while (size--)
 106                 __raw_writel(__raw_readl(source++), d++);
 107         return dest;
 108 }
 109
 110 /*
 111  * This function polls the NANDFC to wait for the basic operation to
 112  * complete by checking the INT bit.
 113  */
 114 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 115                                 uint16_t param)
 116 {
 117         uint32_t tmp;
 118
 119         while (max_retries-- > 0) {
 120 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 121                 tmp = readnfc(&host->regs->config2);
 122                 if (tmp & NFC_V1_V2_CONFIG2_INT) {
 123                         tmp &= ~NFC_V1_V2_CONFIG2_INT;
 124                         writenfc(tmp, &host->regs->config2);
 125 #elif defined(MXC_NFC_V3_2)
 126                 tmp = readnfc(&host->ip_regs->ipc);
 127                 if (tmp & NFC_V3_IPC_INT) {
 128                         tmp &= ~NFC_V3_IPC_INT;
 129                         writenfc(tmp, &host->ip_regs->ipc);
 130 #endif
 131                         break;
 132                 }
 133                 udelay(1);
 134         }
 135         if (max_retries < 0) {
 136                 pr_debug("%s(%d): INT not set\n",
 137                                 __func__, param);
 138         }
 139 }
 140
 141 /*
 142  * This function issues the specified command to the NAND device and
 143  * waits for completion.
 144  */
 145 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 146 {
 147         pr_debug("send_cmd(host, 0x%x)\n", cmd);
 148
 149         writenfc(cmd, &host->regs->flash_cmd);
 150         writenfc(NFC_CMD, &host->regs->operation);
 151
 152         /* Wait for operation to complete */
 153         wait_op_done(host, TROP_US_DELAY, cmd);
 154 }
 155
 156 /*
 157  * This function sends an address (or partial address) to the
 158  * NAND device. The address is used to select the source/destination for
 159  * a NAND command.
 160  */
 161 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 162 {
 163         pr_debug("send_addr(host, 0x%x)\n", addr);
 164
 165         writenfc(addr, &host->regs->flash_addr);
 166         writenfc(NFC_ADDR, &host->regs->operation);
 167
 168         /* Wait for operation to complete */
 169         wait_op_done(host, TROP_US_DELAY, addr);
 170 }
 171
 172 /*
 173  * This function requests the NANDFC to initiate the transfer
 174  * of data currently in the NANDFC RAM buffer to the NAND device.
 175  */
 176 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 177                         int spare_only)
 178 {
 179         if (spare_only)
 180                 pr_debug("send_prog_page (%d)\n", spare_only);
 181
 182         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 183                 int i;
 184                 /*
 185                  *  The controller copies the 64 bytes of spare data from
 186                  *  the first 16 bytes of each of the 4 64 byte spare buffers.
 187                  *  Copy the contiguous data starting in spare_area[0] to
 188                  *  the four spare area buffers.
 189                  */
 190                 for (i = 1; i < 4; i++) {
 191                         void __iomem *src = &host->regs->spare_area[0][i * 16];
 192                         void __iomem *dst = &host->regs->spare_area[i][0];
 193
 194                         mxc_nand_memcpy32(dst, src, 16);
 195                 }
 196         }
 197
 198 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 199         writenfc(buf_id, &host->regs->buf_addr);
 200 #elif defined(MXC_NFC_V3_2)
 201         uint32_t tmp = readnfc(&host->regs->config1);
 202         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 203         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 204         writenfc(tmp, &host->regs->config1);
 205 #endif
 206
 207         /* Configure spare or page+spare access */
 208         if (!host->pagesize_2k) {
 209                 uint32_t config1 = readnfc(&host->regs->config1);
 210                 if (spare_only)
 211                         config1 |= NFC_CONFIG1_SP_EN;
 212                 else
 213                         config1 &= ~NFC_CONFIG1_SP_EN;
 214                 writenfc(config1, &host->regs->config1);
 215         }
 216
 217         writenfc(NFC_INPUT, &host->regs->operation);
 218
 219         /* Wait for operation to complete */
 220         wait_op_done(host, TROP_US_DELAY, spare_only);
 221 }
 222
 223 /*
 224  * Requests NANDFC to initiate the transfer of data from the
 225  * NAND device into in the NANDFC ram buffer.
 226  */
 227 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 228                 int spare_only)
 229 {
 230         pr_debug("send_read_page (%d)\n", spare_only);
 231
 232 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 233         writenfc(buf_id, &host->regs->buf_addr);
 234 #elif defined(MXC_NFC_V3_2)
 235         uint32_t tmp = readnfc(&host->regs->config1);
 236         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 237         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 238         writenfc(tmp, &host->regs->config1);
 239 #endif
 240
 241         /* Configure spare or page+spare access */
 242         if (!host->pagesize_2k) {
 243                 uint32_t config1 = readnfc(&host->regs->config1);
 244                 if (spare_only)
 245                         config1 |= NFC_CONFIG1_SP_EN;
 246                 else
 247                         config1 &= ~NFC_CONFIG1_SP_EN;
 248                 writenfc(config1, &host->regs->config1);
 249         }
 250
 251         writenfc(NFC_OUTPUT, &host->regs->operation);
 252
 253         /* Wait for operation to complete */
 254         wait_op_done(host, TROP_US_DELAY, spare_only);
 255
 256         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 257                 int i;
 258
 259                 /*
 260                  *  The controller copies the 64 bytes of spare data to
 261                  *  the first 16 bytes of each of the 4 spare buffers.
 262                  *  Make the data contiguous starting in spare_area[0].
 263                  */
 264                 for (i = 1; i < 4; i++) {
 265                         void __iomem *src = &host->regs->spare_area[i][0];
 266                         void __iomem *dst = &host->regs->spare_area[0][i * 16];
 267
 268                         mxc_nand_memcpy32(dst, src, 16);
 269                 }
 270         }
 271 }
 272
 273 /* Request the NANDFC to perform a read of the NAND device ID. */
 274 static void send_read_id(struct mxc_nand_host *host)
 275 {
 276         uint32_t tmp;
 277
 278 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 279         /* NANDFC buffer 0 is used for device ID output */
 280         writenfc(0x0, &host->regs->buf_addr);
 281 #elif defined(MXC_NFC_V3_2)
 282         tmp = readnfc(&host->regs->config1);
 283         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 284         writenfc(tmp, &host->regs->config1);
 285 #endif
 286
 287         /* Read ID into main buffer */
 288         tmp = readnfc(&host->regs->config1);
 289         tmp &= ~NFC_CONFIG1_SP_EN;
 290         writenfc(tmp, &host->regs->config1);
 291
 292         writenfc(NFC_ID, &host->regs->operation);
 293
 294         /* Wait for operation to complete */
 295         wait_op_done(host, TROP_US_DELAY, 0);
 296 }
 297
 298 /*
 299  * This function requests the NANDFC to perform a read of the
 300  * NAND device status and returns the current status.
 301  */
 302 static uint16_t get_dev_status(struct mxc_nand_host *host)
 303 {
 304 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 305         void __iomem *main_buf = host->regs->main_area[1];
 306         uint32_t store;
 307 #endif
 308         uint32_t ret, tmp;
 309         /* Issue status request to NAND device */
 310
 311 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 312         /* store the main area1 first word, later do recovery */
 313         store = readl(main_buf);
 314         /* NANDFC buffer 1 is used for device status */
 315         writenfc(1, &host->regs->buf_addr);
 316 #endif
 317
 318         /* Read status into main buffer */
 319         tmp = readnfc(&host->regs->config1);
 320         tmp &= ~NFC_CONFIG1_SP_EN;
 321         writenfc(tmp, &host->regs->config1);
 322
 323         writenfc(NFC_STATUS, &host->regs->operation);
 324
 325         /* Wait for operation to complete */
 326         wait_op_done(host, TROP_US_DELAY, 0);
 327
 328 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 329         /*
 330          *  Status is placed in first word of main buffer
 331          * get status, then recovery area 1 data
 332          */
 333         ret = readw(main_buf);
 334         writel(store, main_buf);
 335 #elif defined(MXC_NFC_V3_2)
 336         ret = readnfc(&host->regs->config1) >> 16;
 337 #endif
 338
 339         return ret;
 340 }
 341
 342 /* This function is used by upper layer to checks if device is ready */
 343 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 344 {
 345         /*
 346          * NFC handles R/B internally. Therefore, this function
 347          * always returns status as ready.
 348          */
 349         return 1;
 350 }
 351
 352 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 353 {
 354         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 355         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 356 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 357         uint16_t tmp = readnfc(&host->regs->config1);
 358
 359         if (on)
 360                 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
 361         else
 362                 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 363         writenfc(tmp, &host->regs->config1);
 364 #elif defined(MXC_NFC_V3_2)
 365         uint32_t tmp = readnfc(&host->ip_regs->config2);
 366
 367         if (on)
 368                 tmp |= NFC_V3_CONFIG2_ECC_EN;
 369         else
 370                 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
 371         writenfc(tmp, &host->ip_regs->config2);
 372 #endif
 373 }
 374
 375 #ifdef CONFIG_MXC_NAND_HWECC
 376 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 377 {
 378         /*
 379          * If HW ECC is enabled, we turn it on during init. There is
 380          * no need to enable again here.
 381          */
 382 }
 383
 384 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
 385 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 386                                       struct nand_chip *chip,
 387                                       int page)
 388 {
 389         struct mxc_nand_host *host = nand_get_controller_data(chip);
 390         uint8_t *buf = chip->oob_poi;
 391         int length = mtd->oobsize;
 392         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 393         uint8_t *bufpoi = buf;
 394         int i, toread;
 395
 396         pr_debug("%s: Reading OOB area of page %u to oob %p\n",
 397                          __func__, page, buf);
 398
 399         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 400         for (i = 0; i < chip->ecc.steps; i++) {
 401                 toread = min_t(int, length, chip->ecc.prepad);
 402                 if (toread) {
 403                         chip->read_buf(mtd, bufpoi, toread);
 404                         bufpoi += toread;
 405                         length -= toread;
 406                 }
 407                 bufpoi += chip->ecc.bytes;
 408                 host->col_addr += chip->ecc.bytes;
 409                 length -= chip->ecc.bytes;
 410
 411                 toread = min_t(int, length, chip->ecc.postpad);
 412                 if (toread) {
 413                         chip->read_buf(mtd, bufpoi, toread);
 414                         bufpoi += toread;
 415                         length -= toread;
 416                 }
 417         }
 418         if (length > 0)
 419                 chip->read_buf(mtd, bufpoi, length);
 420
 421         _mxc_nand_enable_hwecc(mtd, 0);
 422         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 423                         mtd->writesize + chip->ecc.prepad, page);
 424         bufpoi = buf + chip->ecc.prepad;
 425         length = mtd->oobsize - chip->ecc.prepad;
 426         for (i = 0; i < chip->ecc.steps; i++) {
 427                 toread = min_t(int, length, chip->ecc.bytes);
 428                 chip->read_buf(mtd, bufpoi, toread);
 429                 bufpoi += eccpitch;
 430                 length -= eccpitch;
 431                 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
 432         }
 433         _mxc_nand_enable_hwecc(mtd, 1);
 434         return 1;
 435 }
 436
 437 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 438                                            struct nand_chip *chip,
 439                                            uint8_t *buf,
 440                                            int oob_required,
 441                                            int page)
 442 {
 443         struct mxc_nand_host *host = nand_get_controller_data(chip);
 444         int eccsize = chip->ecc.size;
 445         int eccbytes = chip->ecc.bytes;
 446         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 447         uint8_t *oob = chip->oob_poi;
 448         int steps, size;
 449         int n;
 450
 451         _mxc_nand_enable_hwecc(mtd, 0);
 452         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 453
 454         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 455                 host->col_addr = n * eccsize;
 456                 chip->read_buf(mtd, buf, eccsize);
 457                 buf += eccsize;
 458
 459                 host->col_addr = mtd->writesize + n * eccpitch;
 460                 if (chip->ecc.prepad) {
 461                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 462                         oob += chip->ecc.prepad;
 463                 }
 464
 465                 chip->read_buf(mtd, oob, eccbytes);
 466                 oob += eccbytes;
 467
 468                 if (chip->ecc.postpad) {
 469                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 470                         oob += chip->ecc.postpad;
 471                 }
 472         }
 473
 474         size = mtd->oobsize - (oob - chip->oob_poi);
 475         if (size)
 476                 chip->read_buf(mtd, oob, size);
 477         _mxc_nand_enable_hwecc(mtd, 1);
 478
 479         return 0;
 480 }
 481
 482 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 483                                        struct nand_chip *chip,
 484                                        uint8_t *buf,
 485                                        int oob_required,
 486                                        int page)
 487 {
 488         struct mxc_nand_host *host = nand_get_controller_data(chip);
 489         int n, eccsize = chip->ecc.size;
 490         int eccbytes = chip->ecc.bytes;
 491         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 492         int eccsteps = chip->ecc.steps;
 493         uint8_t *p = buf;
 494         uint8_t *oob = chip->oob_poi;
 495
 496         pr_debug("Reading page %u to buf %p oob %p\n",
 497                  page, buf, oob);
 498
 499         /* first read the data area and the available portion of OOB */
 500         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 501                 int stat;
 502
 503                 host->col_addr = n * eccsize;
 504
 505                 chip->read_buf(mtd, p, eccsize);
 506
 507                 host->col_addr = mtd->writesize + n * eccpitch;
 508
 509                 if (chip->ecc.prepad) {
 510                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 511                         oob += chip->ecc.prepad;
 512                 }
 513
 514                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 515
 516                 if (stat < 0)
 517                         mtd->ecc_stats.failed++;
 518                 else
 519                         mtd->ecc_stats.corrected += stat;
 520                 oob += eccbytes;
 521
 522                 if (chip->ecc.postpad) {
 523                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 524                         oob += chip->ecc.postpad;
 525                 }
 526         }
 527
 528         /* Calculate remaining oob bytes */
 529         n = mtd->oobsize - (oob - chip->oob_poi);
 530         if (n)
 531                 chip->read_buf(mtd, oob, n);
 532
 533         /* Then switch ECC off and read the OOB area to get the ECC code */
 534         _mxc_nand_enable_hwecc(mtd, 0);
 535         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 536         eccsteps = chip->ecc.steps;
 537         oob = chip->oob_poi + chip->ecc.prepad;
 538         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 539                 host->col_addr = mtd->writesize +
 540                                  n * eccpitch +
 541                                  chip->ecc.prepad;
 542                 chip->read_buf(mtd, oob, eccbytes);
 543                 oob += eccbytes + chip->ecc.postpad;
 544         }
 545         _mxc_nand_enable_hwecc(mtd, 1);
 546         return 0;
 547 }
 548
 549 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 550                                        struct nand_chip *chip, int page)
 551 {
 552         struct mxc_nand_host *host = nand_get_controller_data(chip);
 553         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 554         int length = mtd->oobsize;
 555         int i, len, status, steps = chip->ecc.steps;
 556         const uint8_t *bufpoi = chip->oob_poi;
 557
 558         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 559         for (i = 0; i < steps; i++) {
 560                 len = min_t(int, length, eccpitch);
 561
 562                 chip->write_buf(mtd, bufpoi, len);
 563                 bufpoi += len;
 564                 length -= len;
 565                 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
 566         }
 567         if (length > 0)
 568                 chip->write_buf(mtd, bufpoi, length);
 569
 570         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 571         status = chip->waitfunc(mtd, chip);
 572         return status & NAND_STATUS_FAIL ? -EIO : 0;
 573 }
 574
 575 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 576                                              struct nand_chip *chip,
 577                                              const uint8_t *buf,
 578                                              int oob_required, int page)
 579 {
 580         struct mxc_nand_host *host = nand_get_controller_data(chip);
 581         int eccsize = chip->ecc.size;
 582         int eccbytes = chip->ecc.bytes;
 583         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 584         uint8_t *oob = chip->oob_poi;
 585         int steps, size;
 586         int n;
 587
 588         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 589                 host->col_addr = n * eccsize;
 590                 chip->write_buf(mtd, buf, eccsize);
 591                 buf += eccsize;
 592
 593                 host->col_addr = mtd->writesize + n * eccpitch;
 594
 595                 if (chip->ecc.prepad) {
 596                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 597                         oob += chip->ecc.prepad;
 598                 }
 599
 600                 host->col_addr += eccbytes;
 601                 oob += eccbytes;
 602
 603                 if (chip->ecc.postpad) {
 604                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 605                         oob += chip->ecc.postpad;
 606                 }
 607         }
 608
 609         size = mtd->oobsize - (oob - chip->oob_poi);
 610         if (size)
 611                 chip->write_buf(mtd, oob, size);
 612         return 0;
 613 }
 614
 615 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 616                                          struct nand_chip *chip,
 617                                          const uint8_t *buf,
 618                                          int oob_required, int page)
 619 {
 620         struct mxc_nand_host *host = nand_get_controller_data(chip);
 621         int i, n, eccsize = chip->ecc.size;
 622         int eccbytes = chip->ecc.bytes;
 623         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 624         int eccsteps = chip->ecc.steps;
 625         const uint8_t *p = buf;
 626         uint8_t *oob = chip->oob_poi;
 627
 628         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 629
 630         for (i = n = 0;
 631              eccsteps;
 632              n++, eccsteps--, i += eccbytes, p += eccsize) {
 633                 host->col_addr = n * eccsize;
 634
 635                 chip->write_buf(mtd, p, eccsize);
 636
 637                 host->col_addr = mtd->writesize + n * eccpitch;
 638
 639                 if (chip->ecc.prepad) {
 640                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 641                         oob += chip->ecc.prepad;
 642                 }
 643
 644                 chip->write_buf(mtd, oob, eccbytes);
 645                 oob += eccbytes;
 646
 647                 if (chip->ecc.postpad) {
 648                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 649                         oob += chip->ecc.postpad;
 650                 }
 651         }
 652
 653         /* Calculate remaining oob bytes */
 654         i = mtd->oobsize - (oob - chip->oob_poi);
 655         if (i)
 656                 chip->write_buf(mtd, oob, i);
 657         return 0;
 658 }
 659
 660 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 661                                  u_char *read_ecc, u_char *calc_ecc)
 662 {
 663         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 664         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 665         uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 666         int subpages = mtd->writesize / nand_chip->subpagesize;
 667         int pg2blk_shift = nand_chip->phys_erase_shift -
 668                            nand_chip->page_shift;
 669
 670         do {
 671                 if ((ecc_status & 0xf) > 4) {
 672                         static int last_bad = -1;
 673
 674                         if (last_bad != host->page_addr >> pg2blk_shift) {
 675                                 last_bad = host->page_addr >> pg2blk_shift;
 676                                 printk(KERN_DEBUG
 677                                        "MXC_NAND: HWECC uncorrectable ECC error"
 678                                        " in block %u page %u subpage %d\n",
 679                                        last_bad, host->page_addr,
 680                                        mtd->writesize / nand_chip->subpagesize
 681                                             - subpages);
 682                         }
 683                         return -EBADMSG;
 684                 }
 685                 ecc_status >>= 4;
 686                 subpages--;
 687         } while (subpages > 0);
 688
 689         return 0;
 690 }
 691 #else
 692 #define mxc_nand_read_page_syndrome NULL
 693 #define mxc_nand_read_page_raw_syndrome NULL
 694 #define mxc_nand_read_oob_syndrome NULL
 695 #define mxc_nand_write_page_syndrome NULL
 696 #define mxc_nand_write_page_raw_syndrome NULL
 697 #define mxc_nand_write_oob_syndrome NULL
 698
 699 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 700                                  u_char *read_ecc, u_char *calc_ecc)
 701 {
 702         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 703         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 704
 705         /*
 706          * 1-Bit errors are automatically corrected in HW.  No need for
 707          * additional correction.  2-Bit errors cannot be corrected by
 708          * HW ECC, so we need to return failure
 709          */
 710         uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
 711
 712         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 713                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 714                 return -EBADMSG;
 715         }
 716
 717         return 0;
 718 }
 719 #endif
 720
 721 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 722                                   u_char *ecc_code)
 723 {
 724         return 0;
 725 }
 726 #endif
 727
 728 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 729 {
 730         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 731         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 732         uint8_t ret = 0;
 733         uint16_t col;
 734         uint16_t __iomem *main_buf =
 735                 (uint16_t __iomem *)host->regs->main_area[0];
 736         uint16_t __iomem *spare_buf =
 737                 (uint16_t __iomem *)host->regs->spare_area[0];
 738         union {
 739                 uint16_t word;
 740                 uint8_t bytes[2];
 741         } nfc_word;
 742
 743         /* Check for status request */
 744         if (host->status_request)
 745                 return get_dev_status(host) & 0xFF;
 746
 747         /* Get column for 16-bit access */
 748         col = host->col_addr >> 1;
 749
 750         /* If we are accessing the spare region */
 751         if (host->spare_only)
 752                 nfc_word.word = readw(&spare_buf[col]);
 753         else
 754                 nfc_word.word = readw(&main_buf[col]);
 755
 756         /* Pick upper/lower byte of word from RAM buffer */
 757         ret = nfc_word.bytes[host->col_addr & 0x1];
 758
 759         /* Update saved column address */
 760         if (nand_chip->options & NAND_BUSWIDTH_16)
 761                 host->col_addr += 2;
 762         else
 763                 host->col_addr++;
 764
 765         return ret;
 766 }
 767
 768 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 769 {
 770         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 771         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 772         uint16_t col, ret;
 773         uint16_t __iomem *p;
 774
 775         pr_debug("mxc_nand_read_word(col = %d)\n", host->col_addr);
 776
 777         col = host->col_addr;
 778         /* Adjust saved column address */
 779         if (col < mtd->writesize && host->spare_only)
 780                 col += mtd->writesize;
 781
 782         if (col < mtd->writesize) {
 783                 p = (uint16_t __iomem *)(host->regs->main_area[0] +
 784                                 (col >> 1));
 785         } else {
 786                 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 787                                 ((col - mtd->writesize) >> 1));
 788         }
 789
 790         if (col & 1) {
 791                 union {
 792                         uint16_t word;
 793                         uint8_t bytes[2];
 794                 } nfc_word[3];
 795
 796                 nfc_word[0].word = readw(p);
 797                 nfc_word[1].word = readw(p + 1);
 798
 799                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 800                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 801
 802                 ret = nfc_word[2].word;
 803         } else {
 804                 ret = readw(p);
 805         }
 806
 807         /* Update saved column address */
 808         host->col_addr = col + 2;
 809
 810         return ret;
 811 }
 812
 813 /*
 814  * Write data of length len to buffer buf. The data to be
 815  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 816  * Operation by the NFC, the data is written to NAND Flash
 817  */
 818 static void mxc_nand_write_buf(struct mtd_info *mtd,
 819                                 const u_char *buf, int len)
 820 {
 821         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 822         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 823         int n, col, i = 0;
 824
 825         pr_debug("mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 826                  len);
 827
 828         col = host->col_addr;
 829
 830         /* Adjust saved column address */
 831         if (col < mtd->writesize && host->spare_only)
 832                 col += mtd->writesize;
 833
 834         n = mtd->writesize + mtd->oobsize - col;
 835         n = min(len, n);
 836
 837         pr_debug("%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 838
 839         while (n > 0) {
 840                 void __iomem *p;
 841
 842                 if (col < mtd->writesize) {
 843                         p = host->regs->main_area[0] + (col & ~3);
 844                 } else {
 845                         p = host->regs->spare_area[0] -
 846                                                 mtd->writesize + (col & ~3);
 847                 }
 848
 849                 pr_debug("%s:%d: p = %p\n", __func__,
 850                          __LINE__, p);
 851
 852                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 853                         union {
 854                                 uint32_t word;
 855                                 uint8_t bytes[4];
 856                         } nfc_word;
 857
 858                         nfc_word.word = readl(p);
 859                         nfc_word.bytes[col & 3] = buf[i++];
 860                         n--;
 861                         col++;
 862
 863                         writel(nfc_word.word, p);
 864                 } else {
 865                         int m = mtd->writesize - col;
 866
 867                         if (col >= mtd->writesize)
 868                                 m += mtd->oobsize;
 869
 870                         m = min(n, m) & ~3;
 871
 872                         pr_debug("%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 873                                  __func__,  __LINE__, n, m, i, col);
 874
 875                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 876                         col += m;
 877                         i += m;
 878                         n -= m;
 879                 }
 880         }
 881         /* Update saved column address */
 882         host->col_addr = col;
 883 }
 884
 885 /*
 886  * Read the data buffer from the NAND Flash. To read the data from NAND
 887  * Flash first the data output cycle is initiated by the NFC, which copies
 888  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 889  */
 890 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 891 {
 892         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 893         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 894         int n, col, i = 0;
 895
 896         pr_debug("mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr,
 897                  len);
 898
 899         col = host->col_addr;
 900
 901         /* Adjust saved column address */
 902         if (col < mtd->writesize && host->spare_only)
 903                 col += mtd->writesize;
 904
 905         n = mtd->writesize + mtd->oobsize - col;
 906         n = min(len, n);
 907
 908         while (n > 0) {
 909                 void __iomem *p;
 910
 911                 if (col < mtd->writesize) {
 912                         p = host->regs->main_area[0] + (col & ~3);
 913                 } else {
 914                         p = host->regs->spare_area[0] -
 915                                         mtd->writesize + (col & ~3);
 916                 }
 917
 918                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 919                         union {
 920                                 uint32_t word;
 921                                 uint8_t bytes[4];
 922                         } nfc_word;
 923
 924                         nfc_word.word = readl(p);
 925                         buf[i++] = nfc_word.bytes[col & 3];
 926                         n--;
 927                         col++;
 928                 } else {
 929                         int m = mtd->writesize - col;
 930
 931                         if (col >= mtd->writesize)
 932                                 m += mtd->oobsize;
 933
 934                         m = min(n, m) & ~3;
 935                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 936
 937                         col += m;
 938                         i += m;
 939                         n -= m;
 940                 }
 941         }
 942         /* Update saved column address */
 943         host->col_addr = col;
 944 }
 945
 946 /*
 947  * This function is used by upper layer for select and
 948  * deselect of the NAND chip
 949  */
 950 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 951 {
 952         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 953         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 954
 955         switch (chip) {
 956         case -1:
 957                 /* TODO: Disable the NFC clock */
 958                 if (host->clk_act)
 959                         host->clk_act = 0;
 960                 break;
 961         case 0:
 962                 /* TODO: Enable the NFC clock */
 963                 if (!host->clk_act)
 964                         host->clk_act = 1;
 965                 break;
 966
 967         default:
 968                 break;
 969         }
 970 }
 971
 972 /*
 973  * Used by the upper layer to write command to NAND Flash for
 974  * different operations to be carried out on NAND Flash
 975  */
 976 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 977                                 int column, int page_addr)
 978 {
 979         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 980         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 981
 982         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 983                  command, column, page_addr);
 984
 985         /* Reset command state information */
 986         host->status_request = false;
 987
 988         /* Command pre-processing step */
 989         switch (command) {
 990
 991         case NAND_CMD_STATUS:
 992                 host->col_addr = 0;
 993                 host->status_request = true;
 994                 break;
 995
 996         case NAND_CMD_READ0:
 997                 host->page_addr = page_addr;
 998                 host->col_addr = column;
 999                 host->spare_only = false;
1000                 break;
1001
1002         case NAND_CMD_READOOB:
1003                 host->col_addr = column;
1004                 host->spare_only = true;
1005                 if (host->pagesize_2k)
1006                         command = NAND_CMD_READ0; /* only READ0 is valid */
1007                 break;
1008
1009         case NAND_CMD_SEQIN:
1010                 if (column >= mtd->writesize) {
1011                         /*
1012                          * before sending SEQIN command for partial write,
1013                          * we need read one page out. FSL NFC does not support
1014                          * partial write. It always sends out 512+ecc+512+ecc
1015                          * for large page nand flash. But for small page nand
1016                          * flash, it does support SPARE ONLY operation.
1017                          */
1018                         if (host->pagesize_2k) {
1019                                 /* call ourself to read a page */
1020                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1021                                                 page_addr);
1022                         }
1023
1024                         host->col_addr = column - mtd->writesize;
1025                         host->spare_only = true;
1026
1027                         /* Set program pointer to spare region */
1028                         if (!host->pagesize_2k)
1029                                 send_cmd(host, NAND_CMD_READOOB);
1030                 } else {
1031                         host->spare_only = false;
1032                         host->col_addr = column;
1033
1034                         /* Set program pointer to page start */
1035                         if (!host->pagesize_2k)
1036                                 send_cmd(host, NAND_CMD_READ0);
1037                 }
1038                 break;
1039
1040         case NAND_CMD_PAGEPROG:
1041                 send_prog_page(host, 0, host->spare_only);
1042
1043                 if (host->pagesize_2k && is_mxc_nfc_1()) {
1044                         /* data in 4 areas */
1045                         send_prog_page(host, 1, host->spare_only);
1046                         send_prog_page(host, 2, host->spare_only);
1047                         send_prog_page(host, 3, host->spare_only);
1048                 }
1049
1050                 break;
1051         }
1052
1053         /* Write out the command to the device. */
1054         send_cmd(host, command);
1055
1056         /* Write out column address, if necessary */
1057         if (column != -1) {
1058                 /*
1059                  * MXC NANDFC can only perform full page+spare or
1060                  * spare-only read/write. When the upper layers perform
1061                  * a read/write buffer operation, we will use the saved
1062                  * column address to index into the full page.
1063                  */
1064                 send_addr(host, 0);
1065                 if (host->pagesize_2k)
1066                         /* another col addr cycle for 2k page */
1067                         send_addr(host, 0);
1068         }
1069
1070         /* Write out page address, if necessary */
1071         if (page_addr != -1) {
1072                 u32 page_mask = nand_chip->pagemask;
1073                 do {
1074                         send_addr(host, page_addr & 0xFF);
1075                         page_addr >>= 8;
1076                         page_mask >>= 8;
1077                 } while (page_mask);
1078         }
1079
1080         /* Command post-processing step */
1081         switch (command) {
1082
1083         case NAND_CMD_RESET:
1084                 break;
1085
1086         case NAND_CMD_READOOB:
1087         case NAND_CMD_READ0:
1088                 if (host->pagesize_2k) {
1089                         /* send read confirm command */
1090                         send_cmd(host, NAND_CMD_READSTART);
1091                         /* read for each AREA */
1092                         send_read_page(host, 0, host->spare_only);
1093                         if (is_mxc_nfc_1()) {
1094                                 send_read_page(host, 1, host->spare_only);
1095                                 send_read_page(host, 2, host->spare_only);
1096                                 send_read_page(host, 3, host->spare_only);
1097                         }
1098                 } else {
1099                         send_read_page(host, 0, host->spare_only);
1100                 }
1101                 break;
1102
1103         case NAND_CMD_READID:
1104                 host->col_addr = 0;
1105                 send_read_id(host);
1106                 break;
1107
1108         case NAND_CMD_PAGEPROG:
1109                 break;
1110
1111         case NAND_CMD_STATUS:
1112                 break;
1113
1114         case NAND_CMD_ERASE2:
1115                 break;
1116         }
1117 }
1118
1119 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1120
1121 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1122 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1123
1124 static struct nand_bbt_descr bbt_main_descr = {
1125         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1126                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1127         .offs = 0,
1128         .len = 4,
1129         .veroffs = 4,
1130         .maxblocks = 4,
1131         .pattern = bbt_pattern,
1132 };
1133
1134 static struct nand_bbt_descr bbt_mirror_descr = {
1135         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1136                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1137         .offs = 0,
1138         .len = 4,
1139         .veroffs = 4,
1140         .maxblocks = 4,
1141         .pattern = mirror_pattern,
1142 };
1143
1144 #endif
1145
1146 int board_nand_init(struct nand_chip *this)
1147 {
1148         struct mtd_info *mtd;
1149 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1150         uint32_t tmp;
1151 #endif
1152
1153 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1154         this->bbt_options |= NAND_BBT_USE_FLASH;
1155         this->bbt_td = &bbt_main_descr;
1156         this->bbt_md = &bbt_mirror_descr;
1157 #endif
1158
1159         /* structures must be linked */
1160         mtd = &this->mtd;
1161         host->nand = this;
1162
1163         /* 5 us command delay time */
1164         this->chip_delay = 5;
1165
1166         nand_set_controller_data(this, host);
1167         this->dev_ready = mxc_nand_dev_ready;
1168         this->cmdfunc = mxc_nand_command;
1169         this->select_chip = mxc_nand_select_chip;
1170         this->read_byte = mxc_nand_read_byte;
1171         this->read_word = mxc_nand_read_word;
1172         this->write_buf = mxc_nand_write_buf;
1173         this->read_buf = mxc_nand_read_buf;
1174
1175         host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1176 #ifdef MXC_NFC_V3_2
1177         host->ip_regs =
1178                 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1179 #endif
1180         host->clk_act = 1;
1181
1182 #ifdef CONFIG_MXC_NAND_HWECC
1183         this->ecc.calculate = mxc_nand_calculate_ecc;
1184         this->ecc.hwctl = mxc_nand_enable_hwecc;
1185         this->ecc.correct = mxc_nand_correct_data;
1186         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1187                 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1188                 this->ecc.read_page = mxc_nand_read_page_syndrome;
1189                 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1190                 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1191                 this->ecc.write_page = mxc_nand_write_page_syndrome;
1192                 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1193                 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1194                 this->ecc.bytes = 9;
1195                 this->ecc.prepad = 7;
1196         } else {
1197                 this->ecc.mode = NAND_ECC_HW;
1198         }
1199
1200         if (is_mxc_nfc_1())
1201                 this->ecc.strength = 1;
1202         else
1203                 this->ecc.strength = 4;
1204
1205         host->pagesize_2k = 0;
1206
1207         this->ecc.size = 512;
1208         _mxc_nand_enable_hwecc(mtd, 1);
1209 #else
1210         this->ecc.layout = &nand_soft_eccoob;
1211         this->ecc.mode = NAND_ECC_SOFT;
1212         _mxc_nand_enable_hwecc(mtd, 0);
1213 #endif
1214         /* Reset NAND */
1215         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1216
1217         /* NAND bus width determines access functions used by upper layer */
1218         if (is_16bit_nand())
1219                 this->options |= NAND_BUSWIDTH_16;
1220
1221 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1222         host->pagesize_2k = 1;
1223         this->ecc.layout = &nand_hw_eccoob2k;
1224 #else
1225         host->pagesize_2k = 0;
1226         this->ecc.layout = &nand_hw_eccoob;
1227 #endif
1228
1229 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1230 #ifdef MXC_NFC_V2_1
1231         tmp = readnfc(&host->regs->config1);
1232         tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1233         tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1234         writenfc(tmp, &host->regs->config1);
1235         if (host->pagesize_2k)
1236                 writenfc(64/2, &host->regs->spare_area_size);
1237         else
1238                 writenfc(16/2, &host->regs->spare_area_size);
1239 #endif
1240
1241         /*
1242          * preset operation
1243          * Unlock the internal RAM Buffer
1244          */
1245         writenfc(0x2, &host->regs->config);
1246
1247         /* Blocks to be unlocked */
1248         writenfc(0x0, &host->regs->unlockstart_blkaddr);
1249         /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1250          * unlockend_blkaddr, but the magic 0x4000 does not always work
1251          * when writing more than some 32 megabytes (on 2k page nands)
1252          * However 0xFFFF doesn't seem to have this kind
1253          * of limitation (tried it back and forth several times).
1254          * The linux kernel driver sets this to 0xFFFF for the v2 controller
1255          * only, but probably this was not tested there for v1.
1256          * The very same limitation seems to apply to this kernel driver.
1257          * This might be NAND chip specific and the i.MX31 datasheet is
1258          * extremely vague about the semantics of this register.
1259          */
1260         writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1261
1262         /* Unlock Block Command for given address range */
1263         writenfc(0x4, &host->regs->wrprot);
1264 #elif defined(MXC_NFC_V3_2)
1265         writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1266         writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1267
1268         /* Unlock the internal RAM Buffer */
1269         writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1270                         &host->ip_regs->wrprot);
1271
1272         /* Blocks to be unlocked */
1273         for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1274                 writenfc(0x0 | 0xFFFF << 16,
1275                                 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1276
1277         writenfc(0, &host->ip_regs->ipc);
1278
1279         tmp = readnfc(&host->ip_regs->config2);
1280         tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1281                         NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1282         tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1283
1284         if (host->pagesize_2k) {
1285                 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1286                 tmp |= NFC_V3_CONFIG2_PS_2048;
1287         } else {
1288                 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1289                 tmp |= NFC_V3_CONFIG2_PS_512;
1290         }
1291
1292         writenfc(tmp, &host->ip_regs->config2);
1293
1294         tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1295                         NFC_V3_CONFIG3_NO_SDMA |
1296                         NFC_V3_CONFIG3_RBB_MODE |
1297                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1298                         NFC_V3_CONFIG3_ADD_OP(0);
1299
1300         if (!(this->options & NAND_BUSWIDTH_16))
1301                 tmp |= NFC_V3_CONFIG3_FW8;
1302
1303         writenfc(tmp, &host->ip_regs->config3);
1304
1305         writenfc(0, &host->ip_regs->delay_line);
1306 #endif
1307
1308         return 0;
1309 }