drivers/mtd/nand/raw/mxc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   4  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   5  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <nand.h>
  11 #include <linux/err.h>
  12 #include <asm/io.h>
  13 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  14         defined(CONFIG_MX51) || defined(CONFIG_MX53)
  15 #include <asm/arch/imx-regs.h>
  16 #endif
  17 #include "mxc_nand.h"
  18
  19 #define DRIVER_NAME "mxc_nand"
  20
  21 struct mxc_nand_host {
  22         struct nand_chip                *nand;
  23
  24         struct mxc_nand_regs __iomem    *regs;
  25 #ifdef MXC_NFC_V3_2
  26         struct mxc_nand_ip_regs __iomem *ip_regs;
  27 #endif
  28         int                             spare_only;
  29         int                             status_request;
  30         int                             pagesize_2k;
  31         int                             clk_act;
  32         uint16_t                        col_addr;
  33         unsigned int                    page_addr;
  34 };
  35
  36 static struct mxc_nand_host mxc_host;
  37 static struct mxc_nand_host *host = &mxc_host;
  38
  39 /* Define delays in microsec for NAND device operations */
  40 #define TROP_US_DELAY   2000
  41 /* Macros to get byte and bit positions of ECC */
  42 #define COLPOS(x)  ((x) >> 3)
  43 #define BITPOS(x) ((x) & 0xf)
  44
  45 /* Define single bit Error positions in Main & Spare area */
  46 #define MAIN_SINGLEBIT_ERROR 0x4
  47 #define SPARE_SINGLEBIT_ERROR 0x1
  48
  49 /* OOB placement block for use with hardware ecc generation */
  50 #if defined(MXC_NFC_V1)
  51 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  52 static struct nand_ecclayout nand_hw_eccoob = {
  53         .eccbytes = 5,
  54         .eccpos = {6, 7, 8, 9, 10},
  55         .oobfree = { {0, 5}, {11, 5}, }
  56 };
  57 #else
  58 static struct nand_ecclayout nand_hw_eccoob2k = {
  59         .eccbytes = 20,
  60         .eccpos = {
  61                 6, 7, 8, 9, 10,
  62                 22, 23, 24, 25, 26,
  63                 38, 39, 40, 41, 42,
  64                 54, 55, 56, 57, 58,
  65         },
  66         .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  67 };
  68 #endif
  69 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  70 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  71 static struct nand_ecclayout nand_hw_eccoob = {
  72         .eccbytes = 9,
  73         .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  74         .oobfree = { {2, 5} }
  75 };
  76 #else
  77 static struct nand_ecclayout nand_hw_eccoob2k = {
  78         .eccbytes = 36,
  79         .eccpos = {
  80                 7, 8, 9, 10, 11, 12, 13, 14, 15,
  81                 23, 24, 25, 26, 27, 28, 29, 30, 31,
  82                 39, 40, 41, 42, 43, 44, 45, 46, 47,
  83                 55, 56, 57, 58, 59, 60, 61, 62, 63,
  84         },
  85         .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  86 };
  87 #endif
  88 #endif
  89
  90 static int is_16bit_nand(void)
  91 {
  92 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  93         return 1;
  94 #else
  95         return 0;
  96 #endif
  97 }
  98
  99 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
 100 {
 101         uint32_t *d = dest;
 102
 103         size >>= 2;
 104         while (size--)
 105                 __raw_writel(__raw_readl(source++), d++);
 106         return dest;
 107 }
 108
 109 /*
 110  * This function polls the NANDFC to wait for the basic operation to
 111  * complete by checking the INT bit.
 112  */
 113 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 114                                 uint16_t param)
 115 {
 116         uint32_t tmp;
 117
 118         while (max_retries-- > 0) {
 119 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 120                 tmp = readnfc(&host->regs->config2);
 121                 if (tmp & NFC_V1_V2_CONFIG2_INT) {
 122                         tmp &= ~NFC_V1_V2_CONFIG2_INT;
 123                         writenfc(tmp, &host->regs->config2);
 124 #elif defined(MXC_NFC_V3_2)
 125                 tmp = readnfc(&host->ip_regs->ipc);
 126                 if (tmp & NFC_V3_IPC_INT) {
 127                         tmp &= ~NFC_V3_IPC_INT;
 128                         writenfc(tmp, &host->ip_regs->ipc);
 129 #endif
 130                         break;
 131                 }
 132                 udelay(1);
 133         }
 134         if (max_retries < 0) {
 135                 pr_debug("%s(%d): INT not set\n",
 136                                 __func__, param);
 137         }
 138 }
 139
 140 /*
 141  * This function issues the specified command to the NAND device and
 142  * waits for completion.
 143  */
 144 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 145 {
 146         pr_debug("send_cmd(host, 0x%x)\n", cmd);
 147
 148         writenfc(cmd, &host->regs->flash_cmd);
 149         writenfc(NFC_CMD, &host->regs->operation);
 150
 151         /* Wait for operation to complete */
 152         wait_op_done(host, TROP_US_DELAY, cmd);
 153 }
 154
 155 /*
 156  * This function sends an address (or partial address) to the
 157  * NAND device. The address is used to select the source/destination for
 158  * a NAND command.
 159  */
 160 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 161 {
 162         pr_debug("send_addr(host, 0x%x)\n", addr);
 163
 164         writenfc(addr, &host->regs->flash_addr);
 165         writenfc(NFC_ADDR, &host->regs->operation);
 166
 167         /* Wait for operation to complete */
 168         wait_op_done(host, TROP_US_DELAY, addr);
 169 }
 170
 171 /*
 172  * This function requests the NANDFC to initiate the transfer
 173  * of data currently in the NANDFC RAM buffer to the NAND device.
 174  */
 175 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 176                         int spare_only)
 177 {
 178         if (spare_only)
 179                 pr_debug("send_prog_page (%d)\n", spare_only);
 180
 181         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 182                 int i;
 183                 /*
 184                  *  The controller copies the 64 bytes of spare data from
 185                  *  the first 16 bytes of each of the 4 64 byte spare buffers.
 186                  *  Copy the contiguous data starting in spare_area[0] to
 187                  *  the four spare area buffers.
 188                  */
 189                 for (i = 1; i < 4; i++) {
 190                         void __iomem *src = &host->regs->spare_area[0][i * 16];
 191                         void __iomem *dst = &host->regs->spare_area[i][0];
 192
 193                         mxc_nand_memcpy32(dst, src, 16);
 194                 }
 195         }
 196
 197 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 198         writenfc(buf_id, &host->regs->buf_addr);
 199 #elif defined(MXC_NFC_V3_2)
 200         uint32_t tmp = readnfc(&host->regs->config1);
 201         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 202         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 203         writenfc(tmp, &host->regs->config1);
 204 #endif
 205
 206         /* Configure spare or page+spare access */
 207         if (!host->pagesize_2k) {
 208                 uint32_t config1 = readnfc(&host->regs->config1);
 209                 if (spare_only)
 210                         config1 |= NFC_CONFIG1_SP_EN;
 211                 else
 212                         config1 &= ~NFC_CONFIG1_SP_EN;
 213                 writenfc(config1, &host->regs->config1);
 214         }
 215
 216         writenfc(NFC_INPUT, &host->regs->operation);
 217
 218         /* Wait for operation to complete */
 219         wait_op_done(host, TROP_US_DELAY, spare_only);
 220 }
 221
 222 /*
 223  * Requests NANDFC to initiate the transfer of data from the
 224  * NAND device into in the NANDFC ram buffer.
 225  */
 226 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 227                 int spare_only)
 228 {
 229         pr_debug("send_read_page (%d)\n", spare_only);
 230
 231 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 232         writenfc(buf_id, &host->regs->buf_addr);
 233 #elif defined(MXC_NFC_V3_2)
 234         uint32_t tmp = readnfc(&host->regs->config1);
 235         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 236         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 237         writenfc(tmp, &host->regs->config1);
 238 #endif
 239
 240         /* Configure spare or page+spare access */
 241         if (!host->pagesize_2k) {
 242                 uint32_t config1 = readnfc(&host->regs->config1);
 243                 if (spare_only)
 244                         config1 |= NFC_CONFIG1_SP_EN;
 245                 else
 246                         config1 &= ~NFC_CONFIG1_SP_EN;
 247                 writenfc(config1, &host->regs->config1);
 248         }
 249
 250         writenfc(NFC_OUTPUT, &host->regs->operation);
 251
 252         /* Wait for operation to complete */
 253         wait_op_done(host, TROP_US_DELAY, spare_only);
 254
 255         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 256                 int i;
 257
 258                 /*
 259                  *  The controller copies the 64 bytes of spare data to
 260                  *  the first 16 bytes of each of the 4 spare buffers.
 261                  *  Make the data contiguous starting in spare_area[0].
 262                  */
 263                 for (i = 1; i < 4; i++) {
 264                         void __iomem *src = &host->regs->spare_area[i][0];
 265                         void __iomem *dst = &host->regs->spare_area[0][i * 16];
 266
 267                         mxc_nand_memcpy32(dst, src, 16);
 268                 }
 269         }
 270 }
 271
 272 /* Request the NANDFC to perform a read of the NAND device ID. */
 273 static void send_read_id(struct mxc_nand_host *host)
 274 {
 275         uint32_t tmp;
 276
 277 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 278         /* NANDFC buffer 0 is used for device ID output */
 279         writenfc(0x0, &host->regs->buf_addr);
 280 #elif defined(MXC_NFC_V3_2)
 281         tmp = readnfc(&host->regs->config1);
 282         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 283         writenfc(tmp, &host->regs->config1);
 284 #endif
 285
 286         /* Read ID into main buffer */
 287         tmp = readnfc(&host->regs->config1);
 288         tmp &= ~NFC_CONFIG1_SP_EN;
 289         writenfc(tmp, &host->regs->config1);
 290
 291         writenfc(NFC_ID, &host->regs->operation);
 292
 293         /* Wait for operation to complete */
 294         wait_op_done(host, TROP_US_DELAY, 0);
 295 }
 296
 297 /*
 298  * This function requests the NANDFC to perform a read of the
 299  * NAND device status and returns the current status.
 300  */
 301 static uint16_t get_dev_status(struct mxc_nand_host *host)
 302 {
 303 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 304         void __iomem *main_buf = host->regs->main_area[1];
 305         uint32_t store;
 306 #endif
 307         uint32_t ret, tmp;
 308         /* Issue status request to NAND device */
 309
 310 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 311         /* store the main area1 first word, later do recovery */
 312         store = readl(main_buf);
 313         /* NANDFC buffer 1 is used for device status */
 314         writenfc(1, &host->regs->buf_addr);
 315 #endif
 316
 317         /* Read status into main buffer */
 318         tmp = readnfc(&host->regs->config1);
 319         tmp &= ~NFC_CONFIG1_SP_EN;
 320         writenfc(tmp, &host->regs->config1);
 321
 322         writenfc(NFC_STATUS, &host->regs->operation);
 323
 324         /* Wait for operation to complete */
 325         wait_op_done(host, TROP_US_DELAY, 0);
 326
 327 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 328         /*
 329          *  Status is placed in first word of main buffer
 330          * get status, then recovery area 1 data
 331          */
 332         ret = readw(main_buf);
 333         writel(store, main_buf);
 334 #elif defined(MXC_NFC_V3_2)
 335         ret = readnfc(&host->regs->config1) >> 16;
 336 #endif
 337
 338         return ret;
 339 }
 340
 341 /* This function is used by upper layer to checks if device is ready */
 342 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 343 {
 344         /*
 345          * NFC handles R/B internally. Therefore, this function
 346          * always returns status as ready.
 347          */
 348         return 1;
 349 }
 350
 351 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 352 {
 353         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 354         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 355 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 356         uint16_t tmp = readnfc(&host->regs->config1);
 357
 358         if (on)
 359                 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
 360         else
 361                 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 362         writenfc(tmp, &host->regs->config1);
 363 #elif defined(MXC_NFC_V3_2)
 364         uint32_t tmp = readnfc(&host->ip_regs->config2);
 365
 366         if (on)
 367                 tmp |= NFC_V3_CONFIG2_ECC_EN;
 368         else
 369                 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
 370         writenfc(tmp, &host->ip_regs->config2);
 371 #endif
 372 }
 373
 374 #ifdef CONFIG_MXC_NAND_HWECC
 375 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 376 {
 377         /*
 378          * If HW ECC is enabled, we turn it on during init. There is
 379          * no need to enable again here.
 380          */
 381 }
 382
 383 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
 384 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 385                                       struct nand_chip *chip,
 386                                       int page)
 387 {
 388         struct mxc_nand_host *host = nand_get_controller_data(chip);
 389         uint8_t *buf = chip->oob_poi;
 390         int length = mtd->oobsize;
 391         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 392         uint8_t *bufpoi = buf;
 393         int i, toread;
 394
 395         pr_debug("%s: Reading OOB area of page %u to oob %p\n",
 396                          __func__, page, buf);
 397
 398         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 399         for (i = 0; i < chip->ecc.steps; i++) {
 400                 toread = min_t(int, length, chip->ecc.prepad);
 401                 if (toread) {
 402                         chip->read_buf(mtd, bufpoi, toread);
 403                         bufpoi += toread;
 404                         length -= toread;
 405                 }
 406                 bufpoi += chip->ecc.bytes;
 407                 host->col_addr += chip->ecc.bytes;
 408                 length -= chip->ecc.bytes;
 409
 410                 toread = min_t(int, length, chip->ecc.postpad);
 411                 if (toread) {
 412                         chip->read_buf(mtd, bufpoi, toread);
 413                         bufpoi += toread;
 414                         length -= toread;
 415                 }
 416         }
 417         if (length > 0)
 418                 chip->read_buf(mtd, bufpoi, length);
 419
 420         _mxc_nand_enable_hwecc(mtd, 0);
 421         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 422                         mtd->writesize + chip->ecc.prepad, page);
 423         bufpoi = buf + chip->ecc.prepad;
 424         length = mtd->oobsize - chip->ecc.prepad;
 425         for (i = 0; i < chip->ecc.steps; i++) {
 426                 toread = min_t(int, length, chip->ecc.bytes);
 427                 chip->read_buf(mtd, bufpoi, toread);
 428                 bufpoi += eccpitch;
 429                 length -= eccpitch;
 430                 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
 431         }
 432         _mxc_nand_enable_hwecc(mtd, 1);
 433         return 1;
 434 }
 435
 436 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 437                                            struct nand_chip *chip,
 438                                            uint8_t *buf,
 439                                            int oob_required,
 440                                            int page)
 441 {
 442         struct mxc_nand_host *host = nand_get_controller_data(chip);
 443         int eccsize = chip->ecc.size;
 444         int eccbytes = chip->ecc.bytes;
 445         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 446         uint8_t *oob = chip->oob_poi;
 447         int steps, size;
 448         int n;
 449
 450         _mxc_nand_enable_hwecc(mtd, 0);
 451         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 452
 453         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 454                 host->col_addr = n * eccsize;
 455                 chip->read_buf(mtd, buf, eccsize);
 456                 buf += eccsize;
 457
 458                 host->col_addr = mtd->writesize + n * eccpitch;
 459                 if (chip->ecc.prepad) {
 460                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 461                         oob += chip->ecc.prepad;
 462                 }
 463
 464                 chip->read_buf(mtd, oob, eccbytes);
 465                 oob += eccbytes;
 466
 467                 if (chip->ecc.postpad) {
 468                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 469                         oob += chip->ecc.postpad;
 470                 }
 471         }
 472
 473         size = mtd->oobsize - (oob - chip->oob_poi);
 474         if (size)
 475                 chip->read_buf(mtd, oob, size);
 476         _mxc_nand_enable_hwecc(mtd, 1);
 477
 478         return 0;
 479 }
 480
 481 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 482                                        struct nand_chip *chip,
 483                                        uint8_t *buf,
 484                                        int oob_required,
 485                                        int page)
 486 {
 487         struct mxc_nand_host *host = nand_get_controller_data(chip);
 488         int n, eccsize = chip->ecc.size;
 489         int eccbytes = chip->ecc.bytes;
 490         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 491         int eccsteps = chip->ecc.steps;
 492         uint8_t *p = buf;
 493         uint8_t *oob = chip->oob_poi;
 494
 495         pr_debug("Reading page %u to buf %p oob %p\n",
 496                  page, buf, oob);
 497
 498         /* first read the data area and the available portion of OOB */
 499         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 500                 int stat;
 501
 502                 host->col_addr = n * eccsize;
 503
 504                 chip->read_buf(mtd, p, eccsize);
 505
 506                 host->col_addr = mtd->writesize + n * eccpitch;
 507
 508                 if (chip->ecc.prepad) {
 509                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 510                         oob += chip->ecc.prepad;
 511                 }
 512
 513                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 514
 515                 if (stat < 0)
 516                         mtd->ecc_stats.failed++;
 517                 else
 518                         mtd->ecc_stats.corrected += stat;
 519                 oob += eccbytes;
 520
 521                 if (chip->ecc.postpad) {
 522                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 523                         oob += chip->ecc.postpad;
 524                 }
 525         }
 526
 527         /* Calculate remaining oob bytes */
 528         n = mtd->oobsize - (oob - chip->oob_poi);
 529         if (n)
 530                 chip->read_buf(mtd, oob, n);
 531
 532         /* Then switch ECC off and read the OOB area to get the ECC code */
 533         _mxc_nand_enable_hwecc(mtd, 0);
 534         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 535         eccsteps = chip->ecc.steps;
 536         oob = chip->oob_poi + chip->ecc.prepad;
 537         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 538                 host->col_addr = mtd->writesize +
 539                                  n * eccpitch +
 540                                  chip->ecc.prepad;
 541                 chip->read_buf(mtd, oob, eccbytes);
 542                 oob += eccbytes + chip->ecc.postpad;
 543         }
 544         _mxc_nand_enable_hwecc(mtd, 1);
 545         return 0;
 546 }
 547
 548 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 549                                        struct nand_chip *chip, int page)
 550 {
 551         struct mxc_nand_host *host = nand_get_controller_data(chip);
 552         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 553         int length = mtd->oobsize;
 554         int i, len, status, steps = chip->ecc.steps;
 555         const uint8_t *bufpoi = chip->oob_poi;
 556
 557         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 558         for (i = 0; i < steps; i++) {
 559                 len = min_t(int, length, eccpitch);
 560
 561                 chip->write_buf(mtd, bufpoi, len);
 562                 bufpoi += len;
 563                 length -= len;
 564                 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
 565         }
 566         if (length > 0)
 567                 chip->write_buf(mtd, bufpoi, length);
 568
 569         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 570         status = chip->waitfunc(mtd, chip);
 571         return status & NAND_STATUS_FAIL ? -EIO : 0;
 572 }
 573
 574 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 575                                              struct nand_chip *chip,
 576                                              const uint8_t *buf,
 577                                              int oob_required, int page)
 578 {
 579         struct mxc_nand_host *host = nand_get_controller_data(chip);
 580         int eccsize = chip->ecc.size;
 581         int eccbytes = chip->ecc.bytes;
 582         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 583         uint8_t *oob = chip->oob_poi;
 584         int steps, size;
 585         int n;
 586
 587         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 588                 host->col_addr = n * eccsize;
 589                 chip->write_buf(mtd, buf, eccsize);
 590                 buf += eccsize;
 591
 592                 host->col_addr = mtd->writesize + n * eccpitch;
 593
 594                 if (chip->ecc.prepad) {
 595                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 596                         oob += chip->ecc.prepad;
 597                 }
 598
 599                 host->col_addr += eccbytes;
 600                 oob += eccbytes;
 601
 602                 if (chip->ecc.postpad) {
 603                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 604                         oob += chip->ecc.postpad;
 605                 }
 606         }
 607
 608         size = mtd->oobsize - (oob - chip->oob_poi);
 609         if (size)
 610                 chip->write_buf(mtd, oob, size);
 611         return 0;
 612 }
 613
 614 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 615                                          struct nand_chip *chip,
 616                                          const uint8_t *buf,
 617                                          int oob_required, int page)
 618 {
 619         struct mxc_nand_host *host = nand_get_controller_data(chip);
 620         int i, n, eccsize = chip->ecc.size;
 621         int eccbytes = chip->ecc.bytes;
 622         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 623         int eccsteps = chip->ecc.steps;
 624         const uint8_t *p = buf;
 625         uint8_t *oob = chip->oob_poi;
 626
 627         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 628
 629         for (i = n = 0;
 630              eccsteps;
 631              n++, eccsteps--, i += eccbytes, p += eccsize) {
 632                 host->col_addr = n * eccsize;
 633
 634                 chip->write_buf(mtd, p, eccsize);
 635
 636                 host->col_addr = mtd->writesize + n * eccpitch;
 637
 638                 if (chip->ecc.prepad) {
 639                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 640                         oob += chip->ecc.prepad;
 641                 }
 642
 643                 chip->write_buf(mtd, oob, eccbytes);
 644                 oob += eccbytes;
 645
 646                 if (chip->ecc.postpad) {
 647                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 648                         oob += chip->ecc.postpad;
 649                 }
 650         }
 651
 652         /* Calculate remaining oob bytes */
 653         i = mtd->oobsize - (oob - chip->oob_poi);
 654         if (i)
 655                 chip->write_buf(mtd, oob, i);
 656         return 0;
 657 }
 658
 659 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 660                                  u_char *read_ecc, u_char *calc_ecc)
 661 {
 662         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 663         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 664         uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 665         int subpages = mtd->writesize / nand_chip->subpagesize;
 666         int pg2blk_shift = nand_chip->phys_erase_shift -
 667                            nand_chip->page_shift;
 668
 669         do {
 670                 if ((ecc_status & 0xf) > 4) {
 671                         static int last_bad = -1;
 672
 673                         if (last_bad != host->page_addr >> pg2blk_shift) {
 674                                 last_bad = host->page_addr >> pg2blk_shift;
 675                                 printk(KERN_DEBUG
 676                                        "MXC_NAND: HWECC uncorrectable ECC error"
 677                                        " in block %u page %u subpage %d\n",
 678                                        last_bad, host->page_addr,
 679                                        mtd->writesize / nand_chip->subpagesize
 680                                             - subpages);
 681                         }
 682                         return -EBADMSG;
 683                 }
 684                 ecc_status >>= 4;
 685                 subpages--;
 686         } while (subpages > 0);
 687
 688         return 0;
 689 }
 690 #else
 691 #define mxc_nand_read_page_syndrome NULL
 692 #define mxc_nand_read_page_raw_syndrome NULL
 693 #define mxc_nand_read_oob_syndrome NULL
 694 #define mxc_nand_write_page_syndrome NULL
 695 #define mxc_nand_write_page_raw_syndrome NULL
 696 #define mxc_nand_write_oob_syndrome NULL
 697
 698 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 699                                  u_char *read_ecc, u_char *calc_ecc)
 700 {
 701         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 702         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 703
 704         /*
 705          * 1-Bit errors are automatically corrected in HW.  No need for
 706          * additional correction.  2-Bit errors cannot be corrected by
 707          * HW ECC, so we need to return failure
 708          */
 709         uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
 710
 711         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 712                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 713                 return -EBADMSG;
 714         }
 715
 716         return 0;
 717 }
 718 #endif
 719
 720 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 721                                   u_char *ecc_code)
 722 {
 723         return 0;
 724 }
 725 #endif
 726
 727 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 728 {
 729         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 730         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 731         uint8_t ret = 0;
 732         uint16_t col;
 733         uint16_t __iomem *main_buf =
 734                 (uint16_t __iomem *)host->regs->main_area[0];
 735         uint16_t __iomem *spare_buf =
 736                 (uint16_t __iomem *)host->regs->spare_area[0];
 737         union {
 738                 uint16_t word;
 739                 uint8_t bytes[2];
 740         } nfc_word;
 741
 742         /* Check for status request */
 743         if (host->status_request)
 744                 return get_dev_status(host) & 0xFF;
 745
 746         /* Get column for 16-bit access */
 747         col = host->col_addr >> 1;
 748
 749         /* If we are accessing the spare region */
 750         if (host->spare_only)
 751                 nfc_word.word = readw(&spare_buf[col]);
 752         else
 753                 nfc_word.word = readw(&main_buf[col]);
 754
 755         /* Pick upper/lower byte of word from RAM buffer */
 756         ret = nfc_word.bytes[host->col_addr & 0x1];
 757
 758         /* Update saved column address */
 759         if (nand_chip->options & NAND_BUSWIDTH_16)
 760                 host->col_addr += 2;
 761         else
 762                 host->col_addr++;
 763
 764         return ret;
 765 }
 766
 767 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 768 {
 769         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 770         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 771         uint16_t col, ret;
 772         uint16_t __iomem *p;
 773
 774         pr_debug("mxc_nand_read_word(col = %d)\n", host->col_addr);
 775
 776         col = host->col_addr;
 777         /* Adjust saved column address */
 778         if (col < mtd->writesize && host->spare_only)
 779                 col += mtd->writesize;
 780
 781         if (col < mtd->writesize) {
 782                 p = (uint16_t __iomem *)(host->regs->main_area[0] +
 783                                 (col >> 1));
 784         } else {
 785                 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 786                                 ((col - mtd->writesize) >> 1));
 787         }
 788
 789         if (col & 1) {
 790                 union {
 791                         uint16_t word;
 792                         uint8_t bytes[2];
 793                 } nfc_word[3];
 794
 795                 nfc_word[0].word = readw(p);
 796                 nfc_word[1].word = readw(p + 1);
 797
 798                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 799                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 800
 801                 ret = nfc_word[2].word;
 802         } else {
 803                 ret = readw(p);
 804         }
 805
 806         /* Update saved column address */
 807         host->col_addr = col + 2;
 808
 809         return ret;
 810 }
 811
 812 /*
 813  * Write data of length len to buffer buf. The data to be
 814  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 815  * Operation by the NFC, the data is written to NAND Flash
 816  */
 817 static void mxc_nand_write_buf(struct mtd_info *mtd,
 818                                 const u_char *buf, int len)
 819 {
 820         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 821         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 822         int n, col, i = 0;
 823
 824         pr_debug("mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 825                  len);
 826
 827         col = host->col_addr;
 828
 829         /* Adjust saved column address */
 830         if (col < mtd->writesize && host->spare_only)
 831                 col += mtd->writesize;
 832
 833         n = mtd->writesize + mtd->oobsize - col;
 834         n = min(len, n);
 835
 836         pr_debug("%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 837
 838         while (n > 0) {
 839                 void __iomem *p;
 840
 841                 if (col < mtd->writesize) {
 842                         p = host->regs->main_area[0] + (col & ~3);
 843                 } else {
 844                         p = host->regs->spare_area[0] -
 845                                                 mtd->writesize + (col & ~3);
 846                 }
 847
 848                 pr_debug("%s:%d: p = %p\n", __func__,
 849                          __LINE__, p);
 850
 851                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 852                         union {
 853                                 uint32_t word;
 854                                 uint8_t bytes[4];
 855                         } nfc_word;
 856
 857                         nfc_word.word = readl(p);
 858                         nfc_word.bytes[col & 3] = buf[i++];
 859                         n--;
 860                         col++;
 861
 862                         writel(nfc_word.word, p);
 863                 } else {
 864                         int m = mtd->writesize - col;
 865
 866                         if (col >= mtd->writesize)
 867                                 m += mtd->oobsize;
 868
 869                         m = min(n, m) & ~3;
 870
 871                         pr_debug("%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 872                                  __func__,  __LINE__, n, m, i, col);
 873
 874                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 875                         col += m;
 876                         i += m;
 877                         n -= m;
 878                 }
 879         }
 880         /* Update saved column address */
 881         host->col_addr = col;
 882 }
 883
 884 /*
 885  * Read the data buffer from the NAND Flash. To read the data from NAND
 886  * Flash first the data output cycle is initiated by the NFC, which copies
 887  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 888  */
 889 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 890 {
 891         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 892         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 893         int n, col, i = 0;
 894
 895         pr_debug("mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr,
 896                  len);
 897
 898         col = host->col_addr;
 899
 900         /* Adjust saved column address */
 901         if (col < mtd->writesize && host->spare_only)
 902                 col += mtd->writesize;
 903
 904         n = mtd->writesize + mtd->oobsize - col;
 905         n = min(len, n);
 906
 907         while (n > 0) {
 908                 void __iomem *p;
 909
 910                 if (col < mtd->writesize) {
 911                         p = host->regs->main_area[0] + (col & ~3);
 912                 } else {
 913                         p = host->regs->spare_area[0] -
 914                                         mtd->writesize + (col & ~3);
 915                 }
 916
 917                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 918                         union {
 919                                 uint32_t word;
 920                                 uint8_t bytes[4];
 921                         } nfc_word;
 922
 923                         nfc_word.word = readl(p);
 924                         buf[i++] = nfc_word.bytes[col & 3];
 925                         n--;
 926                         col++;
 927                 } else {
 928                         int m = mtd->writesize - col;
 929
 930                         if (col >= mtd->writesize)
 931                                 m += mtd->oobsize;
 932
 933                         m = min(n, m) & ~3;
 934                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 935
 936                         col += m;
 937                         i += m;
 938                         n -= m;
 939                 }
 940         }
 941         /* Update saved column address */
 942         host->col_addr = col;
 943 }
 944
 945 /*
 946  * This function is used by upper layer for select and
 947  * deselect of the NAND chip
 948  */
 949 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 950 {
 951         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 952         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 953
 954         switch (chip) {
 955         case -1:
 956                 /* TODO: Disable the NFC clock */
 957                 if (host->clk_act)
 958                         host->clk_act = 0;
 959                 break;
 960         case 0:
 961                 /* TODO: Enable the NFC clock */
 962                 if (!host->clk_act)
 963                         host->clk_act = 1;
 964                 break;
 965
 966         default:
 967                 break;
 968         }
 969 }
 970
 971 /*
 972  * Used by the upper layer to write command to NAND Flash for
 973  * different operations to be carried out on NAND Flash
 974  */
 975 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 976                                 int column, int page_addr)
 977 {
 978         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 979         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 980
 981         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 982                  command, column, page_addr);
 983
 984         /* Reset command state information */
 985         host->status_request = false;
 986
 987         /* Command pre-processing step */
 988         switch (command) {
 989
 990         case NAND_CMD_STATUS:
 991                 host->col_addr = 0;
 992                 host->status_request = true;
 993                 break;
 994
 995         case NAND_CMD_READ0:
 996                 host->page_addr = page_addr;
 997                 host->col_addr = column;
 998                 host->spare_only = false;
 999                 break;
1000
1001         case NAND_CMD_READOOB:
1002                 host->col_addr = column;
1003                 host->spare_only = true;
1004                 if (host->pagesize_2k)
1005                         command = NAND_CMD_READ0; /* only READ0 is valid */
1006                 break;
1007
1008         case NAND_CMD_SEQIN:
1009                 if (column >= mtd->writesize) {
1010                         /*
1011                          * before sending SEQIN command for partial write,
1012                          * we need read one page out. FSL NFC does not support
1013                          * partial write. It always sends out 512+ecc+512+ecc
1014                          * for large page nand flash. But for small page nand
1015                          * flash, it does support SPARE ONLY operation.
1016                          */
1017                         if (host->pagesize_2k) {
1018                                 /* call ourself to read a page */
1019                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1020                                                 page_addr);
1021                         }
1022
1023                         host->col_addr = column - mtd->writesize;
1024                         host->spare_only = true;
1025
1026                         /* Set program pointer to spare region */
1027                         if (!host->pagesize_2k)
1028                                 send_cmd(host, NAND_CMD_READOOB);
1029                 } else {
1030                         host->spare_only = false;
1031                         host->col_addr = column;
1032
1033                         /* Set program pointer to page start */
1034                         if (!host->pagesize_2k)
1035                                 send_cmd(host, NAND_CMD_READ0);
1036                 }
1037                 break;
1038
1039         case NAND_CMD_PAGEPROG:
1040                 send_prog_page(host, 0, host->spare_only);
1041
1042                 if (host->pagesize_2k && is_mxc_nfc_1()) {
1043                         /* data in 4 areas */
1044                         send_prog_page(host, 1, host->spare_only);
1045                         send_prog_page(host, 2, host->spare_only);
1046                         send_prog_page(host, 3, host->spare_only);
1047                 }
1048
1049                 break;
1050         }
1051
1052         /* Write out the command to the device. */
1053         send_cmd(host, command);
1054
1055         /* Write out column address, if necessary */
1056         if (column != -1) {
1057                 /*
1058                  * MXC NANDFC can only perform full page+spare or
1059                  * spare-only read/write. When the upper layers perform
1060                  * a read/write buffer operation, we will use the saved
1061                  * column address to index into the full page.
1062                  */
1063                 send_addr(host, 0);
1064                 if (host->pagesize_2k)
1065                         /* another col addr cycle for 2k page */
1066                         send_addr(host, 0);
1067         }
1068
1069         /* Write out page address, if necessary */
1070         if (page_addr != -1) {
1071                 u32 page_mask = nand_chip->pagemask;
1072                 do {
1073                         send_addr(host, page_addr & 0xFF);
1074                         page_addr >>= 8;
1075                         page_mask >>= 8;
1076                 } while (page_mask);
1077         }
1078
1079         /* Command post-processing step */
1080         switch (command) {
1081
1082         case NAND_CMD_RESET:
1083                 break;
1084
1085         case NAND_CMD_READOOB:
1086         case NAND_CMD_READ0:
1087                 if (host->pagesize_2k) {
1088                         /* send read confirm command */
1089                         send_cmd(host, NAND_CMD_READSTART);
1090                         /* read for each AREA */
1091                         send_read_page(host, 0, host->spare_only);
1092                         if (is_mxc_nfc_1()) {
1093                                 send_read_page(host, 1, host->spare_only);
1094                                 send_read_page(host, 2, host->spare_only);
1095                                 send_read_page(host, 3, host->spare_only);
1096                         }
1097                 } else {
1098                         send_read_page(host, 0, host->spare_only);
1099                 }
1100                 break;
1101
1102         case NAND_CMD_READID:
1103                 host->col_addr = 0;
1104                 send_read_id(host);
1105                 break;
1106
1107         case NAND_CMD_PAGEPROG:
1108                 break;
1109
1110         case NAND_CMD_STATUS:
1111                 break;
1112
1113         case NAND_CMD_ERASE2:
1114                 break;
1115         }
1116 }
1117
1118 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1119
1120 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1121 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1122
1123 static struct nand_bbt_descr bbt_main_descr = {
1124         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1125                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1126         .offs = 0,
1127         .len = 4,
1128         .veroffs = 4,
1129         .maxblocks = 4,
1130         .pattern = bbt_pattern,
1131 };
1132
1133 static struct nand_bbt_descr bbt_mirror_descr = {
1134         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1135                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1136         .offs = 0,
1137         .len = 4,
1138         .veroffs = 4,
1139         .maxblocks = 4,
1140         .pattern = mirror_pattern,
1141 };
1142
1143 #endif
1144
1145 int board_nand_init(struct nand_chip *this)
1146 {
1147         struct mtd_info *mtd;
1148 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1149         uint32_t tmp;
1150 #endif
1151
1152 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1153         this->bbt_options |= NAND_BBT_USE_FLASH;
1154         this->bbt_td = &bbt_main_descr;
1155         this->bbt_md = &bbt_mirror_descr;
1156 #endif
1157
1158         /* structures must be linked */
1159         mtd = &this->mtd;
1160         host->nand = this;
1161
1162         /* 5 us command delay time */
1163         this->chip_delay = 5;
1164
1165         nand_set_controller_data(this, host);
1166         this->dev_ready = mxc_nand_dev_ready;
1167         this->cmdfunc = mxc_nand_command;
1168         this->select_chip = mxc_nand_select_chip;
1169         this->read_byte = mxc_nand_read_byte;
1170         this->read_word = mxc_nand_read_word;
1171         this->write_buf = mxc_nand_write_buf;
1172         this->read_buf = mxc_nand_read_buf;
1173
1174         host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1175 #ifdef MXC_NFC_V3_2
1176         host->ip_regs =
1177                 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1178 #endif
1179         host->clk_act = 1;
1180
1181 #ifdef CONFIG_MXC_NAND_HWECC
1182         this->ecc.calculate = mxc_nand_calculate_ecc;
1183         this->ecc.hwctl = mxc_nand_enable_hwecc;
1184         this->ecc.correct = mxc_nand_correct_data;
1185         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1186                 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1187                 this->ecc.read_page = mxc_nand_read_page_syndrome;
1188                 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1189                 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1190                 this->ecc.write_page = mxc_nand_write_page_syndrome;
1191                 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1192                 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1193                 this->ecc.bytes = 9;
1194                 this->ecc.prepad = 7;
1195         } else {
1196                 this->ecc.mode = NAND_ECC_HW;
1197         }
1198
1199         if (is_mxc_nfc_1())
1200                 this->ecc.strength = 1;
1201         else
1202                 this->ecc.strength = 4;
1203
1204         host->pagesize_2k = 0;
1205
1206         this->ecc.size = 512;
1207         _mxc_nand_enable_hwecc(mtd, 1);
1208 #else
1209         this->ecc.layout = &nand_soft_eccoob;
1210         this->ecc.mode = NAND_ECC_SOFT;
1211         _mxc_nand_enable_hwecc(mtd, 0);
1212 #endif
1213         /* Reset NAND */
1214         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1215
1216         /* NAND bus width determines access functions used by upper layer */
1217         if (is_16bit_nand())
1218                 this->options |= NAND_BUSWIDTH_16;
1219
1220 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1221         host->pagesize_2k = 1;
1222         this->ecc.layout = &nand_hw_eccoob2k;
1223 #else
1224         host->pagesize_2k = 0;
1225         this->ecc.layout = &nand_hw_eccoob;
1226 #endif
1227
1228 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1229 #ifdef MXC_NFC_V2_1
1230         tmp = readnfc(&host->regs->config1);
1231         tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1232         tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1233         writenfc(tmp, &host->regs->config1);
1234         if (host->pagesize_2k)
1235                 writenfc(64/2, &host->regs->spare_area_size);
1236         else
1237                 writenfc(16/2, &host->regs->spare_area_size);
1238 #endif
1239
1240         /*
1241          * preset operation
1242          * Unlock the internal RAM Buffer
1243          */
1244         writenfc(0x2, &host->regs->config);
1245
1246         /* Blocks to be unlocked */
1247         writenfc(0x0, &host->regs->unlockstart_blkaddr);
1248         /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1249          * unlockend_blkaddr, but the magic 0x4000 does not always work
1250          * when writing more than some 32 megabytes (on 2k page nands)
1251          * However 0xFFFF doesn't seem to have this kind
1252          * of limitation (tried it back and forth several times).
1253          * The linux kernel driver sets this to 0xFFFF for the v2 controller
1254          * only, but probably this was not tested there for v1.
1255          * The very same limitation seems to apply to this kernel driver.
1256          * This might be NAND chip specific and the i.MX31 datasheet is
1257          * extremely vague about the semantics of this register.
1258          */
1259         writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1260
1261         /* Unlock Block Command for given address range */
1262         writenfc(0x4, &host->regs->wrprot);
1263 #elif defined(MXC_NFC_V3_2)
1264         writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1265         writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1266
1267         /* Unlock the internal RAM Buffer */
1268         writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1269                         &host->ip_regs->wrprot);
1270
1271         /* Blocks to be unlocked */
1272         for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1273                 writenfc(0x0 | 0xFFFF << 16,
1274                                 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1275
1276         writenfc(0, &host->ip_regs->ipc);
1277
1278         tmp = readnfc(&host->ip_regs->config2);
1279         tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1280                         NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1281         tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1282
1283         if (host->pagesize_2k) {
1284                 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1285                 tmp |= NFC_V3_CONFIG2_PS_2048;
1286         } else {
1287                 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1288                 tmp |= NFC_V3_CONFIG2_PS_512;
1289         }
1290
1291         writenfc(tmp, &host->ip_regs->config2);
1292
1293         tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1294                         NFC_V3_CONFIG3_NO_SDMA |
1295                         NFC_V3_CONFIG3_RBB_MODE |
1296                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1297                         NFC_V3_CONFIG3_ADD_OP(0);
1298
1299         if (!(this->options & NAND_BUSWIDTH_16))
1300                 tmp |= NFC_V3_CONFIG3_FW8;
1301
1302         writenfc(tmp, &host->ip_regs->config3);
1303
1304         writenfc(0, &host->ip_regs->delay_line);
1305 #endif
1306
1307         return 0;
1308 }