drivers/mtd/nand/raw/atmel_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   8  *
   9  * Add Programmable Multibit ECC support for various AT91 SoC
  10  *     (C) Copyright 2012 ATMEL, Hong Xu
  11  */
  12
  13 #include <common.h>
  14 #include <log.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <linux/bug.h>
  20 #include <linux/delay.h>
  21
  22 #include <malloc.h>
  23 #include <nand.h>
  24 #include <watchdog.h>
  25 #include <linux/mtd/nand_ecc.h>
  26
  27 #ifdef CONFIG_ATMEL_NAND_HWECC
  28
  29 /* Register access macros */
  30 #define ecc_readl(add, reg)                             \
  31         readl(add + ATMEL_ECC_##reg)
  32 #define ecc_writel(add, reg, value)                     \
  33         writel((value), add + ATMEL_ECC_##reg)
  34
  35 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  36
  37 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  38
  39 #ifdef CONFIG_SPL_BUILD
  40 #undef CONFIG_SYS_NAND_ONFI_DETECTION
  41 #endif
  42
  43 struct atmel_nand_host {
  44         struct pmecc_regs __iomem *pmecc;
  45         struct pmecc_errloc_regs __iomem *pmerrloc;
  46         void __iomem            *pmecc_rom_base;
  47
  48         u8              pmecc_corr_cap;
  49         u16             pmecc_sector_size;
  50         u32             pmecc_index_table_offset;
  51         u32             pmecc_version;
  52
  53         int             pmecc_bytes_per_sector;
  54         int             pmecc_sector_number;
  55         int             pmecc_degree;   /* Degree of remainders */
  56         int             pmecc_cw_len;   /* Length of codeword */
  57
  58         /* lookup table for alpha_to and index_of */
  59         void __iomem    *pmecc_alpha_to;
  60         void __iomem    *pmecc_index_of;
  61
  62         /* data for pmecc computation */
  63         int16_t *pmecc_smu;
  64         int16_t *pmecc_partial_syn;
  65         int16_t *pmecc_si;
  66         int16_t *pmecc_lmu; /* polynomal order */
  67         int     *pmecc_mu;
  68         int     *pmecc_dmu;
  69         int     *pmecc_delta;
  70 };
  71
  72 static struct atmel_nand_host pmecc_host;
  73 static struct nand_ecclayout atmel_pmecc_oobinfo;
  74
  75 /*
  76  * Return number of ecc bytes per sector according to sector size and
  77  * correction capability
  78  *
  79  * Following table shows what at91 PMECC supported:
  80  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  81  * =====================        ================        =================
  82  *                2-bits                 4-bytes                  4-bytes
  83  *                4-bits                 7-bytes                  7-bytes
  84  *                8-bits                13-bytes                 14-bytes
  85  *               12-bits                20-bytes                 21-bytes
  86  *               24-bits                39-bytes                 42-bytes
  87  *               32-bits                52-bytes                 56-bytes
  88  */
  89 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  90 {
  91         int m = 12 + sector_size / 512;
  92         return (m * cap + 7) / 8;
  93 }
  94
  95 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  96         int oobsize, int ecc_len)
  97 {
  98         int i;
  99
 100         layout->eccbytes = ecc_len;
 101
 102         /* ECC will occupy the last ecc_len bytes continuously */
 103         for (i = 0; i < ecc_len; i++)
 104                 layout->eccpos[i] = oobsize - ecc_len + i;
 105
 106         layout->oobfree[0].offset = 2;
 107         layout->oobfree[0].length =
 108                 oobsize - ecc_len - layout->oobfree[0].offset;
 109 }
 110
 111 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 112 {
 113         int table_size;
 114
 115         table_size = host->pmecc_sector_size == 512 ?
 116                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 117
 118         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 119         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 120                         table_size * sizeof(int16_t);
 121 }
 122
 123 static void pmecc_data_free(struct atmel_nand_host *host)
 124 {
 125         free(host->pmecc_partial_syn);
 126         free(host->pmecc_si);
 127         free(host->pmecc_lmu);
 128         free(host->pmecc_smu);
 129         free(host->pmecc_mu);
 130         free(host->pmecc_dmu);
 131         free(host->pmecc_delta);
 132 }
 133
 134 static int pmecc_data_alloc(struct atmel_nand_host *host)
 135 {
 136         const int cap = host->pmecc_corr_cap;
 137         int size;
 138
 139         size = (2 * cap + 1) * sizeof(int16_t);
 140         host->pmecc_partial_syn = malloc(size);
 141         host->pmecc_si = malloc(size);
 142         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 143         host->pmecc_smu = malloc((cap + 2) * size);
 144
 145         size = (cap + 1) * sizeof(int);
 146         host->pmecc_mu = malloc(size);
 147         host->pmecc_dmu = malloc(size);
 148         host->pmecc_delta = malloc(size);
 149
 150         if (host->pmecc_partial_syn &&
 151                         host->pmecc_si &&
 152                         host->pmecc_lmu &&
 153                         host->pmecc_smu &&
 154                         host->pmecc_mu &&
 155                         host->pmecc_dmu &&
 156                         host->pmecc_delta)
 157                 return 0;
 158
 159         /* error happened */
 160         pmecc_data_free(host);
 161         return -ENOMEM;
 162
 163 }
 164
 165 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 166 {
 167         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 168         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 169         int i;
 170         uint32_t value;
 171
 172         /* Fill odd syndromes */
 173         for (i = 0; i < host->pmecc_corr_cap; i++) {
 174                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 175                 if (i & 1)
 176                         value >>= 16;
 177                 value &= 0xffff;
 178                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 179         }
 180 }
 181
 182 static void pmecc_substitute(struct mtd_info *mtd)
 183 {
 184         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 185         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 186         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 187         int16_t __iomem *index_of = host->pmecc_index_of;
 188         int16_t *partial_syn = host->pmecc_partial_syn;
 189         const int cap = host->pmecc_corr_cap;
 190         int16_t *si;
 191         int i, j;
 192
 193         /* si[] is a table that holds the current syndrome value,
 194          * an element of that table belongs to the field
 195          */
 196         si = host->pmecc_si;
 197
 198         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 199
 200         /* Computation 2t syndromes based on S(x) */
 201         /* Odd syndromes */
 202         for (i = 1; i < 2 * cap; i += 2) {
 203                 for (j = 0; j < host->pmecc_degree; j++) {
 204                         if (partial_syn[i] & (0x1 << j))
 205                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 206                 }
 207         }
 208         /* Even syndrome = (Odd syndrome) ** 2 */
 209         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 210                 if (si[j] == 0) {
 211                         si[i] = 0;
 212                 } else {
 213                         int16_t tmp;
 214
 215                         tmp = readw(index_of + si[j]);
 216                         tmp = (tmp * 2) % host->pmecc_cw_len;
 217                         si[i] = readw(alpha_to + tmp);
 218                 }
 219         }
 220 }
 221
 222 /*
 223  * This function defines a Berlekamp iterative procedure for
 224  * finding the value of the error location polynomial.
 225  * The input is si[], initialize by pmecc_substitute().
 226  * The output is smu[][].
 227  *
 228  * This function is written according to chip datasheet Chapter:
 229  * Find the Error Location Polynomial Sigma(x) of Section:
 230  * Programmable Multibit ECC Control (PMECC).
 231  */
 232 static void pmecc_get_sigma(struct mtd_info *mtd)
 233 {
 234         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 235         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 236
 237         int16_t *lmu = host->pmecc_lmu;
 238         int16_t *si = host->pmecc_si;
 239         int *mu = host->pmecc_mu;
 240         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 241         int *delta = host->pmecc_delta; /* Delta order */
 242         int cw_len = host->pmecc_cw_len;
 243         const int16_t cap = host->pmecc_corr_cap;
 244         const int num = 2 * cap + 1;
 245         int16_t __iomem *index_of = host->pmecc_index_of;
 246         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 247         int i, j, k;
 248         uint32_t dmu_0_count, tmp;
 249         int16_t *smu = host->pmecc_smu;
 250
 251         /* index of largest delta */
 252         int ro;
 253         int largest;
 254         int diff;
 255
 256         /* Init the Sigma(x) */
 257         memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
 258
 259         dmu_0_count = 0;
 260
 261         /* First Row */
 262
 263         /* Mu */
 264         mu[0] = -1;
 265
 266         smu[0] = 1;
 267
 268         /* discrepancy set to 1 */
 269         dmu[0] = 1;
 270         /* polynom order set to 0 */
 271         lmu[0] = 0;
 272         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 273         delta[0] = -1;
 274
 275         /* Second Row */
 276
 277         /* Mu */
 278         mu[1] = 0;
 279         /* Sigma(x) set to 1 */
 280         smu[num] = 1;
 281
 282         /* discrepancy set to S1 */
 283         dmu[1] = si[1];
 284
 285         /* polynom order set to 0 */
 286         lmu[1] = 0;
 287
 288         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 289         delta[1] = 0;
 290
 291         for (i = 1; i <= cap; i++) {
 292                 mu[i + 1] = i << 1;
 293                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 294                 /* check if discrepancy is set to 0 */
 295                 if (dmu[i] == 0) {
 296                         dmu_0_count++;
 297
 298                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 299                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 300                                 tmp += 2;
 301                         else
 302                                 tmp += 1;
 303
 304                         if (dmu_0_count == tmp) {
 305                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 306                                         smu[(cap + 1) * num + j] =
 307                                                         smu[i * num + j];
 308
 309                                 lmu[cap + 1] = lmu[i];
 310                                 return;
 311                         }
 312
 313                         /* copy polynom */
 314                         for (j = 0; j <= lmu[i] >> 1; j++)
 315                                 smu[(i + 1) * num + j] = smu[i * num + j];
 316
 317                         /* copy previous polynom order to the next */
 318                         lmu[i + 1] = lmu[i];
 319                 } else {
 320                         ro = 0;
 321                         largest = -1;
 322                         /* find largest delta with dmu != 0 */
 323                         for (j = 0; j < i; j++) {
 324                                 if ((dmu[j]) && (delta[j] > largest)) {
 325                                         largest = delta[j];
 326                                         ro = j;
 327                                 }
 328                         }
 329
 330                         /* compute difference */
 331                         diff = (mu[i] - mu[ro]);
 332
 333                         /* Compute degree of the new smu polynomial */
 334                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 335                                 lmu[i + 1] = lmu[i];
 336                         else
 337                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 338
 339                         /* Init smu[i+1] with 0 */
 340                         for (k = 0; k < num; k++)
 341                                 smu[(i + 1) * num + k] = 0;
 342
 343                         /* Compute smu[i+1] */
 344                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 345                                 int16_t a, b, c;
 346
 347                                 if (!(smu[ro * num + k] && dmu[i]))
 348                                         continue;
 349                                 a = readw(index_of + dmu[i]);
 350                                 b = readw(index_of + dmu[ro]);
 351                                 c = readw(index_of + smu[ro * num + k]);
 352                                 tmp = a + (cw_len - b) + c;
 353                                 a = readw(alpha_to + tmp % cw_len);
 354                                 smu[(i + 1) * num + (k + diff)] = a;
 355                         }
 356
 357                         for (k = 0; k <= lmu[i] >> 1; k++)
 358                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 359                 }
 360
 361                 /* End Computing Sigma (Mu+1) and L(mu) */
 362                 /* In either case compute delta */
 363                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 364
 365                 /* Do not compute discrepancy for the last iteration */
 366                 if (i >= cap)
 367                         continue;
 368
 369                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 370                         tmp = 2 * (i - 1);
 371                         if (k == 0) {
 372                                 dmu[i + 1] = si[tmp + 3];
 373                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 374                                 int16_t a, b, c;
 375                                 a = readw(index_of +
 376                                                 smu[(i + 1) * num + k]);
 377                                 b = si[2 * (i - 1) + 3 - k];
 378                                 c = readw(index_of + b);
 379                                 tmp = a + c;
 380                                 tmp %= cw_len;
 381                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 382                                         dmu[i + 1];
 383                         }
 384                 }
 385         }
 386 }
 387
 388 static int pmecc_err_location(struct mtd_info *mtd)
 389 {
 390         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 391         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 392         const int cap = host->pmecc_corr_cap;
 393         const int num = 2 * cap + 1;
 394         int sector_size = host->pmecc_sector_size;
 395         int err_nbr = 0;        /* number of error */
 396         int roots_nbr;          /* number of roots */
 397         int i;
 398         uint32_t val;
 399         int16_t *smu = host->pmecc_smu;
 400         int timeout = PMECC_MAX_TIMEOUT_US;
 401
 402         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 403
 404         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 405                 pmecc_writel(host->pmerrloc, sigma[i],
 406                              smu[(cap + 1) * num + i]);
 407                 err_nbr++;
 408         }
 409
 410         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 411         if (sector_size == 1024)
 412                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 413
 414         pmecc_writel(host->pmerrloc, elcfg, val);
 415         pmecc_writel(host->pmerrloc, elen,
 416                      sector_size * 8 + host->pmecc_degree * cap);
 417
 418         while (--timeout) {
 419                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 420                         break;
 421                 WATCHDOG_RESET();
 422                 udelay(1);
 423         }
 424
 425         if (!timeout) {
 426                 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
 427                 return -1;
 428         }
 429
 430         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 431                         >> 8;
 432         /* Number of roots == degree of smu hence <= cap */
 433         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 434                 return err_nbr - 1;
 435
 436         /* Number of roots does not match the degree of smu
 437          * unable to correct error */
 438         return -1;
 439 }
 440
 441 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 442                 int sector_num, int extra_bytes, int err_nbr)
 443 {
 444         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 445         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 446         int i = 0;
 447         int byte_pos, bit_pos, sector_size, pos;
 448         uint32_t tmp;
 449         uint8_t err_byte;
 450
 451         sector_size = host->pmecc_sector_size;
 452
 453         while (err_nbr) {
 454                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 455                 byte_pos = tmp / 8;
 456                 bit_pos  = tmp % 8;
 457
 458                 if (byte_pos >= (sector_size + extra_bytes))
 459                         BUG();  /* should never happen */
 460
 461                 if (byte_pos < sector_size) {
 462                         err_byte = *(buf + byte_pos);
 463                         *(buf + byte_pos) ^= (1 << bit_pos);
 464
 465                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 466                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 467                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 468                 } else {
 469                         /* Bit flip in OOB area */
 470                         tmp = sector_num * host->pmecc_bytes_per_sector
 471                                         + (byte_pos - sector_size);
 472                         err_byte = ecc[tmp];
 473                         ecc[tmp] ^= (1 << bit_pos);
 474
 475                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 476                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 477                                 pos, bit_pos, err_byte, ecc[tmp]);
 478                 }
 479
 480                 i++;
 481                 err_nbr--;
 482         }
 483
 484         return;
 485 }
 486
 487 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 488         u8 *ecc)
 489 {
 490         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 491         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 492         int i, err_nbr, eccbytes;
 493         uint8_t *buf_pos;
 494
 495         /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
 496         if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
 497                 goto normal_check;
 498
 499         eccbytes = nand_chip->ecc.bytes;
 500         for (i = 0; i < eccbytes; i++)
 501                 if (ecc[i] != 0xff)
 502                         goto normal_check;
 503         /* Erased page, return OK */
 504         return 0;
 505
 506 normal_check:
 507         for (i = 0; i < host->pmecc_sector_number; i++) {
 508                 err_nbr = 0;
 509                 if (pmecc_stat & 0x1) {
 510                         buf_pos = buf + i * host->pmecc_sector_size;
 511
 512                         pmecc_gen_syndrome(mtd, i);
 513                         pmecc_substitute(mtd);
 514                         pmecc_get_sigma(mtd);
 515
 516                         err_nbr = pmecc_err_location(mtd);
 517                         if (err_nbr == -1) {
 518                                 dev_err(host->dev, "PMECC: Too many errors\n");
 519                                 mtd->ecc_stats.failed++;
 520                                 return -EBADMSG;
 521                         } else {
 522                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 523                                         host->pmecc_bytes_per_sector, err_nbr);
 524                                 mtd->ecc_stats.corrected += err_nbr;
 525                         }
 526                 }
 527                 pmecc_stat >>= 1;
 528         }
 529
 530         return 0;
 531 }
 532
 533 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 534         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 535 {
 536         struct atmel_nand_host *host = nand_get_controller_data(chip);
 537         int eccsize = chip->ecc.size;
 538         uint8_t *oob = chip->oob_poi;
 539         uint32_t *eccpos = chip->ecc.layout->eccpos;
 540         uint32_t stat;
 541         int timeout = PMECC_MAX_TIMEOUT_US;
 542
 543         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 544         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 545         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 546                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 547
 548         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 549         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 550
 551         chip->read_buf(mtd, buf, eccsize);
 552         chip->read_buf(mtd, oob, mtd->oobsize);
 553
 554         while (--timeout) {
 555                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 556                         break;
 557                 WATCHDOG_RESET();
 558                 udelay(1);
 559         }
 560
 561         if (!timeout) {
 562                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
 563                 return -1;
 564         }
 565
 566         stat = pmecc_readl(host->pmecc, isr);
 567         if (stat != 0)
 568                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 569                         return -EBADMSG;
 570
 571         return 0;
 572 }
 573
 574 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 575                 struct nand_chip *chip, const uint8_t *buf,
 576                 int oob_required, int page)
 577 {
 578         struct atmel_nand_host *host = nand_get_controller_data(chip);
 579         uint32_t *eccpos = chip->ecc.layout->eccpos;
 580         int i, j;
 581         int timeout = PMECC_MAX_TIMEOUT_US;
 582
 583         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 584         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 585
 586         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 587                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 588
 589         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 590         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 591
 592         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 593
 594         while (--timeout) {
 595                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 596                         break;
 597                 WATCHDOG_RESET();
 598                 udelay(1);
 599         }
 600
 601         if (!timeout) {
 602                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 603                 goto out;
 604         }
 605
 606         for (i = 0; i < host->pmecc_sector_number; i++) {
 607                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 608                         int pos;
 609
 610                         pos = i * host->pmecc_bytes_per_sector + j;
 611                         chip->oob_poi[eccpos[pos]] =
 612                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 613                 }
 614         }
 615         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 616 out:
 617         return 0;
 618 }
 619
 620 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 621 {
 622         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 623         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 624         uint32_t val = 0;
 625         struct nand_ecclayout *ecc_layout;
 626
 627         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 628         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 629
 630         switch (host->pmecc_corr_cap) {
 631         case 2:
 632                 val = PMECC_CFG_BCH_ERR2;
 633                 break;
 634         case 4:
 635                 val = PMECC_CFG_BCH_ERR4;
 636                 break;
 637         case 8:
 638                 val = PMECC_CFG_BCH_ERR8;
 639                 break;
 640         case 12:
 641                 val = PMECC_CFG_BCH_ERR12;
 642                 break;
 643         case 24:
 644                 val = PMECC_CFG_BCH_ERR24;
 645                 break;
 646         case 32:
 647                 val = PMECC_CFG_BCH_ERR32;
 648                 break;
 649         }
 650
 651         if (host->pmecc_sector_size == 512)
 652                 val |= PMECC_CFG_SECTOR512;
 653         else if (host->pmecc_sector_size == 1024)
 654                 val |= PMECC_CFG_SECTOR1024;
 655
 656         switch (host->pmecc_sector_number) {
 657         case 1:
 658                 val |= PMECC_CFG_PAGE_1SECTOR;
 659                 break;
 660         case 2:
 661                 val |= PMECC_CFG_PAGE_2SECTORS;
 662                 break;
 663         case 4:
 664                 val |= PMECC_CFG_PAGE_4SECTORS;
 665                 break;
 666         case 8:
 667                 val |= PMECC_CFG_PAGE_8SECTORS;
 668                 break;
 669         }
 670
 671         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 672                 | PMECC_CFG_AUTO_DISABLE);
 673         pmecc_writel(host->pmecc, cfg, val);
 674
 675         ecc_layout = nand_chip->ecc.layout;
 676         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 677         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 678         pmecc_writel(host->pmecc, eaddr,
 679                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 680         /* See datasheet about PMECC Clock Control Register */
 681         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 682         pmecc_writel(host->pmecc, idr, 0xff);
 683         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 684 }
 685
 686 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 687 /*
 688  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 689  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 690  *                    ONFI ECC parameters.
 691  * @host: point to an atmel_nand_host structure.
 692  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 693  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 694  * @chip: point to an nand_chip structure.
 695  * @cap: store the ONFI ECC correct bits capbility
 696  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 697  *
 698  * Return 0 if success. otherwise return the error code.
 699  */
 700 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 701                 struct nand_chip *chip,
 702                 int *cap, int *sector_size)
 703 {
 704         /* Get ECC requirement from ONFI parameters */
 705         *cap = *sector_size = 0;
 706         if (chip->onfi_version) {
 707                 *cap = chip->ecc_strength_ds;
 708                 *sector_size = chip->ecc_step_ds;
 709                 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
 710                          *cap, *sector_size);
 711         }
 712
 713         if (*cap == 0 && *sector_size == 0) {
 714                 /* Non-ONFI compliant */
 715                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
 716                 *cap = 2;
 717                 *sector_size = 512;
 718         }
 719
 720         /* If head file doesn't specify then use the one in ONFI parameters */
 721         if (host->pmecc_corr_cap == 0) {
 722                 /* use the most fitable ecc bits (the near bigger one ) */
 723                 if (*cap <= 2)
 724                         host->pmecc_corr_cap = 2;
 725                 else if (*cap <= 4)
 726                         host->pmecc_corr_cap = 4;
 727                 else if (*cap <= 8)
 728                         host->pmecc_corr_cap = 8;
 729                 else if (*cap <= 12)
 730                         host->pmecc_corr_cap = 12;
 731                 else if (*cap <= 24)
 732                         host->pmecc_corr_cap = 24;
 733                 else
 734 #ifdef CONFIG_SAMA5D2
 735                         host->pmecc_corr_cap = 32;
 736 #else
 737                         host->pmecc_corr_cap = 24;
 738 #endif
 739         }
 740         if (host->pmecc_sector_size == 0) {
 741                 /* use the most fitable sector size (the near smaller one ) */
 742                 if (*sector_size >= 1024)
 743                         host->pmecc_sector_size = 1024;
 744                 else if (*sector_size >= 512)
 745                         host->pmecc_sector_size = 512;
 746                 else
 747                         return -EINVAL;
 748         }
 749         return 0;
 750 }
 751 #endif
 752
 753 #if defined(NO_GALOIS_TABLE_IN_ROM)
 754 static uint16_t *pmecc_galois_table;
 755 static inline int deg(unsigned int poly)
 756 {
 757         /* polynomial degree is the most-significant bit index */
 758         return fls(poly) - 1;
 759 }
 760
 761 static int build_gf_tables(int mm, unsigned int poly,
 762                            int16_t *index_of, int16_t *alpha_to)
 763 {
 764         unsigned int i, x = 1;
 765         const unsigned int k = 1 << deg(poly);
 766         unsigned int nn = (1 << mm) - 1;
 767
 768         /* primitive polynomial must be of degree m */
 769         if (k != (1u << mm))
 770                 return -EINVAL;
 771
 772         for (i = 0; i < nn; i++) {
 773                 alpha_to[i] = x;
 774                 index_of[x] = i;
 775                 if (i && (x == 1))
 776                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
 777                         return -EINVAL;
 778                 x <<= 1;
 779                 if (x & k)
 780                         x ^= poly;
 781         }
 782
 783         alpha_to[nn] = 1;
 784         index_of[0] = 0;
 785
 786         return 0;
 787 }
 788
 789 static uint16_t *create_lookup_table(int sector_size)
 790 {
 791         int degree = (sector_size == 512) ?
 792                         PMECC_GF_DIMENSION_13 :
 793                         PMECC_GF_DIMENSION_14;
 794         unsigned int poly = (sector_size == 512) ?
 795                         PMECC_GF_13_PRIMITIVE_POLY :
 796                         PMECC_GF_14_PRIMITIVE_POLY;
 797         int table_size = (sector_size == 512) ?
 798                         PMECC_INDEX_TABLE_SIZE_512 :
 799                         PMECC_INDEX_TABLE_SIZE_1024;
 800
 801         int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
 802         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
 803                 return NULL;
 804
 805         return (uint16_t *)addr;
 806 }
 807 #endif
 808
 809 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 810                 struct mtd_info *mtd)
 811 {
 812         struct atmel_nand_host *host;
 813         int cap, sector_size;
 814
 815         host = &pmecc_host;
 816         nand_set_controller_data(nand, host);
 817
 818         nand->ecc.mode = NAND_ECC_HW;
 819         nand->ecc.calculate = NULL;
 820         nand->ecc.correct = NULL;
 821         nand->ecc.hwctl = NULL;
 822
 823 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 824         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 825
 826 #ifdef CONFIG_PMECC_CAP
 827         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 828 #endif
 829 #ifdef CONFIG_PMECC_SECTOR_SIZE
 830         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 831 #endif
 832         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 833          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 834          * from ONFI.
 835          */
 836         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 837                 dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
 838                         cap, sector_size);
 839                 return -EINVAL;
 840         }
 841
 842         if (cap > host->pmecc_corr_cap)
 843                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 844                                 host->pmecc_corr_cap, cap);
 845         if (sector_size < host->pmecc_sector_size)
 846                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 847                                 host->pmecc_sector_size, sector_size);
 848 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 849         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 850         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 851 #endif
 852
 853         cap = host->pmecc_corr_cap;
 854         sector_size = host->pmecc_sector_size;
 855
 856         /* TODO: need check whether cap & sector_size is validate */
 857 #if defined(NO_GALOIS_TABLE_IN_ROM)
 858         /*
 859          * As pmecc_rom_base is the begin of the gallois field table, So the
 860          * index offset just set as 0.
 861          */
 862         host->pmecc_index_table_offset = 0;
 863 #else
 864         if (host->pmecc_sector_size == 512)
 865                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 866         else
 867                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 868 #endif
 869
 870         pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
 871                  cap, sector_size);
 872
 873         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 874         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 875                         ATMEL_BASE_PMERRLOC;
 876 #if defined(NO_GALOIS_TABLE_IN_ROM)
 877         pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
 878         if (!pmecc_galois_table) {
 879                 dev_err(host->dev, "out of memory\n");
 880                 return -ENOMEM;
 881         }
 882
 883         host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
 884 #else
 885         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 886 #endif
 887
 888         /* ECC is calculated for the whole page (1 step) */
 889         nand->ecc.size = mtd->writesize;
 890
 891         /* set ECC page size and oob layout */
 892         switch (mtd->writesize) {
 893         case 2048:
 894         case 4096:
 895         case 8192:
 896                 host->pmecc_degree = (sector_size == 512) ?
 897                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 898                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 899                 host->pmecc_sector_number = mtd->writesize / sector_size;
 900                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 901                         cap, sector_size);
 902                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 903                 host->pmecc_index_of = host->pmecc_rom_base +
 904                         host->pmecc_index_table_offset;
 905
 906                 nand->ecc.steps = 1;
 907                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 908                                        host->pmecc_sector_number;
 909
 910                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 911                         dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
 912                                         MTD_MAX_ECCPOS_ENTRIES_LARGE);
 913                         return -EINVAL;
 914                 }
 915
 916                 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
 917                         dev_err(host->dev, "No room for ECC bytes\n");
 918                         return -EINVAL;
 919                 }
 920                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 921                                         mtd->oobsize,
 922                                         nand->ecc.bytes);
 923                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 924                 break;
 925         case 512:
 926         case 1024:
 927                 /* TODO */
 928                 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
 929         default:
 930                 /* page size not handled by HW ECC */
 931                 /* switching back to soft ECC */
 932                 nand->ecc.mode = NAND_ECC_SOFT;
 933                 nand->ecc.read_page = NULL;
 934                 nand->ecc.postpad = 0;
 935                 nand->ecc.prepad = 0;
 936                 nand->ecc.bytes = 0;
 937                 return 0;
 938         }
 939
 940         /* Allocate data for PMECC computation */
 941         if (pmecc_data_alloc(host)) {
 942                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
 943                 return -ENOMEM;
 944         }
 945
 946         nand->options |= NAND_NO_SUBPAGE_WRITE;
 947         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 948         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 949         nand->ecc.strength = cap;
 950
 951         /* Check the PMECC ip version */
 952         host->pmecc_version = pmecc_readl(host->pmerrloc, version);
 953         dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
 954
 955         atmel_pmecc_core_init(mtd);
 956
 957         return 0;
 958 }
 959
 960 #else
 961
 962 /* oob layout for large page size
 963  * bad block info is on bytes 0 and 1
 964  * the bytes have to be consecutives to avoid
 965  * several NAND_CMD_RNDOUT during read
 966  */
 967 static struct nand_ecclayout atmel_oobinfo_large = {
 968         .eccbytes = 4,
 969         .eccpos = {60, 61, 62, 63},
 970         .oobfree = {
 971                 {2, 58}
 972         },
 973 };
 974
 975 /* oob layout for small page size
 976  * bad block info is on bytes 4 and 5
 977  * the bytes have to be consecutives to avoid
 978  * several NAND_CMD_RNDOUT during read
 979  */
 980 static struct nand_ecclayout atmel_oobinfo_small = {
 981         .eccbytes = 4,
 982         .eccpos = {0, 1, 2, 3},
 983         .oobfree = {
 984                 {6, 10}
 985         },
 986 };
 987
 988 /*
 989  * Calculate HW ECC
 990  *
 991  * function called after a write
 992  *
 993  * mtd:        MTD block structure
 994  * dat:        raw data (unused)
 995  * ecc_code:   buffer for ECC
 996  */
 997 static int atmel_nand_calculate(struct mtd_info *mtd,
 998                 const u_char *dat, unsigned char *ecc_code)
 999 {
1000         unsigned int ecc_value;
1001
1002         /* get the first 2 ECC bytes */
1003         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1004
1005         ecc_code[0] = ecc_value & 0xFF;
1006         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1007
1008         /* get the last 2 ECC bytes */
1009         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1010
1011         ecc_code[2] = ecc_value & 0xFF;
1012         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1013
1014         return 0;
1015 }
1016
1017 /*
1018  * HW ECC read page function
1019  *
1020  * mtd:        mtd info structure
1021  * chip:       nand chip info structure
1022  * buf:        buffer to store read data
1023  * oob_required:    caller expects OOB data read to chip->oob_poi
1024  */
1025 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1026                                 uint8_t *buf, int oob_required, int page)
1027 {
1028         int eccsize = chip->ecc.size;
1029         int eccbytes = chip->ecc.bytes;
1030         uint32_t *eccpos = chip->ecc.layout->eccpos;
1031         uint8_t *p = buf;
1032         uint8_t *oob = chip->oob_poi;
1033         uint8_t *ecc_pos;
1034         int stat;
1035
1036         /* read the page */
1037         chip->read_buf(mtd, p, eccsize);
1038
1039         /* move to ECC position if needed */
1040         if (eccpos[0] != 0) {
1041                 /* This only works on large pages
1042                  * because the ECC controller waits for
1043                  * NAND_CMD_RNDOUTSTART after the
1044                  * NAND_CMD_RNDOUT.
1045                  * anyway, for small pages, the eccpos[0] == 0
1046                  */
1047                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1048                                 mtd->writesize + eccpos[0], -1);
1049         }
1050
1051         /* the ECC controller needs to read the ECC just after the data */
1052         ecc_pos = oob + eccpos[0];
1053         chip->read_buf(mtd, ecc_pos, eccbytes);
1054
1055         /* check if there's an error */
1056         stat = chip->ecc.correct(mtd, p, oob, NULL);
1057
1058         if (stat < 0)
1059                 mtd->ecc_stats.failed++;
1060         else
1061                 mtd->ecc_stats.corrected += stat;
1062
1063         /* get back to oob start (end of page) */
1064         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1065
1066         /* read the oob */
1067         chip->read_buf(mtd, oob, mtd->oobsize);
1068
1069         return 0;
1070 }
1071
1072 /*
1073  * HW ECC Correction
1074  *
1075  * function called after a read
1076  *
1077  * mtd:        MTD block structure
1078  * dat:        raw data read from the chip
1079  * read_ecc:   ECC from the chip (unused)
1080  * isnull:     unused
1081  *
1082  * Detect and correct a 1 bit error for a page
1083  */
1084 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1085                 u_char *read_ecc, u_char *isnull)
1086 {
1087         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1088         unsigned int ecc_status;
1089         unsigned int ecc_word, ecc_bit;
1090
1091         /* get the status from the Status Register */
1092         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1093
1094         /* if there's no error */
1095         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1096                 return 0;
1097
1098         /* get error bit offset (4 bits) */
1099         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1100         /* get word address (12 bits) */
1101         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1102         ecc_word >>= 4;
1103
1104         /* if there are multiple errors */
1105         if (ecc_status & ATMEL_ECC_MULERR) {
1106                 /* check if it is a freshly erased block
1107                  * (filled with 0xff) */
1108                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1109                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1110                         /* the block has just been erased, return OK */
1111                         return 0;
1112                 }
1113                 /* it doesn't seems to be a freshly
1114                  * erased block.
1115                  * We can't correct so many errors */
1116                 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1117                                 " Unable to correct.\n");
1118                 return -EBADMSG;
1119         }
1120
1121         /* if there's a single bit error : we can correct it */
1122         if (ecc_status & ATMEL_ECC_ECCERR) {
1123                 /* there's nothing much to do here.
1124                  * the bit error is on the ECC itself.
1125                  */
1126                 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1127                                 " Nothing to correct\n");
1128                 return 0;
1129         }
1130
1131         dev_warn(host->dev, "atmel_nand : one bit error on data."
1132                         " (word offset in the page :"
1133                         " 0x%x bit offset : 0x%x)\n",
1134                         ecc_word, ecc_bit);
1135         /* correct the error */
1136         if (nand_chip->options & NAND_BUSWIDTH_16) {
1137                 /* 16 bits words */
1138                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1139         } else {
1140                 /* 8 bits words */
1141                 dat[ecc_word] ^= (1 << ecc_bit);
1142         }
1143         dev_warn(host->dev, "atmel_nand : error corrected\n");
1144         return 1;
1145 }
1146
1147 /*
1148  * Enable HW ECC : unused on most chips
1149  */
1150 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1151 {
1152 }
1153
1154 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1155 {
1156         nand->ecc.mode = NAND_ECC_HW;
1157         nand->ecc.calculate = atmel_nand_calculate;
1158         nand->ecc.correct = atmel_nand_correct;
1159         nand->ecc.hwctl = atmel_nand_hwctl;
1160         nand->ecc.read_page = atmel_nand_read_page;
1161         nand->ecc.bytes = 4;
1162         nand->ecc.strength = 4;
1163
1164         if (nand->ecc.mode == NAND_ECC_HW) {
1165                 /* ECC is calculated for the whole page (1 step) */
1166                 nand->ecc.size = mtd->writesize;
1167
1168                 /* set ECC page size and oob layout */
1169                 switch (mtd->writesize) {
1170                 case 512:
1171                         nand->ecc.layout = &atmel_oobinfo_small;
1172                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1173                                         ATMEL_ECC_PAGESIZE_528);
1174                         break;
1175                 case 1024:
1176                         nand->ecc.layout = &atmel_oobinfo_large;
1177                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1178                                         ATMEL_ECC_PAGESIZE_1056);
1179                         break;
1180                 case 2048:
1181                         nand->ecc.layout = &atmel_oobinfo_large;
1182                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1183                                         ATMEL_ECC_PAGESIZE_2112);
1184                         break;
1185                 case 4096:
1186                         nand->ecc.layout = &atmel_oobinfo_large;
1187                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1188                                         ATMEL_ECC_PAGESIZE_4224);
1189                         break;
1190                 default:
1191                         /* page size not handled by HW ECC */
1192                         /* switching back to soft ECC */
1193                         nand->ecc.mode = NAND_ECC_SOFT;
1194                         nand->ecc.calculate = NULL;
1195                         nand->ecc.correct = NULL;
1196                         nand->ecc.hwctl = NULL;
1197                         nand->ecc.read_page = NULL;
1198                         nand->ecc.postpad = 0;
1199                         nand->ecc.prepad = 0;
1200                         nand->ecc.bytes = 0;
1201                         break;
1202                 }
1203         }
1204
1205         return 0;
1206 }
1207
1208 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1209
1210 #endif /* CONFIG_ATMEL_NAND_HWECC */
1211
1212 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1213                                          int cmd, unsigned int ctrl)
1214 {
1215         struct nand_chip *this = mtd_to_nand(mtd);
1216
1217         if (ctrl & NAND_CTRL_CHANGE) {
1218                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1219                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1220                              | CONFIG_SYS_NAND_MASK_CLE);
1221
1222                 if (ctrl & NAND_CLE)
1223                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1224                 if (ctrl & NAND_ALE)
1225                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1226
1227 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1228                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1229                                     !(ctrl & NAND_NCE));
1230 #endif
1231                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1232         }
1233
1234         if (cmd != NAND_CMD_NONE)
1235                 writeb(cmd, this->IO_ADDR_W);
1236 }
1237
1238 #ifdef CONFIG_SYS_NAND_READY_PIN
1239 static int at91_nand_ready(struct mtd_info *mtd)
1240 {
1241         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1242 }
1243 #endif
1244
1245 #ifdef CONFIG_SPL_BUILD
1246 /* The following code is for SPL */
1247 static struct mtd_info *mtd;
1248 static struct nand_chip nand_chip;
1249
1250 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1251 {
1252         struct nand_chip *this = mtd_to_nand(mtd);
1253         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1254         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1255                         unsigned int ctrl) = this->cmd_ctrl;
1256
1257         while (!this->dev_ready(mtd))
1258                 ;
1259
1260         if (cmd == NAND_CMD_READOOB) {
1261                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1262                 cmd = NAND_CMD_READ0;
1263         }
1264
1265         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1266
1267         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1268                 offs >>= 1;
1269
1270         hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1271         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1272         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1273         hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1274 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1275         hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1276 #endif
1277         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1278
1279         hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1280         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1281
1282         while (!this->dev_ready(mtd))
1283                 ;
1284
1285         return 0;
1286 }
1287
1288 static int nand_is_bad_block(int block)
1289 {
1290         struct nand_chip *this = mtd_to_nand(mtd);
1291
1292         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1293
1294         if (this->options & NAND_BUSWIDTH_16) {
1295                 if (readw(this->IO_ADDR_R) != 0xffff)
1296                         return 1;
1297         } else {
1298                 if (readb(this->IO_ADDR_R) != 0xff)
1299                         return 1;
1300         }
1301
1302         return 0;
1303 }
1304
1305 #ifdef CONFIG_SPL_NAND_ECC
1306 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1307 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1308                   CONFIG_SYS_NAND_ECCSIZE)
1309 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1310
1311 static int nand_read_page(int block, int page, void *dst)
1312 {
1313         struct nand_chip *this = mtd_to_nand(mtd);
1314         u_char ecc_calc[ECCTOTAL];
1315         u_char ecc_code[ECCTOTAL];
1316         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1317         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1318         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1319         int eccsteps = ECCSTEPS;
1320         int i;
1321         uint8_t *p = dst;
1322         nand_command(block, page, 0, NAND_CMD_READ0);
1323
1324         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1325                 if (this->ecc.mode != NAND_ECC_SOFT)
1326                         this->ecc.hwctl(mtd, NAND_ECC_READ);
1327                 this->read_buf(mtd, p, eccsize);
1328                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1329         }
1330         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1331
1332         for (i = 0; i < ECCTOTAL; i++)
1333                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1334
1335         eccsteps = ECCSTEPS;
1336         p = dst;
1337
1338         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1339                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1340
1341         return 0;
1342 }
1343
1344 int spl_nand_erase_one(int block, int page)
1345 {
1346         struct nand_chip *this = mtd_to_nand(mtd);
1347         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1348                         unsigned int ctrl) = this->cmd_ctrl;
1349         int page_addr;
1350
1351         if (nand_chip.select_chip)
1352                 nand_chip.select_chip(mtd, 0);
1353
1354         page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1355         hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1356         /* Row address */
1357         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1358         hwctrl(mtd, ((page_addr >> 8) & 0xff),
1359                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1360 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1361         /* One more address cycle for devices > 128MiB */
1362         hwctrl(mtd, (page_addr >> 16) & 0x0f,
1363                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1364 #endif
1365         hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1366
1367         while (!this->dev_ready(mtd))
1368                 ;
1369
1370         nand_deselect();
1371
1372         return 0;
1373 }
1374 #else
1375 static int nand_read_page(int block, int page, void *dst)
1376 {
1377         struct nand_chip *this = mtd_to_nand(mtd);
1378
1379         nand_command(block, page, 0, NAND_CMD_READ0);
1380         atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1381
1382         return 0;
1383 }
1384 #endif /* CONFIG_SPL_NAND_ECC */
1385
1386 int at91_nand_wait_ready(struct mtd_info *mtd)
1387 {
1388         struct nand_chip *this = mtd_to_nand(mtd);
1389
1390         udelay(this->chip_delay);
1391
1392         return 1;
1393 }
1394
1395 int board_nand_init(struct nand_chip *nand)
1396 {
1397         int ret = 0;
1398
1399         nand->ecc.mode = NAND_ECC_SOFT;
1400 #ifdef CONFIG_SYS_NAND_DBW_16
1401         nand->options = NAND_BUSWIDTH_16;
1402         nand->read_buf = nand_read_buf16;
1403 #else
1404         nand->read_buf = nand_read_buf;
1405 #endif
1406         nand->cmd_ctrl = at91_nand_hwcontrol;
1407 #ifdef CONFIG_SYS_NAND_READY_PIN
1408         nand->dev_ready = at91_nand_ready;
1409 #else
1410         nand->dev_ready = at91_nand_wait_ready;
1411 #endif
1412         nand->chip_delay = 20;
1413 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1414         nand->bbt_options |= NAND_BBT_USE_FLASH;
1415 #endif
1416
1417 #ifdef CONFIG_ATMEL_NAND_HWECC
1418 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1419         ret = atmel_pmecc_nand_init_params(nand, mtd);
1420 #endif
1421 #endif
1422
1423         return ret;
1424 }
1425
1426 void nand_init(void)
1427 {
1428         mtd = nand_to_mtd(&nand_chip);
1429         mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1430         mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1431         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1432         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1433         board_nand_init(&nand_chip);
1434
1435 #ifdef CONFIG_SPL_NAND_ECC
1436         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1437                 nand_chip.ecc.calculate = nand_calculate_ecc;
1438                 nand_chip.ecc.correct = nand_correct_data;
1439         }
1440 #endif
1441
1442         if (nand_chip.select_chip)
1443                 nand_chip.select_chip(mtd, 0);
1444 }
1445
1446 void nand_deselect(void)
1447 {
1448         if (nand_chip.select_chip)
1449                 nand_chip.select_chip(mtd, -1);
1450 }
1451
1452 #include "nand_spl_loaders.c"
1453
1454 #else
1455
1456 #ifndef CONFIG_SYS_NAND_BASE_LIST
1457 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1458 #endif
1459 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1460 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1461
1462 int atmel_nand_chip_init(int devnum, ulong base_addr)
1463 {
1464         int ret;
1465         struct nand_chip *nand = &nand_chip[devnum];
1466         struct mtd_info *mtd = nand_to_mtd(nand);
1467
1468         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1469
1470 #ifdef CONFIG_NAND_ECC_BCH
1471         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1472 #else
1473         nand->ecc.mode = NAND_ECC_SOFT;
1474 #endif
1475 #ifdef CONFIG_SYS_NAND_DBW_16
1476         nand->options = NAND_BUSWIDTH_16;
1477 #endif
1478         nand->cmd_ctrl = at91_nand_hwcontrol;
1479 #ifdef CONFIG_SYS_NAND_READY_PIN
1480         nand->dev_ready = at91_nand_ready;
1481 #endif
1482         nand->chip_delay = 75;
1483 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1484         nand->bbt_options |= NAND_BBT_USE_FLASH;
1485 #endif
1486
1487         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1488         if (ret)
1489                 return ret;
1490
1491 #ifdef CONFIG_ATMEL_NAND_HWECC
1492 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1493         ret = atmel_pmecc_nand_init_params(nand, mtd);
1494 #else
1495         ret = atmel_hwecc_nand_init_param(nand, mtd);
1496 #endif
1497         if (ret)
1498                 return ret;
1499 #endif
1500
1501         ret = nand_scan_tail(mtd);
1502         if (!ret)
1503                 nand_register(devnum, mtd);
1504
1505         return ret;
1506 }
1507
1508 void board_nand_init(void)
1509 {
1510         int i;
1511         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1512                 if (atmel_nand_chip_init(i, base_addr[i]))
1513                         dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1514                                 i);
1515 }
1516 #endif /* CONFIG_SPL_BUILD */