drivers/mtd/nand/raw/atmel_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   8  *
   9  * Add Programmable Multibit ECC support for various AT91 SoC
  10  *     (C) Copyright 2012 ATMEL, Hong Xu
  11  */
  12
  13 #include <common.h>
  14 #include <log.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <linux/bug.h>
  20
  21 #include <malloc.h>
  22 #include <nand.h>
  23 #include <watchdog.h>
  24 #include <linux/mtd/nand_ecc.h>
  25
  26 #ifdef CONFIG_ATMEL_NAND_HWECC
  27
  28 /* Register access macros */
  29 #define ecc_readl(add, reg)                             \
  30         readl(add + ATMEL_ECC_##reg)
  31 #define ecc_writel(add, reg, value)                     \
  32         writel((value), add + ATMEL_ECC_##reg)
  33
  34 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  35
  36 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  37
  38 #ifdef CONFIG_SPL_BUILD
  39 #undef CONFIG_SYS_NAND_ONFI_DETECTION
  40 #endif
  41
  42 struct atmel_nand_host {
  43         struct pmecc_regs __iomem *pmecc;
  44         struct pmecc_errloc_regs __iomem *pmerrloc;
  45         void __iomem            *pmecc_rom_base;
  46
  47         u8              pmecc_corr_cap;
  48         u16             pmecc_sector_size;
  49         u32             pmecc_index_table_offset;
  50         u32             pmecc_version;
  51
  52         int             pmecc_bytes_per_sector;
  53         int             pmecc_sector_number;
  54         int             pmecc_degree;   /* Degree of remainders */
  55         int             pmecc_cw_len;   /* Length of codeword */
  56
  57         /* lookup table for alpha_to and index_of */
  58         void __iomem    *pmecc_alpha_to;
  59         void __iomem    *pmecc_index_of;
  60
  61         /* data for pmecc computation */
  62         int16_t *pmecc_smu;
  63         int16_t *pmecc_partial_syn;
  64         int16_t *pmecc_si;
  65         int16_t *pmecc_lmu; /* polynomal order */
  66         int     *pmecc_mu;
  67         int     *pmecc_dmu;
  68         int     *pmecc_delta;
  69 };
  70
  71 static struct atmel_nand_host pmecc_host;
  72 static struct nand_ecclayout atmel_pmecc_oobinfo;
  73
  74 /*
  75  * Return number of ecc bytes per sector according to sector size and
  76  * correction capability
  77  *
  78  * Following table shows what at91 PMECC supported:
  79  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  80  * =====================        ================        =================
  81  *                2-bits                 4-bytes                  4-bytes
  82  *                4-bits                 7-bytes                  7-bytes
  83  *                8-bits                13-bytes                 14-bytes
  84  *               12-bits                20-bytes                 21-bytes
  85  *               24-bits                39-bytes                 42-bytes
  86  *               32-bits                52-bytes                 56-bytes
  87  */
  88 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  89 {
  90         int m = 12 + sector_size / 512;
  91         return (m * cap + 7) / 8;
  92 }
  93
  94 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  95         int oobsize, int ecc_len)
  96 {
  97         int i;
  98
  99         layout->eccbytes = ecc_len;
 100
 101         /* ECC will occupy the last ecc_len bytes continuously */
 102         for (i = 0; i < ecc_len; i++)
 103                 layout->eccpos[i] = oobsize - ecc_len + i;
 104
 105         layout->oobfree[0].offset = 2;
 106         layout->oobfree[0].length =
 107                 oobsize - ecc_len - layout->oobfree[0].offset;
 108 }
 109
 110 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 111 {
 112         int table_size;
 113
 114         table_size = host->pmecc_sector_size == 512 ?
 115                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 116
 117         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 118         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 119                         table_size * sizeof(int16_t);
 120 }
 121
 122 static void pmecc_data_free(struct atmel_nand_host *host)
 123 {
 124         free(host->pmecc_partial_syn);
 125         free(host->pmecc_si);
 126         free(host->pmecc_lmu);
 127         free(host->pmecc_smu);
 128         free(host->pmecc_mu);
 129         free(host->pmecc_dmu);
 130         free(host->pmecc_delta);
 131 }
 132
 133 static int pmecc_data_alloc(struct atmel_nand_host *host)
 134 {
 135         const int cap = host->pmecc_corr_cap;
 136         int size;
 137
 138         size = (2 * cap + 1) * sizeof(int16_t);
 139         host->pmecc_partial_syn = malloc(size);
 140         host->pmecc_si = malloc(size);
 141         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 142         host->pmecc_smu = malloc((cap + 2) * size);
 143
 144         size = (cap + 1) * sizeof(int);
 145         host->pmecc_mu = malloc(size);
 146         host->pmecc_dmu = malloc(size);
 147         host->pmecc_delta = malloc(size);
 148
 149         if (host->pmecc_partial_syn &&
 150                         host->pmecc_si &&
 151                         host->pmecc_lmu &&
 152                         host->pmecc_smu &&
 153                         host->pmecc_mu &&
 154                         host->pmecc_dmu &&
 155                         host->pmecc_delta)
 156                 return 0;
 157
 158         /* error happened */
 159         pmecc_data_free(host);
 160         return -ENOMEM;
 161
 162 }
 163
 164 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 165 {
 166         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 167         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 168         int i;
 169         uint32_t value;
 170
 171         /* Fill odd syndromes */
 172         for (i = 0; i < host->pmecc_corr_cap; i++) {
 173                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 174                 if (i & 1)
 175                         value >>= 16;
 176                 value &= 0xffff;
 177                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 178         }
 179 }
 180
 181 static void pmecc_substitute(struct mtd_info *mtd)
 182 {
 183         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 184         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 185         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 186         int16_t __iomem *index_of = host->pmecc_index_of;
 187         int16_t *partial_syn = host->pmecc_partial_syn;
 188         const int cap = host->pmecc_corr_cap;
 189         int16_t *si;
 190         int i, j;
 191
 192         /* si[] is a table that holds the current syndrome value,
 193          * an element of that table belongs to the field
 194          */
 195         si = host->pmecc_si;
 196
 197         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 198
 199         /* Computation 2t syndromes based on S(x) */
 200         /* Odd syndromes */
 201         for (i = 1; i < 2 * cap; i += 2) {
 202                 for (j = 0; j < host->pmecc_degree; j++) {
 203                         if (partial_syn[i] & (0x1 << j))
 204                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 205                 }
 206         }
 207         /* Even syndrome = (Odd syndrome) ** 2 */
 208         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 209                 if (si[j] == 0) {
 210                         si[i] = 0;
 211                 } else {
 212                         int16_t tmp;
 213
 214                         tmp = readw(index_of + si[j]);
 215                         tmp = (tmp * 2) % host->pmecc_cw_len;
 216                         si[i] = readw(alpha_to + tmp);
 217                 }
 218         }
 219 }
 220
 221 /*
 222  * This function defines a Berlekamp iterative procedure for
 223  * finding the value of the error location polynomial.
 224  * The input is si[], initialize by pmecc_substitute().
 225  * The output is smu[][].
 226  *
 227  * This function is written according to chip datasheet Chapter:
 228  * Find the Error Location Polynomial Sigma(x) of Section:
 229  * Programmable Multibit ECC Control (PMECC).
 230  */
 231 static void pmecc_get_sigma(struct mtd_info *mtd)
 232 {
 233         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 234         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 235
 236         int16_t *lmu = host->pmecc_lmu;
 237         int16_t *si = host->pmecc_si;
 238         int *mu = host->pmecc_mu;
 239         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 240         int *delta = host->pmecc_delta; /* Delta order */
 241         int cw_len = host->pmecc_cw_len;
 242         const int16_t cap = host->pmecc_corr_cap;
 243         const int num = 2 * cap + 1;
 244         int16_t __iomem *index_of = host->pmecc_index_of;
 245         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 246         int i, j, k;
 247         uint32_t dmu_0_count, tmp;
 248         int16_t *smu = host->pmecc_smu;
 249
 250         /* index of largest delta */
 251         int ro;
 252         int largest;
 253         int diff;
 254
 255         /* Init the Sigma(x) */
 256         memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
 257
 258         dmu_0_count = 0;
 259
 260         /* First Row */
 261
 262         /* Mu */
 263         mu[0] = -1;
 264
 265         smu[0] = 1;
 266
 267         /* discrepancy set to 1 */
 268         dmu[0] = 1;
 269         /* polynom order set to 0 */
 270         lmu[0] = 0;
 271         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 272         delta[0] = -1;
 273
 274         /* Second Row */
 275
 276         /* Mu */
 277         mu[1] = 0;
 278         /* Sigma(x) set to 1 */
 279         smu[num] = 1;
 280
 281         /* discrepancy set to S1 */
 282         dmu[1] = si[1];
 283
 284         /* polynom order set to 0 */
 285         lmu[1] = 0;
 286
 287         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 288         delta[1] = 0;
 289
 290         for (i = 1; i <= cap; i++) {
 291                 mu[i + 1] = i << 1;
 292                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 293                 /* check if discrepancy is set to 0 */
 294                 if (dmu[i] == 0) {
 295                         dmu_0_count++;
 296
 297                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 298                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 299                                 tmp += 2;
 300                         else
 301                                 tmp += 1;
 302
 303                         if (dmu_0_count == tmp) {
 304                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 305                                         smu[(cap + 1) * num + j] =
 306                                                         smu[i * num + j];
 307
 308                                 lmu[cap + 1] = lmu[i];
 309                                 return;
 310                         }
 311
 312                         /* copy polynom */
 313                         for (j = 0; j <= lmu[i] >> 1; j++)
 314                                 smu[(i + 1) * num + j] = smu[i * num + j];
 315
 316                         /* copy previous polynom order to the next */
 317                         lmu[i + 1] = lmu[i];
 318                 } else {
 319                         ro = 0;
 320                         largest = -1;
 321                         /* find largest delta with dmu != 0 */
 322                         for (j = 0; j < i; j++) {
 323                                 if ((dmu[j]) && (delta[j] > largest)) {
 324                                         largest = delta[j];
 325                                         ro = j;
 326                                 }
 327                         }
 328
 329                         /* compute difference */
 330                         diff = (mu[i] - mu[ro]);
 331
 332                         /* Compute degree of the new smu polynomial */
 333                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 334                                 lmu[i + 1] = lmu[i];
 335                         else
 336                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 337
 338                         /* Init smu[i+1] with 0 */
 339                         for (k = 0; k < num; k++)
 340                                 smu[(i + 1) * num + k] = 0;
 341
 342                         /* Compute smu[i+1] */
 343                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 344                                 int16_t a, b, c;
 345
 346                                 if (!(smu[ro * num + k] && dmu[i]))
 347                                         continue;
 348                                 a = readw(index_of + dmu[i]);
 349                                 b = readw(index_of + dmu[ro]);
 350                                 c = readw(index_of + smu[ro * num + k]);
 351                                 tmp = a + (cw_len - b) + c;
 352                                 a = readw(alpha_to + tmp % cw_len);
 353                                 smu[(i + 1) * num + (k + diff)] = a;
 354                         }
 355
 356                         for (k = 0; k <= lmu[i] >> 1; k++)
 357                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 358                 }
 359
 360                 /* End Computing Sigma (Mu+1) and L(mu) */
 361                 /* In either case compute delta */
 362                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 363
 364                 /* Do not compute discrepancy for the last iteration */
 365                 if (i >= cap)
 366                         continue;
 367
 368                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 369                         tmp = 2 * (i - 1);
 370                         if (k == 0) {
 371                                 dmu[i + 1] = si[tmp + 3];
 372                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 373                                 int16_t a, b, c;
 374                                 a = readw(index_of +
 375                                                 smu[(i + 1) * num + k]);
 376                                 b = si[2 * (i - 1) + 3 - k];
 377                                 c = readw(index_of + b);
 378                                 tmp = a + c;
 379                                 tmp %= cw_len;
 380                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 381                                         dmu[i + 1];
 382                         }
 383                 }
 384         }
 385 }
 386
 387 static int pmecc_err_location(struct mtd_info *mtd)
 388 {
 389         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 390         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 391         const int cap = host->pmecc_corr_cap;
 392         const int num = 2 * cap + 1;
 393         int sector_size = host->pmecc_sector_size;
 394         int err_nbr = 0;        /* number of error */
 395         int roots_nbr;          /* number of roots */
 396         int i;
 397         uint32_t val;
 398         int16_t *smu = host->pmecc_smu;
 399         int timeout = PMECC_MAX_TIMEOUT_US;
 400
 401         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 402
 403         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 404                 pmecc_writel(host->pmerrloc, sigma[i],
 405                              smu[(cap + 1) * num + i]);
 406                 err_nbr++;
 407         }
 408
 409         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 410         if (sector_size == 1024)
 411                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 412
 413         pmecc_writel(host->pmerrloc, elcfg, val);
 414         pmecc_writel(host->pmerrloc, elen,
 415                      sector_size * 8 + host->pmecc_degree * cap);
 416
 417         while (--timeout) {
 418                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 419                         break;
 420                 WATCHDOG_RESET();
 421                 udelay(1);
 422         }
 423
 424         if (!timeout) {
 425                 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
 426                 return -1;
 427         }
 428
 429         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 430                         >> 8;
 431         /* Number of roots == degree of smu hence <= cap */
 432         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 433                 return err_nbr - 1;
 434
 435         /* Number of roots does not match the degree of smu
 436          * unable to correct error */
 437         return -1;
 438 }
 439
 440 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 441                 int sector_num, int extra_bytes, int err_nbr)
 442 {
 443         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 444         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 445         int i = 0;
 446         int byte_pos, bit_pos, sector_size, pos;
 447         uint32_t tmp;
 448         uint8_t err_byte;
 449
 450         sector_size = host->pmecc_sector_size;
 451
 452         while (err_nbr) {
 453                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 454                 byte_pos = tmp / 8;
 455                 bit_pos  = tmp % 8;
 456
 457                 if (byte_pos >= (sector_size + extra_bytes))
 458                         BUG();  /* should never happen */
 459
 460                 if (byte_pos < sector_size) {
 461                         err_byte = *(buf + byte_pos);
 462                         *(buf + byte_pos) ^= (1 << bit_pos);
 463
 464                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 465                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 466                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 467                 } else {
 468                         /* Bit flip in OOB area */
 469                         tmp = sector_num * host->pmecc_bytes_per_sector
 470                                         + (byte_pos - sector_size);
 471                         err_byte = ecc[tmp];
 472                         ecc[tmp] ^= (1 << bit_pos);
 473
 474                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 475                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 476                                 pos, bit_pos, err_byte, ecc[tmp]);
 477                 }
 478
 479                 i++;
 480                 err_nbr--;
 481         }
 482
 483         return;
 484 }
 485
 486 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 487         u8 *ecc)
 488 {
 489         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 490         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 491         int i, err_nbr, eccbytes;
 492         uint8_t *buf_pos;
 493
 494         /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
 495         if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
 496                 goto normal_check;
 497
 498         eccbytes = nand_chip->ecc.bytes;
 499         for (i = 0; i < eccbytes; i++)
 500                 if (ecc[i] != 0xff)
 501                         goto normal_check;
 502         /* Erased page, return OK */
 503         return 0;
 504
 505 normal_check:
 506         for (i = 0; i < host->pmecc_sector_number; i++) {
 507                 err_nbr = 0;
 508                 if (pmecc_stat & 0x1) {
 509                         buf_pos = buf + i * host->pmecc_sector_size;
 510
 511                         pmecc_gen_syndrome(mtd, i);
 512                         pmecc_substitute(mtd);
 513                         pmecc_get_sigma(mtd);
 514
 515                         err_nbr = pmecc_err_location(mtd);
 516                         if (err_nbr == -1) {
 517                                 dev_err(host->dev, "PMECC: Too many errors\n");
 518                                 mtd->ecc_stats.failed++;
 519                                 return -EBADMSG;
 520                         } else {
 521                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 522                                         host->pmecc_bytes_per_sector, err_nbr);
 523                                 mtd->ecc_stats.corrected += err_nbr;
 524                         }
 525                 }
 526                 pmecc_stat >>= 1;
 527         }
 528
 529         return 0;
 530 }
 531
 532 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 533         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 534 {
 535         struct atmel_nand_host *host = nand_get_controller_data(chip);
 536         int eccsize = chip->ecc.size;
 537         uint8_t *oob = chip->oob_poi;
 538         uint32_t *eccpos = chip->ecc.layout->eccpos;
 539         uint32_t stat;
 540         int timeout = PMECC_MAX_TIMEOUT_US;
 541
 542         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 543         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 544         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 545                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 546
 547         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 548         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 549
 550         chip->read_buf(mtd, buf, eccsize);
 551         chip->read_buf(mtd, oob, mtd->oobsize);
 552
 553         while (--timeout) {
 554                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 555                         break;
 556                 WATCHDOG_RESET();
 557                 udelay(1);
 558         }
 559
 560         if (!timeout) {
 561                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
 562                 return -1;
 563         }
 564
 565         stat = pmecc_readl(host->pmecc, isr);
 566         if (stat != 0)
 567                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 568                         return -EBADMSG;
 569
 570         return 0;
 571 }
 572
 573 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 574                 struct nand_chip *chip, const uint8_t *buf,
 575                 int oob_required, int page)
 576 {
 577         struct atmel_nand_host *host = nand_get_controller_data(chip);
 578         uint32_t *eccpos = chip->ecc.layout->eccpos;
 579         int i, j;
 580         int timeout = PMECC_MAX_TIMEOUT_US;
 581
 582         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 583         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 584
 585         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 586                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 587
 588         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 589         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 590
 591         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 592
 593         while (--timeout) {
 594                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 595                         break;
 596                 WATCHDOG_RESET();
 597                 udelay(1);
 598         }
 599
 600         if (!timeout) {
 601                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 602                 goto out;
 603         }
 604
 605         for (i = 0; i < host->pmecc_sector_number; i++) {
 606                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 607                         int pos;
 608
 609                         pos = i * host->pmecc_bytes_per_sector + j;
 610                         chip->oob_poi[eccpos[pos]] =
 611                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 612                 }
 613         }
 614         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 615 out:
 616         return 0;
 617 }
 618
 619 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 620 {
 621         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 622         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 623         uint32_t val = 0;
 624         struct nand_ecclayout *ecc_layout;
 625
 626         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 627         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 628
 629         switch (host->pmecc_corr_cap) {
 630         case 2:
 631                 val = PMECC_CFG_BCH_ERR2;
 632                 break;
 633         case 4:
 634                 val = PMECC_CFG_BCH_ERR4;
 635                 break;
 636         case 8:
 637                 val = PMECC_CFG_BCH_ERR8;
 638                 break;
 639         case 12:
 640                 val = PMECC_CFG_BCH_ERR12;
 641                 break;
 642         case 24:
 643                 val = PMECC_CFG_BCH_ERR24;
 644                 break;
 645         case 32:
 646                 val = PMECC_CFG_BCH_ERR32;
 647                 break;
 648         }
 649
 650         if (host->pmecc_sector_size == 512)
 651                 val |= PMECC_CFG_SECTOR512;
 652         else if (host->pmecc_sector_size == 1024)
 653                 val |= PMECC_CFG_SECTOR1024;
 654
 655         switch (host->pmecc_sector_number) {
 656         case 1:
 657                 val |= PMECC_CFG_PAGE_1SECTOR;
 658                 break;
 659         case 2:
 660                 val |= PMECC_CFG_PAGE_2SECTORS;
 661                 break;
 662         case 4:
 663                 val |= PMECC_CFG_PAGE_4SECTORS;
 664                 break;
 665         case 8:
 666                 val |= PMECC_CFG_PAGE_8SECTORS;
 667                 break;
 668         }
 669
 670         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 671                 | PMECC_CFG_AUTO_DISABLE);
 672         pmecc_writel(host->pmecc, cfg, val);
 673
 674         ecc_layout = nand_chip->ecc.layout;
 675         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 676         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 677         pmecc_writel(host->pmecc, eaddr,
 678                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 679         /* See datasheet about PMECC Clock Control Register */
 680         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 681         pmecc_writel(host->pmecc, idr, 0xff);
 682         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 683 }
 684
 685 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 686 /*
 687  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 688  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 689  *                    ONFI ECC parameters.
 690  * @host: point to an atmel_nand_host structure.
 691  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 692  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 693  * @chip: point to an nand_chip structure.
 694  * @cap: store the ONFI ECC correct bits capbility
 695  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 696  *
 697  * Return 0 if success. otherwise return the error code.
 698  */
 699 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 700                 struct nand_chip *chip,
 701                 int *cap, int *sector_size)
 702 {
 703         /* Get ECC requirement from ONFI parameters */
 704         *cap = *sector_size = 0;
 705         if (chip->onfi_version) {
 706                 *cap = chip->ecc_strength_ds;
 707                 *sector_size = chip->ecc_step_ds;
 708                 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
 709                          *cap, *sector_size);
 710         }
 711
 712         if (*cap == 0 && *sector_size == 0) {
 713                 /* Non-ONFI compliant */
 714                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
 715                 *cap = 2;
 716                 *sector_size = 512;
 717         }
 718
 719         /* If head file doesn't specify then use the one in ONFI parameters */
 720         if (host->pmecc_corr_cap == 0) {
 721                 /* use the most fitable ecc bits (the near bigger one ) */
 722                 if (*cap <= 2)
 723                         host->pmecc_corr_cap = 2;
 724                 else if (*cap <= 4)
 725                         host->pmecc_corr_cap = 4;
 726                 else if (*cap <= 8)
 727                         host->pmecc_corr_cap = 8;
 728                 else if (*cap <= 12)
 729                         host->pmecc_corr_cap = 12;
 730                 else if (*cap <= 24)
 731                         host->pmecc_corr_cap = 24;
 732                 else
 733 #ifdef CONFIG_SAMA5D2
 734                         host->pmecc_corr_cap = 32;
 735 #else
 736                         host->pmecc_corr_cap = 24;
 737 #endif
 738         }
 739         if (host->pmecc_sector_size == 0) {
 740                 /* use the most fitable sector size (the near smaller one ) */
 741                 if (*sector_size >= 1024)
 742                         host->pmecc_sector_size = 1024;
 743                 else if (*sector_size >= 512)
 744                         host->pmecc_sector_size = 512;
 745                 else
 746                         return -EINVAL;
 747         }
 748         return 0;
 749 }
 750 #endif
 751
 752 #if defined(NO_GALOIS_TABLE_IN_ROM)
 753 static uint16_t *pmecc_galois_table;
 754 static inline int deg(unsigned int poly)
 755 {
 756         /* polynomial degree is the most-significant bit index */
 757         return fls(poly) - 1;
 758 }
 759
 760 static int build_gf_tables(int mm, unsigned int poly,
 761                            int16_t *index_of, int16_t *alpha_to)
 762 {
 763         unsigned int i, x = 1;
 764         const unsigned int k = 1 << deg(poly);
 765         unsigned int nn = (1 << mm) - 1;
 766
 767         /* primitive polynomial must be of degree m */
 768         if (k != (1u << mm))
 769                 return -EINVAL;
 770
 771         for (i = 0; i < nn; i++) {
 772                 alpha_to[i] = x;
 773                 index_of[x] = i;
 774                 if (i && (x == 1))
 775                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
 776                         return -EINVAL;
 777                 x <<= 1;
 778                 if (x & k)
 779                         x ^= poly;
 780         }
 781
 782         alpha_to[nn] = 1;
 783         index_of[0] = 0;
 784
 785         return 0;
 786 }
 787
 788 static uint16_t *create_lookup_table(int sector_size)
 789 {
 790         int degree = (sector_size == 512) ?
 791                         PMECC_GF_DIMENSION_13 :
 792                         PMECC_GF_DIMENSION_14;
 793         unsigned int poly = (sector_size == 512) ?
 794                         PMECC_GF_13_PRIMITIVE_POLY :
 795                         PMECC_GF_14_PRIMITIVE_POLY;
 796         int table_size = (sector_size == 512) ?
 797                         PMECC_INDEX_TABLE_SIZE_512 :
 798                         PMECC_INDEX_TABLE_SIZE_1024;
 799
 800         int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
 801         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
 802                 return NULL;
 803
 804         return (uint16_t *)addr;
 805 }
 806 #endif
 807
 808 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 809                 struct mtd_info *mtd)
 810 {
 811         struct atmel_nand_host *host;
 812         int cap, sector_size;
 813
 814         host = &pmecc_host;
 815         nand_set_controller_data(nand, host);
 816
 817         nand->ecc.mode = NAND_ECC_HW;
 818         nand->ecc.calculate = NULL;
 819         nand->ecc.correct = NULL;
 820         nand->ecc.hwctl = NULL;
 821
 822 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 823         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 824
 825 #ifdef CONFIG_PMECC_CAP
 826         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 827 #endif
 828 #ifdef CONFIG_PMECC_SECTOR_SIZE
 829         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 830 #endif
 831         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 832          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 833          * from ONFI.
 834          */
 835         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 836                 dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
 837                         cap, sector_size);
 838                 return -EINVAL;
 839         }
 840
 841         if (cap > host->pmecc_corr_cap)
 842                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 843                                 host->pmecc_corr_cap, cap);
 844         if (sector_size < host->pmecc_sector_size)
 845                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 846                                 host->pmecc_sector_size, sector_size);
 847 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 848         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 849         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 850 #endif
 851
 852         cap = host->pmecc_corr_cap;
 853         sector_size = host->pmecc_sector_size;
 854
 855         /* TODO: need check whether cap & sector_size is validate */
 856 #if defined(NO_GALOIS_TABLE_IN_ROM)
 857         /*
 858          * As pmecc_rom_base is the begin of the gallois field table, So the
 859          * index offset just set as 0.
 860          */
 861         host->pmecc_index_table_offset = 0;
 862 #else
 863         if (host->pmecc_sector_size == 512)
 864                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 865         else
 866                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 867 #endif
 868
 869         pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
 870                  cap, sector_size);
 871
 872         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 873         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 874                         ATMEL_BASE_PMERRLOC;
 875 #if defined(NO_GALOIS_TABLE_IN_ROM)
 876         pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
 877         if (!pmecc_galois_table) {
 878                 dev_err(host->dev, "out of memory\n");
 879                 return -ENOMEM;
 880         }
 881
 882         host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
 883 #else
 884         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 885 #endif
 886
 887         /* ECC is calculated for the whole page (1 step) */
 888         nand->ecc.size = mtd->writesize;
 889
 890         /* set ECC page size and oob layout */
 891         switch (mtd->writesize) {
 892         case 2048:
 893         case 4096:
 894         case 8192:
 895                 host->pmecc_degree = (sector_size == 512) ?
 896                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 897                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 898                 host->pmecc_sector_number = mtd->writesize / sector_size;
 899                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 900                         cap, sector_size);
 901                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 902                 host->pmecc_index_of = host->pmecc_rom_base +
 903                         host->pmecc_index_table_offset;
 904
 905                 nand->ecc.steps = 1;
 906                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 907                                        host->pmecc_sector_number;
 908
 909                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 910                         dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
 911                                         MTD_MAX_ECCPOS_ENTRIES_LARGE);
 912                         return -EINVAL;
 913                 }
 914
 915                 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
 916                         dev_err(host->dev, "No room for ECC bytes\n");
 917                         return -EINVAL;
 918                 }
 919                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 920                                         mtd->oobsize,
 921                                         nand->ecc.bytes);
 922                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 923                 break;
 924         case 512:
 925         case 1024:
 926                 /* TODO */
 927                 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
 928         default:
 929                 /* page size not handled by HW ECC */
 930                 /* switching back to soft ECC */
 931                 nand->ecc.mode = NAND_ECC_SOFT;
 932                 nand->ecc.read_page = NULL;
 933                 nand->ecc.postpad = 0;
 934                 nand->ecc.prepad = 0;
 935                 nand->ecc.bytes = 0;
 936                 return 0;
 937         }
 938
 939         /* Allocate data for PMECC computation */
 940         if (pmecc_data_alloc(host)) {
 941                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
 942                 return -ENOMEM;
 943         }
 944
 945         nand->options |= NAND_NO_SUBPAGE_WRITE;
 946         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 947         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 948         nand->ecc.strength = cap;
 949
 950         /* Check the PMECC ip version */
 951         host->pmecc_version = pmecc_readl(host->pmerrloc, version);
 952         dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
 953
 954         atmel_pmecc_core_init(mtd);
 955
 956         return 0;
 957 }
 958
 959 #else
 960
 961 /* oob layout for large page size
 962  * bad block info is on bytes 0 and 1
 963  * the bytes have to be consecutives to avoid
 964  * several NAND_CMD_RNDOUT during read
 965  */
 966 static struct nand_ecclayout atmel_oobinfo_large = {
 967         .eccbytes = 4,
 968         .eccpos = {60, 61, 62, 63},
 969         .oobfree = {
 970                 {2, 58}
 971         },
 972 };
 973
 974 /* oob layout for small page size
 975  * bad block info is on bytes 4 and 5
 976  * the bytes have to be consecutives to avoid
 977  * several NAND_CMD_RNDOUT during read
 978  */
 979 static struct nand_ecclayout atmel_oobinfo_small = {
 980         .eccbytes = 4,
 981         .eccpos = {0, 1, 2, 3},
 982         .oobfree = {
 983                 {6, 10}
 984         },
 985 };
 986
 987 /*
 988  * Calculate HW ECC
 989  *
 990  * function called after a write
 991  *
 992  * mtd:        MTD block structure
 993  * dat:        raw data (unused)
 994  * ecc_code:   buffer for ECC
 995  */
 996 static int atmel_nand_calculate(struct mtd_info *mtd,
 997                 const u_char *dat, unsigned char *ecc_code)
 998 {
 999         unsigned int ecc_value;
1000
1001         /* get the first 2 ECC bytes */
1002         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1003
1004         ecc_code[0] = ecc_value & 0xFF;
1005         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1006
1007         /* get the last 2 ECC bytes */
1008         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1009
1010         ecc_code[2] = ecc_value & 0xFF;
1011         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1012
1013         return 0;
1014 }
1015
1016 /*
1017  * HW ECC read page function
1018  *
1019  * mtd:        mtd info structure
1020  * chip:       nand chip info structure
1021  * buf:        buffer to store read data
1022  * oob_required:    caller expects OOB data read to chip->oob_poi
1023  */
1024 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1025                                 uint8_t *buf, int oob_required, int page)
1026 {
1027         int eccsize = chip->ecc.size;
1028         int eccbytes = chip->ecc.bytes;
1029         uint32_t *eccpos = chip->ecc.layout->eccpos;
1030         uint8_t *p = buf;
1031         uint8_t *oob = chip->oob_poi;
1032         uint8_t *ecc_pos;
1033         int stat;
1034
1035         /* read the page */
1036         chip->read_buf(mtd, p, eccsize);
1037
1038         /* move to ECC position if needed */
1039         if (eccpos[0] != 0) {
1040                 /* This only works on large pages
1041                  * because the ECC controller waits for
1042                  * NAND_CMD_RNDOUTSTART after the
1043                  * NAND_CMD_RNDOUT.
1044                  * anyway, for small pages, the eccpos[0] == 0
1045                  */
1046                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1047                                 mtd->writesize + eccpos[0], -1);
1048         }
1049
1050         /* the ECC controller needs to read the ECC just after the data */
1051         ecc_pos = oob + eccpos[0];
1052         chip->read_buf(mtd, ecc_pos, eccbytes);
1053
1054         /* check if there's an error */
1055         stat = chip->ecc.correct(mtd, p, oob, NULL);
1056
1057         if (stat < 0)
1058                 mtd->ecc_stats.failed++;
1059         else
1060                 mtd->ecc_stats.corrected += stat;
1061
1062         /* get back to oob start (end of page) */
1063         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1064
1065         /* read the oob */
1066         chip->read_buf(mtd, oob, mtd->oobsize);
1067
1068         return 0;
1069 }
1070
1071 /*
1072  * HW ECC Correction
1073  *
1074  * function called after a read
1075  *
1076  * mtd:        MTD block structure
1077  * dat:        raw data read from the chip
1078  * read_ecc:   ECC from the chip (unused)
1079  * isnull:     unused
1080  *
1081  * Detect and correct a 1 bit error for a page
1082  */
1083 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1084                 u_char *read_ecc, u_char *isnull)
1085 {
1086         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1087         unsigned int ecc_status;
1088         unsigned int ecc_word, ecc_bit;
1089
1090         /* get the status from the Status Register */
1091         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1092
1093         /* if there's no error */
1094         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1095                 return 0;
1096
1097         /* get error bit offset (4 bits) */
1098         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1099         /* get word address (12 bits) */
1100         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1101         ecc_word >>= 4;
1102
1103         /* if there are multiple errors */
1104         if (ecc_status & ATMEL_ECC_MULERR) {
1105                 /* check if it is a freshly erased block
1106                  * (filled with 0xff) */
1107                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1108                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1109                         /* the block has just been erased, return OK */
1110                         return 0;
1111                 }
1112                 /* it doesn't seems to be a freshly
1113                  * erased block.
1114                  * We can't correct so many errors */
1115                 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1116                                 " Unable to correct.\n");
1117                 return -EBADMSG;
1118         }
1119
1120         /* if there's a single bit error : we can correct it */
1121         if (ecc_status & ATMEL_ECC_ECCERR) {
1122                 /* there's nothing much to do here.
1123                  * the bit error is on the ECC itself.
1124                  */
1125                 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1126                                 " Nothing to correct\n");
1127                 return 0;
1128         }
1129
1130         dev_warn(host->dev, "atmel_nand : one bit error on data."
1131                         " (word offset in the page :"
1132                         " 0x%x bit offset : 0x%x)\n",
1133                         ecc_word, ecc_bit);
1134         /* correct the error */
1135         if (nand_chip->options & NAND_BUSWIDTH_16) {
1136                 /* 16 bits words */
1137                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1138         } else {
1139                 /* 8 bits words */
1140                 dat[ecc_word] ^= (1 << ecc_bit);
1141         }
1142         dev_warn(host->dev, "atmel_nand : error corrected\n");
1143         return 1;
1144 }
1145
1146 /*
1147  * Enable HW ECC : unused on most chips
1148  */
1149 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1150 {
1151 }
1152
1153 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1154 {
1155         nand->ecc.mode = NAND_ECC_HW;
1156         nand->ecc.calculate = atmel_nand_calculate;
1157         nand->ecc.correct = atmel_nand_correct;
1158         nand->ecc.hwctl = atmel_nand_hwctl;
1159         nand->ecc.read_page = atmel_nand_read_page;
1160         nand->ecc.bytes = 4;
1161         nand->ecc.strength = 4;
1162
1163         if (nand->ecc.mode == NAND_ECC_HW) {
1164                 /* ECC is calculated for the whole page (1 step) */
1165                 nand->ecc.size = mtd->writesize;
1166
1167                 /* set ECC page size and oob layout */
1168                 switch (mtd->writesize) {
1169                 case 512:
1170                         nand->ecc.layout = &atmel_oobinfo_small;
1171                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1172                                         ATMEL_ECC_PAGESIZE_528);
1173                         break;
1174                 case 1024:
1175                         nand->ecc.layout = &atmel_oobinfo_large;
1176                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1177                                         ATMEL_ECC_PAGESIZE_1056);
1178                         break;
1179                 case 2048:
1180                         nand->ecc.layout = &atmel_oobinfo_large;
1181                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1182                                         ATMEL_ECC_PAGESIZE_2112);
1183                         break;
1184                 case 4096:
1185                         nand->ecc.layout = &atmel_oobinfo_large;
1186                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1187                                         ATMEL_ECC_PAGESIZE_4224);
1188                         break;
1189                 default:
1190                         /* page size not handled by HW ECC */
1191                         /* switching back to soft ECC */
1192                         nand->ecc.mode = NAND_ECC_SOFT;
1193                         nand->ecc.calculate = NULL;
1194                         nand->ecc.correct = NULL;
1195                         nand->ecc.hwctl = NULL;
1196                         nand->ecc.read_page = NULL;
1197                         nand->ecc.postpad = 0;
1198                         nand->ecc.prepad = 0;
1199                         nand->ecc.bytes = 0;
1200                         break;
1201                 }
1202         }
1203
1204         return 0;
1205 }
1206
1207 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1208
1209 #endif /* CONFIG_ATMEL_NAND_HWECC */
1210
1211 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1212                                          int cmd, unsigned int ctrl)
1213 {
1214         struct nand_chip *this = mtd_to_nand(mtd);
1215
1216         if (ctrl & NAND_CTRL_CHANGE) {
1217                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1218                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1219                              | CONFIG_SYS_NAND_MASK_CLE);
1220
1221                 if (ctrl & NAND_CLE)
1222                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1223                 if (ctrl & NAND_ALE)
1224                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1225
1226 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1227                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1228                                     !(ctrl & NAND_NCE));
1229 #endif
1230                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1231         }
1232
1233         if (cmd != NAND_CMD_NONE)
1234                 writeb(cmd, this->IO_ADDR_W);
1235 }
1236
1237 #ifdef CONFIG_SYS_NAND_READY_PIN
1238 static int at91_nand_ready(struct mtd_info *mtd)
1239 {
1240         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1241 }
1242 #endif
1243
1244 #ifdef CONFIG_SPL_BUILD
1245 /* The following code is for SPL */
1246 static struct mtd_info *mtd;
1247 static struct nand_chip nand_chip;
1248
1249 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1250 {
1251         struct nand_chip *this = mtd_to_nand(mtd);
1252         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1253         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1254                         unsigned int ctrl) = this->cmd_ctrl;
1255
1256         while (!this->dev_ready(mtd))
1257                 ;
1258
1259         if (cmd == NAND_CMD_READOOB) {
1260                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1261                 cmd = NAND_CMD_READ0;
1262         }
1263
1264         hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1265
1266         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1267                 offs >>= 1;
1268
1269         hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1270         hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1271         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1272         hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1273 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1274         hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1275 #endif
1276         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1277
1278         hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1279         hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1280
1281         while (!this->dev_ready(mtd))
1282                 ;
1283
1284         return 0;
1285 }
1286
1287 static int nand_is_bad_block(int block)
1288 {
1289         struct nand_chip *this = mtd_to_nand(mtd);
1290
1291         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1292
1293         if (this->options & NAND_BUSWIDTH_16) {
1294                 if (readw(this->IO_ADDR_R) != 0xffff)
1295                         return 1;
1296         } else {
1297                 if (readb(this->IO_ADDR_R) != 0xff)
1298                         return 1;
1299         }
1300
1301         return 0;
1302 }
1303
1304 #ifdef CONFIG_SPL_NAND_ECC
1305 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1306 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1307                   CONFIG_SYS_NAND_ECCSIZE)
1308 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1309
1310 static int nand_read_page(int block, int page, void *dst)
1311 {
1312         struct nand_chip *this = mtd_to_nand(mtd);
1313         u_char ecc_calc[ECCTOTAL];
1314         u_char ecc_code[ECCTOTAL];
1315         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1316         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1317         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1318         int eccsteps = ECCSTEPS;
1319         int i;
1320         uint8_t *p = dst;
1321         nand_command(block, page, 0, NAND_CMD_READ0);
1322
1323         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1324                 if (this->ecc.mode != NAND_ECC_SOFT)
1325                         this->ecc.hwctl(mtd, NAND_ECC_READ);
1326                 this->read_buf(mtd, p, eccsize);
1327                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1328         }
1329         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1330
1331         for (i = 0; i < ECCTOTAL; i++)
1332                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1333
1334         eccsteps = ECCSTEPS;
1335         p = dst;
1336
1337         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1338                 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1339
1340         return 0;
1341 }
1342
1343 int spl_nand_erase_one(int block, int page)
1344 {
1345         struct nand_chip *this = mtd_to_nand(mtd);
1346         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1347                         unsigned int ctrl) = this->cmd_ctrl;
1348         int page_addr;
1349
1350         if (nand_chip.select_chip)
1351                 nand_chip.select_chip(mtd, 0);
1352
1353         page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1354         hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1355         /* Row address */
1356         hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1357         hwctrl(mtd, ((page_addr >> 8) & 0xff),
1358                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1359 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1360         /* One more address cycle for devices > 128MiB */
1361         hwctrl(mtd, (page_addr >> 16) & 0x0f,
1362                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1363 #endif
1364         hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1365
1366         while (!this->dev_ready(mtd))
1367                 ;
1368
1369         nand_deselect();
1370
1371         return 0;
1372 }
1373 #else
1374 static int nand_read_page(int block, int page, void *dst)
1375 {
1376         struct nand_chip *this = mtd_to_nand(mtd);
1377
1378         nand_command(block, page, 0, NAND_CMD_READ0);
1379         atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1380
1381         return 0;
1382 }
1383 #endif /* CONFIG_SPL_NAND_ECC */
1384
1385 int at91_nand_wait_ready(struct mtd_info *mtd)
1386 {
1387         struct nand_chip *this = mtd_to_nand(mtd);
1388
1389         udelay(this->chip_delay);
1390
1391         return 1;
1392 }
1393
1394 int board_nand_init(struct nand_chip *nand)
1395 {
1396         int ret = 0;
1397
1398         nand->ecc.mode = NAND_ECC_SOFT;
1399 #ifdef CONFIG_SYS_NAND_DBW_16
1400         nand->options = NAND_BUSWIDTH_16;
1401         nand->read_buf = nand_read_buf16;
1402 #else
1403         nand->read_buf = nand_read_buf;
1404 #endif
1405         nand->cmd_ctrl = at91_nand_hwcontrol;
1406 #ifdef CONFIG_SYS_NAND_READY_PIN
1407         nand->dev_ready = at91_nand_ready;
1408 #else
1409         nand->dev_ready = at91_nand_wait_ready;
1410 #endif
1411         nand->chip_delay = 20;
1412 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1413         nand->bbt_options |= NAND_BBT_USE_FLASH;
1414 #endif
1415
1416 #ifdef CONFIG_ATMEL_NAND_HWECC
1417 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1418         ret = atmel_pmecc_nand_init_params(nand, mtd);
1419 #endif
1420 #endif
1421
1422         return ret;
1423 }
1424
1425 void nand_init(void)
1426 {
1427         mtd = nand_to_mtd(&nand_chip);
1428         mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1429         mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1430         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1431         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1432         board_nand_init(&nand_chip);
1433
1434 #ifdef CONFIG_SPL_NAND_ECC
1435         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1436                 nand_chip.ecc.calculate = nand_calculate_ecc;
1437                 nand_chip.ecc.correct = nand_correct_data;
1438         }
1439 #endif
1440
1441         if (nand_chip.select_chip)
1442                 nand_chip.select_chip(mtd, 0);
1443 }
1444
1445 void nand_deselect(void)
1446 {
1447         if (nand_chip.select_chip)
1448                 nand_chip.select_chip(mtd, -1);
1449 }
1450
1451 #include "nand_spl_loaders.c"
1452
1453 #else
1454
1455 #ifndef CONFIG_SYS_NAND_BASE_LIST
1456 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1457 #endif
1458 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1459 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1460
1461 int atmel_nand_chip_init(int devnum, ulong base_addr)
1462 {
1463         int ret;
1464         struct nand_chip *nand = &nand_chip[devnum];
1465         struct mtd_info *mtd = nand_to_mtd(nand);
1466
1467         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1468
1469 #ifdef CONFIG_NAND_ECC_BCH
1470         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1471 #else
1472         nand->ecc.mode = NAND_ECC_SOFT;
1473 #endif
1474 #ifdef CONFIG_SYS_NAND_DBW_16
1475         nand->options = NAND_BUSWIDTH_16;
1476 #endif
1477         nand->cmd_ctrl = at91_nand_hwcontrol;
1478 #ifdef CONFIG_SYS_NAND_READY_PIN
1479         nand->dev_ready = at91_nand_ready;
1480 #endif
1481         nand->chip_delay = 75;
1482 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1483         nand->bbt_options |= NAND_BBT_USE_FLASH;
1484 #endif
1485
1486         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1487         if (ret)
1488                 return ret;
1489
1490 #ifdef CONFIG_ATMEL_NAND_HWECC
1491 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1492         ret = atmel_pmecc_nand_init_params(nand, mtd);
1493 #else
1494         ret = atmel_hwecc_nand_init_param(nand, mtd);
1495 #endif
1496         if (ret)
1497                 return ret;
1498 #endif
1499
1500         ret = nand_scan_tail(mtd);
1501         if (!ret)
1502                 nand_register(devnum, mtd);
1503
1504         return ret;
1505 }
1506
1507 void board_nand_init(void)
1508 {
1509         int i;
1510         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1511                 if (atmel_nand_chip_init(i, base_addr[i]))
1512                         dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1513                                 i);
1514 }
1515 #endif /* CONFIG_SPL_BUILD */