1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
13 #include <dm/device_compat.h>
14 #include <dm/pinctrl.h>
15 #include <linux/compat.h>
16 #include <linux/dma-mapping.h>
18 #include <linux/sizes.h>
19 #include <power/regulator.h>
20 #include <asm/unaligned.h>
22 #include "tmio-common.h"
24 DECLARE_GLOBAL_DATA_PTR;
26 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
28 return readq(priv->regbase + (reg << 1));
31 static void tmio_sd_writeq(struct tmio_sd_priv *priv,
32 u64 val, unsigned int reg)
34 writeq(val, priv->regbase + (reg << 1));
37 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
39 return readw(priv->regbase + (reg >> 1));
42 static void tmio_sd_writew(struct tmio_sd_priv *priv,
43 u16 val, unsigned int reg)
45 writew(val, priv->regbase + (reg >> 1));
48 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
52 if (priv->caps & TMIO_SD_CAP_64BIT)
53 return readl(priv->regbase + (reg << 1));
54 else if (priv->caps & TMIO_SD_CAP_16BIT) {
55 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
56 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
57 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
58 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
62 return readl(priv->regbase + reg);
65 void tmio_sd_writel(struct tmio_sd_priv *priv,
66 u32 val, unsigned int reg)
68 if (priv->caps & TMIO_SD_CAP_64BIT)
69 writel(val, priv->regbase + (reg << 1));
70 else if (priv->caps & TMIO_SD_CAP_16BIT) {
71 writew(val & 0xffff, priv->regbase + (reg >> 1));
72 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
73 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
75 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
77 writel(val, priv->regbase + reg);
80 static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
82 struct tmio_sd_priv *priv = dev_get_priv(dev);
83 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
85 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
87 * TIMEOUT must be returned for unsupported command. Do not
88 * display error log since this might be a part of sequence to
89 * distinguish between SD and MMC.
94 if (info2 & TMIO_SD_INFO2_ERR_TO) {
95 dev_err(dev, "timeout error\n");
99 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
100 TMIO_SD_INFO2_ERR_IDX)) {
101 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
102 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
103 dev_err(dev, "communication out of sync\n");
107 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
108 TMIO_SD_INFO2_ERR_ILW)) {
109 dev_err(dev, "illegal access\n");
116 static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
117 unsigned int reg, u32 flag)
119 struct tmio_sd_priv *priv = dev_get_priv(dev);
123 while (!(tmio_sd_readl(priv, reg) & flag)) {
125 dev_err(dev, "timeout\n");
129 ret = tmio_sd_check_error(dev, cmd);
139 #define tmio_pio_read_fifo(__width, __suffix) \
140 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
141 char *pbuf, uint blksz) \
143 u##__width *buf = (u##__width *)pbuf; \
146 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
147 for (i = 0; i < blksz / ((__width) / 8); i++) { \
148 *buf++ = tmio_sd_read##__suffix(priv, \
152 for (i = 0; i < blksz / ((__width) / 8); i++) { \
154 data = tmio_sd_read##__suffix(priv, \
156 put_unaligned(data, buf++); \
161 tmio_pio_read_fifo(64, q)
162 tmio_pio_read_fifo(32, l)
163 tmio_pio_read_fifo(16, w)
165 static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
166 char *pbuf, uint blocksize)
168 struct tmio_sd_priv *priv = dev_get_priv(dev);
171 /* wait until the buffer is filled with data */
172 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
178 * Clear the status flag _before_ read the buffer out because
179 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
181 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
183 if (priv->caps & TMIO_SD_CAP_64BIT)
184 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
185 else if (priv->caps & TMIO_SD_CAP_16BIT)
186 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
188 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
193 #define tmio_pio_write_fifo(__width, __suffix) \
194 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
195 const char *pbuf, uint blksz)\
197 const u##__width *buf = (const u##__width *)pbuf; \
200 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
201 for (i = 0; i < blksz / ((__width) / 8); i++) { \
202 tmio_sd_write##__suffix(priv, *buf++, \
206 for (i = 0; i < blksz / ((__width) / 8); i++) { \
207 u##__width data = get_unaligned(buf++); \
208 tmio_sd_write##__suffix(priv, data, \
214 tmio_pio_write_fifo(64, q)
215 tmio_pio_write_fifo(32, l)
216 tmio_pio_write_fifo(16, w)
218 static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
219 const char *pbuf, uint blocksize)
221 struct tmio_sd_priv *priv = dev_get_priv(dev);
224 /* wait until the buffer becomes empty */
225 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
230 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
232 if (priv->caps & TMIO_SD_CAP_64BIT)
233 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
234 else if (priv->caps & TMIO_SD_CAP_16BIT)
235 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
237 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
242 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
243 struct mmc_data *data)
245 const char *src = data->src;
246 char *dest = data->dest;
249 for (i = 0; i < data->blocks; i++) {
250 if (data->flags & MMC_DATA_READ)
251 ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
254 ret = tmio_sd_pio_write_one_block(dev, cmd, src,
259 if (data->flags & MMC_DATA_READ)
260 dest += data->blocksize;
262 src += data->blocksize;
268 static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
273 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
274 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
277 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
278 tmp |= TMIO_SD_EXTMODE_DMA_EN;
279 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
281 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
283 /* suppress the warning "right shift count >= width of type" */
284 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
286 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
288 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
291 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
294 struct tmio_sd_priv *priv = dev_get_priv(dev);
295 long wait = 1000000 + 10 * blocks;
297 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
299 dev_err(dev, "timeout during DMA\n");
306 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
307 dev_err(dev, "error during DMA\n");
314 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
316 struct tmio_sd_priv *priv = dev_get_priv(dev);
317 size_t len = data->blocks * data->blocksize;
319 enum dma_data_direction dir;
324 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
326 if (data->flags & MMC_DATA_READ) {
328 dir = DMA_FROM_DEVICE;
330 * The DMA READ completion flag position differs on Socionext
331 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
332 * bit 17 is a hardware bug and forbidden. It is either bit 17
333 * or bit 20 on Renesas SoCs, depending on SoC.
335 poll_flag = priv->read_poll_flag;
336 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
338 buf = (void *)data->src;
340 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
341 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
344 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
346 dma_addr = dma_map_single(buf, len, dir);
348 tmio_sd_dma_start(priv, dma_addr);
350 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
352 if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
355 dma_unmap_single(dma_addr, len, dir);
360 /* check if the address is DMA'able */
361 static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
363 uintptr_t addr = (uintptr_t)data->src;
365 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
368 #if defined(CONFIG_RCAR_GEN3)
369 if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
371 /* Gen3 DMA has 32bit limit */
376 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
377 defined(CONFIG_SPL_BUILD)
379 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
380 * of L2, which is unreachable from the DMA engine.
382 if (addr < CONFIG_SPL_STACK)
389 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
390 struct mmc_data *data)
392 struct tmio_sd_priv *priv = dev_get_priv(dev);
396 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
397 dev_err(dev, "command busy\n");
401 /* clear all status flags */
402 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
403 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
405 /* disable DMA once */
406 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
407 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
408 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
410 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
415 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
416 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
418 /* Do not send CMD12 automatically */
419 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
421 if (data->blocks > 1)
422 tmp |= TMIO_SD_CMD_MULTI;
424 if (data->flags & MMC_DATA_READ)
425 tmp |= TMIO_SD_CMD_RD;
429 * Do not use the response type auto-detection on this hardware.
430 * CMD8, for example, has different response types on SD and eMMC,
431 * while this controller always assumes the response type for SD.
432 * Set the response type manually.
434 switch (cmd->resp_type) {
436 tmp |= TMIO_SD_CMD_RSP_NONE;
439 tmp |= TMIO_SD_CMD_RSP_R1;
442 tmp |= TMIO_SD_CMD_RSP_R1B;
445 tmp |= TMIO_SD_CMD_RSP_R2;
448 tmp |= TMIO_SD_CMD_RSP_R3;
451 dev_err(dev, "unknown response type\n");
455 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
456 cmd->cmdidx, tmp, cmd->cmdarg);
457 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
459 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
464 if (cmd->resp_type & MMC_RSP_136) {
465 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
466 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
467 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
468 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
470 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
471 ((rsp_103_72 & 0xff000000) >> 24);
472 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
473 ((rsp_71_40 & 0xff000000) >> 24);
474 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
475 ((rsp_39_8 & 0xff000000) >> 24);
476 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
479 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
483 /* use DMA if the HW supports it and the buffer is aligned */
484 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
485 tmio_sd_addr_is_dmaable(data))
486 ret = tmio_sd_dma_xfer(dev, data);
488 ret = tmio_sd_pio_xfer(dev, cmd, data);
492 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
498 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
499 TMIO_SD_INFO2_SCLKDIVEN);
502 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
507 switch (mmc->bus_width) {
510 val = TMIO_SD_OPTION_WIDTH_1;
513 val = TMIO_SD_OPTION_WIDTH_4;
516 val = TMIO_SD_OPTION_WIDTH_8;
522 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
523 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
525 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
530 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
535 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
537 tmp |= TMIO_SD_IF_MODE_DDR;
539 tmp &= ~TMIO_SD_IF_MODE_DDR;
540 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
543 static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
545 return priv->clk_get_rate(priv);
548 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
550 unsigned int divisor;
555 mclk = tmio_sd_clk_get_rate(priv);
557 divisor = DIV_ROUND_UP(mclk, mmc->clock);
559 /* Do not set divider to 0xff in DDR mode */
560 if (mmc->ddr_mode && (divisor == 1))
564 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
565 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
566 else if (divisor <= 2)
567 val = TMIO_SD_CLKCTL_DIV2;
568 else if (divisor <= 4)
569 val = TMIO_SD_CLKCTL_DIV4;
570 else if (divisor <= 8)
571 val = TMIO_SD_CLKCTL_DIV8;
572 else if (divisor <= 16)
573 val = TMIO_SD_CLKCTL_DIV16;
574 else if (divisor <= 32)
575 val = TMIO_SD_CLKCTL_DIV32;
576 else if (divisor <= 64)
577 val = TMIO_SD_CLKCTL_DIV64;
578 else if (divisor <= 128)
579 val = TMIO_SD_CLKCTL_DIV128;
580 else if (divisor <= 256)
581 val = TMIO_SD_CLKCTL_DIV256;
582 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
583 val = TMIO_SD_CLKCTL_DIV512;
585 val = TMIO_SD_CLKCTL_DIV1024;
588 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
590 !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
591 ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
593 * Stop the clock before changing its rate
594 * to avoid a glitch signal
596 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
597 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
599 /* Change the clock rate. */
600 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
604 /* Enable or Disable the clock */
605 if (mmc->clk_disable) {
606 tmp |= TMIO_SD_CLKCTL_OFFEN;
607 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
609 tmp &= ~TMIO_SD_CLKCTL_OFFEN;
610 tmp |= TMIO_SD_CLKCTL_SCLKEN;
613 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
618 static void tmio_sd_set_pins(struct udevice *dev)
620 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
622 #ifdef CONFIG_DM_REGULATOR
623 struct tmio_sd_priv *priv = dev_get_priv(dev);
625 if (priv->vqmmc_dev) {
626 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
627 regulator_set_value(priv->vqmmc_dev, 1800000);
629 regulator_set_value(priv->vqmmc_dev, 3300000);
630 regulator_set_enable(priv->vqmmc_dev, true);
634 #ifdef CONFIG_PINCTRL
635 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
636 pinctrl_select_state(dev, "state_uhs");
638 pinctrl_select_state(dev, "default");
642 int tmio_sd_set_ios(struct udevice *dev)
644 struct tmio_sd_priv *priv = dev_get_priv(dev);
645 struct mmc *mmc = mmc_get_mmc_dev(dev);
648 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
649 mmc->clock, mmc->ddr_mode, mmc->bus_width);
651 tmio_sd_set_clk_rate(priv, mmc);
652 ret = tmio_sd_set_bus_width(priv, mmc);
655 tmio_sd_set_ddr_mode(priv, mmc);
656 tmio_sd_set_pins(dev);
661 int tmio_sd_get_cd(struct udevice *dev)
663 struct tmio_sd_priv *priv = dev_get_priv(dev);
665 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
668 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
672 static void tmio_sd_host_init(struct tmio_sd_priv *priv)
676 /* soft reset of the host */
677 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
678 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
679 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
680 tmp |= TMIO_SD_SOFT_RST_RSTX;
681 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
683 /* FIXME: implement eMMC hw_reset */
685 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
688 * Connected to 32bit AXI.
689 * This register dropped backward compatibility at version 0x10.
690 * Write an appropriate value depending on the IP version.
692 if (priv->version >= 0x10) {
693 if (priv->caps & TMIO_SD_CAP_64BIT)
694 tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
696 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
698 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
701 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
702 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
703 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
704 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
708 int tmio_sd_bind(struct udevice *dev)
710 struct tmio_sd_plat *plat = dev_get_platdata(dev);
712 return mmc_bind(dev, &plat->mmc, &plat->cfg);
715 int tmio_sd_probe(struct udevice *dev, u32 quirks)
717 struct tmio_sd_plat *plat = dev_get_platdata(dev);
718 struct tmio_sd_priv *priv = dev_get_priv(dev);
719 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
724 base = devfdt_get_addr(dev);
725 if (base == FDT_ADDR_T_NONE)
728 priv->regbase = devm_ioremap(dev, base, SZ_2K);
732 #ifdef CONFIG_DM_REGULATOR
733 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
735 regulator_set_value(priv->vqmmc_dev, 3300000);
738 ret = mmc_of_parse(dev, &plat->cfg);
740 dev_err(dev, "failed to parse host caps\n");
744 plat->cfg.name = dev->name;
745 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
750 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
752 dev_dbg(dev, "version %x\n", priv->version);
753 if (priv->version >= 0x10) {
754 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
755 priv->caps |= TMIO_SD_CAP_DIV1024;
758 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
760 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
762 tmio_sd_host_init(priv);
764 mclk = tmio_sd_clk_get_rate(priv);
766 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
767 plat->cfg.f_min = mclk /
768 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
769 plat->cfg.f_max = mclk;
770 if (quirks & TMIO_SD_CAP_16BIT)
771 plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
773 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
775 upriv->mmc = &plat->mmc;