drivers/mmc/tegra_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009 SAMSUNG Electronics
   4  * Minkyu Kang <mk7.kang@samsung.com>
   5  * Jaehoon Chung <jh80.chung@samsung.com>
   6  * Portions Copyright 2011-2019 NVIDIA Corporation
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <mmc.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <asm/arch-tegra/tegra_mmc.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  21 #include <asm/arch/clock.h>
  22 #endif
  23
  24 struct tegra_mmc_plat {
  25         struct mmc_config cfg;
  26         struct mmc mmc;
  27 };
  28
  29 struct tegra_mmc_priv {
  30         struct tegra_mmc *reg;
  31         struct reset_ctl reset_ctl;
  32         struct clk clk;
  33         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  34         struct gpio_desc pwr_gpio;      /* Power GPIO */
  35         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  36         unsigned int version;   /* SDHCI spec. version */
  37         unsigned int clock;     /* Current clock (MHz) */
  38         int mmc_id;             /* peripheral id */
  39 };
  40
  41 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  42                                 unsigned short power)
  43 {
  44         u8 pwr = 0;
  45         debug("%s: power = %x\n", __func__, power);
  46
  47         if (power != (unsigned short)-1) {
  48                 switch (1 << power) {
  49                 case MMC_VDD_165_195:
  50                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  51                         break;
  52                 case MMC_VDD_29_30:
  53                 case MMC_VDD_30_31:
  54                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  55                         break;
  56                 case MMC_VDD_32_33:
  57                 case MMC_VDD_33_34:
  58                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  59                         break;
  60                 }
  61         }
  62         debug("%s: pwr = %X\n", __func__, pwr);
  63
  64         /* Set the bus voltage first (if any) */
  65         writeb(pwr, &priv->reg->pwrcon);
  66         if (pwr == 0)
  67                 return;
  68
  69         /* Now enable bus power */
  70         pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  71         writeb(pwr, &priv->reg->pwrcon);
  72 }
  73
  74 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  75                                    struct mmc_data *data,
  76                                    struct bounce_buffer *bbstate)
  77 {
  78         unsigned char ctrl;
  79
  80
  81         debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  82                 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  83                 data->blocksize);
  84
  85         writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  86         /*
  87          * DMASEL[4:3]
  88          * 00 = Selects SDMA
  89          * 01 = Reserved
  90          * 10 = Selects 32-bit Address ADMA2
  91          * 11 = Selects 64-bit Address ADMA2
  92          */
  93         ctrl = readb(&priv->reg->hostctl);
  94         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  95         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  96         writeb(ctrl, &priv->reg->hostctl);
  97
  98         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  99         writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
 100         writew(data->blocks, &priv->reg->blkcnt);
 101 }
 102
 103 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
 104                                         struct mmc_data *data)
 105 {
 106         unsigned short mode;
 107         debug(" mmc_set_transfer_mode called\n");
 108         /*
 109          * TRNMOD
 110          * MUL1SIN0[5]  : Multi/Single Block Select
 111          * RD1WT0[4]    : Data Transfer Direction Select
 112          *      1 = read
 113          *      0 = write
 114          * ENACMD12[2]  : Auto CMD12 Enable
 115          * ENBLKCNT[1]  : Block Count Enable
 116          * ENDMA[0]     : DMA Enable
 117          */
 118         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 119                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 120
 121         if (data->blocks > 1)
 122                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 123
 124         if (data->flags & MMC_DATA_READ)
 125                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 126
 127         writew(mode, &priv->reg->trnmod);
 128 }
 129
 130 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
 131                                   struct mmc_cmd *cmd,
 132                                   struct mmc_data *data,
 133                                   unsigned int timeout)
 134 {
 135         /*
 136          * PRNSTS
 137          * CMDINHDAT[1] : Command Inhibit (DAT)
 138          * CMDINHCMD[0] : Command Inhibit (CMD)
 139          */
 140         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 141
 142         /*
 143          * We shouldn't wait for data inhibit for stop commands, even
 144          * though they might use busy signaling
 145          */
 146         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 147                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 148
 149         while (readl(&priv->reg->prnsts) & mask) {
 150                 if (timeout == 0) {
 151                         printf("%s: timeout error\n", __func__);
 152                         return -1;
 153                 }
 154                 timeout--;
 155                 udelay(1000);
 156         }
 157
 158         return 0;
 159 }
 160
 161 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
 162                                       struct mmc_data *data,
 163                                       struct bounce_buffer *bbstate)
 164 {
 165         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 166         int flags, i;
 167         int result;
 168         unsigned int mask = 0;
 169         unsigned int retry = 0x100000;
 170         debug(" mmc_send_cmd called\n");
 171
 172         result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
 173
 174         if (result < 0)
 175                 return result;
 176
 177         if (data)
 178                 tegra_mmc_prepare_data(priv, data, bbstate);
 179
 180         debug("cmd->arg: %08x\n", cmd->cmdarg);
 181         writel(cmd->cmdarg, &priv->reg->argument);
 182
 183         if (data)
 184                 tegra_mmc_set_transfer_mode(priv, data);
 185
 186         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 187                 return -1;
 188
 189         /*
 190          * CMDREG
 191          * CMDIDX[13:8] : Command index
 192          * DATAPRNT[5]  : Data Present Select
 193          * ENCMDIDX[4]  : Command Index Check Enable
 194          * ENCMDCRC[3]  : Command CRC Check Enable
 195          * RSPTYP[1:0]
 196          *      00 = No Response
 197          *      01 = Length 136
 198          *      10 = Length 48
 199          *      11 = Length 48 Check busy after response
 200          */
 201         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 202                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 203         else if (cmd->resp_type & MMC_RSP_136)
 204                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 205         else if (cmd->resp_type & MMC_RSP_BUSY)
 206                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 207         else
 208                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 209
 210         if (cmd->resp_type & MMC_RSP_CRC)
 211                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 212         if (cmd->resp_type & MMC_RSP_OPCODE)
 213                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 214         if (data)
 215                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 216
 217         debug("cmd: %d\n", cmd->cmdidx);
 218
 219         writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
 220
 221         for (i = 0; i < retry; i++) {
 222                 mask = readl(&priv->reg->norintsts);
 223                 /* Command Complete */
 224                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 225                         if (!data)
 226                                 writel(mask, &priv->reg->norintsts);
 227                         break;
 228                 }
 229         }
 230
 231         if (i == retry) {
 232                 printf("%s: waiting for status update\n", __func__);
 233                 writel(mask, &priv->reg->norintsts);
 234                 return -ETIMEDOUT;
 235         }
 236
 237         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 238                 /* Timeout Error */
 239                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 240                 writel(mask, &priv->reg->norintsts);
 241                 return -ETIMEDOUT;
 242         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 243                 /* Error Interrupt */
 244                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 245                 writel(mask, &priv->reg->norintsts);
 246                 return -1;
 247         }
 248
 249         if (cmd->resp_type & MMC_RSP_PRESENT) {
 250                 if (cmd->resp_type & MMC_RSP_136) {
 251                         /* CRC is stripped so we need to do some shifting. */
 252                         for (i = 0; i < 4; i++) {
 253                                 unsigned long offset = (unsigned long)
 254                                         (&priv->reg->rspreg3 - i);
 255                                 cmd->response[i] = readl(offset) << 8;
 256
 257                                 if (i != 3) {
 258                                         cmd->response[i] |=
 259                                                 readb(offset - 1);
 260                                 }
 261                                 debug("cmd->resp[%d]: %08x\n",
 262                                                 i, cmd->response[i]);
 263                         }
 264                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 265                         for (i = 0; i < retry; i++) {
 266                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 267                                 if (readl(&priv->reg->prnsts)
 268                                         & (1 << 20))    /* DAT[0] */
 269                                         break;
 270                         }
 271
 272                         if (i == retry) {
 273                                 printf("%s: card is still busy\n", __func__);
 274                                 writel(mask, &priv->reg->norintsts);
 275                                 return -ETIMEDOUT;
 276                         }
 277
 278                         cmd->response[0] = readl(&priv->reg->rspreg0);
 279                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 280                 } else {
 281                         cmd->response[0] = readl(&priv->reg->rspreg0);
 282                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 283                 }
 284         }
 285
 286         if (data) {
 287                 unsigned long   start = get_timer(0);
 288
 289                 while (1) {
 290                         mask = readl(&priv->reg->norintsts);
 291
 292                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 293                                 /* Error Interrupt */
 294                                 writel(mask, &priv->reg->norintsts);
 295                                 printf("%s: error during transfer: 0x%08x\n",
 296                                                 __func__, mask);
 297                                 return -1;
 298                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 299                                 /*
 300                                  * DMA Interrupt, restart the transfer where
 301                                  * it was interrupted.
 302                                  */
 303                                 unsigned int address = readl(&priv->reg->sysad);
 304
 305                                 debug("DMA end\n");
 306                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 307                                        &priv->reg->norintsts);
 308                                 writel(address, &priv->reg->sysad);
 309                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 310                                 /* Transfer Complete */
 311                                 debug("r/w is done\n");
 312                                 break;
 313                         } else if (get_timer(start) > 8000UL) {
 314                                 writel(mask, &priv->reg->norintsts);
 315                                 printf("%s: MMC Timeout\n"
 316                                        "    Interrupt status        0x%08x\n"
 317                                        "    Interrupt status enable 0x%08x\n"
 318                                        "    Interrupt signal enable 0x%08x\n"
 319                                        "    Present status          0x%08x\n",
 320                                        __func__, mask,
 321                                        readl(&priv->reg->norintstsen),
 322                                        readl(&priv->reg->norintsigen),
 323                                        readl(&priv->reg->prnsts));
 324                                 return -1;
 325                         }
 326                 }
 327                 writel(mask, &priv->reg->norintsts);
 328         }
 329
 330         udelay(1000);
 331         return 0;
 332 }
 333
 334 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 335                               struct mmc_data *data)
 336 {
 337         void *buf;
 338         unsigned int bbflags;
 339         size_t len;
 340         struct bounce_buffer bbstate;
 341         int ret;
 342
 343         if (data) {
 344                 if (data->flags & MMC_DATA_READ) {
 345                         buf = data->dest;
 346                         bbflags = GEN_BB_WRITE;
 347                 } else {
 348                         buf = (void *)data->src;
 349                         bbflags = GEN_BB_READ;
 350                 }
 351                 len = data->blocks * data->blocksize;
 352
 353                 bounce_buffer_start(&bbstate, buf, len, bbflags);
 354         }
 355
 356         ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
 357
 358         if (data)
 359                 bounce_buffer_stop(&bbstate);
 360
 361         return ret;
 362 }
 363
 364 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
 365 {
 366         ulong rate;
 367         int div;
 368         unsigned short clk;
 369         unsigned long timeout;
 370
 371         debug(" mmc_change_clock called\n");
 372
 373         /*
 374          * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
 375          */
 376         if (clock == 0)
 377                 goto out;
 378
 379         rate = clk_set_rate(&priv->clk, clock);
 380         div = (rate + clock - 1) / clock;
 381
 382 #if defined(CONFIG_TEGRA210)
 383         if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
 384                 /* clock_adjust_periph_pll_div() chooses a 'bad' clock
 385                  * on SDMMC1 T210, so skip it here and force a clock
 386                  * that's been spec'd in the table in the TRM for
 387                  * card-detect (400KHz).
 388                  */
 389                 uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
 390                                 CLOCK_ID_PERIPH, 24727273, NULL);
 391                 div = 62;
 392
 393                 debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
 394                       __func__, effective_rate, div, clock);
 395         } else {
 396                 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
 397                                             clock, &div);
 398         }
 399 #endif
 400         debug("div = %d\n", div);
 401
 402         writew(0, &priv->reg->clkcon);
 403
 404         /*
 405          * CLKCON
 406          * SELFREQ[15:8]        : base clock divided by value
 407          * ENSDCLK[2]           : SD Clock Enable
 408          * STBLINTCLK[1]        : Internal Clock Stable
 409          * ENINTCLK[0]          : Internal Clock Enable
 410          */
 411         div >>= 1;
 412         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 413                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 414         writew(clk, &priv->reg->clkcon);
 415
 416         /* Wait max 10 ms */
 417         timeout = 10;
 418         while (!(readw(&priv->reg->clkcon) &
 419                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 420                 if (timeout == 0) {
 421                         printf("%s: timeout error\n", __func__);
 422                         return;
 423                 }
 424                 timeout--;
 425                 udelay(1000);
 426         }
 427
 428         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 429         writew(clk, &priv->reg->clkcon);
 430
 431         debug("mmc_change_clock: clkcon = %08X\n", clk);
 432
 433 out:
 434         priv->clock = clock;
 435 }
 436
 437 static int tegra_mmc_set_ios(struct udevice *dev)
 438 {
 439         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 440         struct mmc *mmc = mmc_get_mmc_dev(dev);
 441         unsigned char ctrl;
 442         debug(" mmc_set_ios called\n");
 443
 444         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 445
 446         /* Change clock first */
 447         tegra_mmc_change_clock(priv, mmc->clock);
 448
 449         ctrl = readb(&priv->reg->hostctl);
 450
 451         /*
 452          * WIDE8[5]
 453          * 0 = Depend on WIDE4
 454          * 1 = 8-bit mode
 455          * WIDE4[1]
 456          * 1 = 4-bit mode
 457          * 0 = 1-bit mode
 458          */
 459         if (mmc->bus_width == 8)
 460                 ctrl |= (1 << 5);
 461         else if (mmc->bus_width == 4)
 462                 ctrl |= (1 << 1);
 463         else
 464                 ctrl &= ~(1 << 1 | 1 << 5);
 465
 466         writeb(ctrl, &priv->reg->hostctl);
 467         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 468
 469         return 0;
 470 }
 471
 472 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
 473 {
 474 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
 475         u32 val;
 476         u16 clk_con;
 477         int timeout;
 478         int id = priv->mmc_id;
 479
 480         debug("%s: sdmmc address = %p, id = %d\n", __func__,
 481                 priv->reg, id);
 482
 483         /* Set the pad drive strength for SDMMC1 or 3 only */
 484         if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
 485                 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
 486                         __func__);
 487                 return;
 488         }
 489
 490         val = readl(&priv->reg->sdmemcmppadctl);
 491         val &= 0xFFFFFFF0;
 492         val |= MEMCOMP_PADCTRL_VREF;
 493         writel(val, &priv->reg->sdmemcmppadctl);
 494
 495         /* Disable SD Clock Enable before running auto-cal as per TRM */
 496         clk_con = readw(&priv->reg->clkcon);
 497         debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 498         clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 499         writew(clk_con, &priv->reg->clkcon);
 500
 501         val = readl(&priv->reg->autocalcfg);
 502         val &= 0xFFFF0000;
 503         val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
 504         writel(val, &priv->reg->autocalcfg);
 505         val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
 506         writel(val, &priv->reg->autocalcfg);
 507         debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
 508         udelay(1);
 509         timeout = 100;                          /* 10 mSec max (100*100uS) */
 510         do {
 511                 val = readl(&priv->reg->autocalsts);
 512                 udelay(100);
 513         } while ((val & AUTO_CAL_ACTIVE) && --timeout);
 514         val = readl(&priv->reg->autocalsts);
 515         debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
 516               __func__, val, timeout);
 517
 518         /* Re-enable SD Clock Enable when auto-cal is done */
 519         clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 520         writew(clk_con, &priv->reg->clkcon);
 521         clk_con = readw(&priv->reg->clkcon);
 522         debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 523
 524         if (timeout == 0) {
 525                 printf("%s: Warning: Autocal timed out!\n", __func__);
 526                 /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
 527         }
 528
 529 #if defined(CONFIG_TEGRA210)
 530         u32 tap_value, trim_value;
 531
 532         /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
 533         val = readl(&priv->reg->venspictl);     /* aka VENDOR_SYS_SW_CNTL */
 534         val &= IO_TRIM_BYPASS_MASK;
 535         if (id == PERIPH_ID_SDMMC1) {
 536                 tap_value = 4;                  /* default */
 537                 if (val)
 538                         tap_value = 3;
 539                 trim_value = 2;
 540         } else {                                /* SDMMC3 */
 541                 tap_value = 3;
 542                 trim_value = 3;
 543         }
 544
 545         val = readl(&priv->reg->venclkctl);
 546         val &= ~TRIM_VAL_MASK;
 547         val |= (trim_value << TRIM_VAL_SHIFT);
 548         val &= ~TAP_VAL_MASK;
 549         val |= (tap_value << TAP_VAL_SHIFT);
 550         writel(val, &priv->reg->venclkctl);
 551         debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
 552 #endif  /* T210 */
 553 #endif  /* T30/T210 */
 554 }
 555
 556 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
 557 {
 558         unsigned int timeout;
 559         debug(" mmc_reset called\n");
 560
 561         /*
 562          * RSTALL[0] : Software reset for all
 563          * 1 = reset
 564          * 0 = work
 565          */
 566         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
 567
 568         priv->clock = 0;
 569
 570         /* Wait max 100 ms */
 571         timeout = 100;
 572
 573         /* hw clears the bit when it's done */
 574         while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 575                 if (timeout == 0) {
 576                         printf("%s: timeout error\n", __func__);
 577                         return;
 578                 }
 579                 timeout--;
 580                 udelay(1000);
 581         }
 582
 583         /* Set SD bus voltage & enable bus power */
 584         tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
 585         debug("%s: power control = %02X, host control = %02X\n", __func__,
 586                 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
 587
 588         /* Make sure SDIO pads are set up */
 589         tegra_mmc_pad_init(priv);
 590 }
 591
 592 static int tegra_mmc_init(struct udevice *dev)
 593 {
 594         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 595         struct mmc *mmc = mmc_get_mmc_dev(dev);
 596         unsigned int mask;
 597         debug(" tegra_mmc_init called\n");
 598
 599 #if defined(CONFIG_TEGRA210)
 600         priv->mmc_id = clock_decode_periph_id(dev);
 601         if (priv->mmc_id == PERIPH_ID_NONE) {
 602                 printf("%s: Missing/invalid peripheral ID\n", __func__);
 603                 return -EINVAL;
 604         }
 605 #endif
 606         tegra_mmc_reset(priv, mmc);
 607
 608 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
 609         /*
 610          * Disable the external clock loopback and use the internal one on
 611          * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
 612          * bits being set to 0xfffd according to the TRM.
 613          *
 614          * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
 615          * approach once proper kernel integration made it mainline.
 616          */
 617         if (priv->reg == (void *)0x700b0400) {
 618                 mask = readl(&priv->reg->venmiscctl);
 619                 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
 620                 writel(mask, &priv->reg->venmiscctl);
 621         }
 622 #endif
 623
 624         priv->version = readw(&priv->reg->hcver);
 625         debug("host version = %x\n", priv->version);
 626
 627         /* mask all */
 628         writel(0xffffffff, &priv->reg->norintstsen);
 629         writel(0xffffffff, &priv->reg->norintsigen);
 630
 631         writeb(0xe, &priv->reg->timeoutcon);    /* TMCLK * 2^27 */
 632         /*
 633          * NORMAL Interrupt Status Enable Register init
 634          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 635          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 636          * [3] ENSTADMAINT   : DMA boundary interrupt
 637          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 638          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 639         */
 640         mask = readl(&priv->reg->norintstsen);
 641         mask &= ~(0xffff);
 642         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 643                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 644                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 645                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 646                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 647         writel(mask, &priv->reg->norintstsen);
 648
 649         /*
 650          * NORMAL Interrupt Signal Enable Register init
 651          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 652          */
 653         mask = readl(&priv->reg->norintsigen);
 654         mask &= ~(0xffff);
 655         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 656         writel(mask, &priv->reg->norintsigen);
 657
 658         return 0;
 659 }
 660
 661 static int tegra_mmc_getcd(struct udevice *dev)
 662 {
 663         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 664
 665         debug("tegra_mmc_getcd called\n");
 666
 667         if (dm_gpio_is_valid(&priv->cd_gpio))
 668                 return dm_gpio_get_value(&priv->cd_gpio);
 669
 670         return 1;
 671 }
 672
 673 static const struct dm_mmc_ops tegra_mmc_ops = {
 674         .send_cmd       = tegra_mmc_send_cmd,
 675         .set_ios        = tegra_mmc_set_ios,
 676         .get_cd         = tegra_mmc_getcd,
 677 };
 678
 679 static int tegra_mmc_probe(struct udevice *dev)
 680 {
 681         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 682         struct tegra_mmc_plat *plat = dev_get_platdata(dev);
 683         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 684         struct mmc_config *cfg = &plat->cfg;
 685         int bus_width, ret;
 686
 687         cfg->name = dev->name;
 688
 689         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 690
 691         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 692         cfg->host_caps = 0;
 693         if (bus_width == 8)
 694                 cfg->host_caps |= MMC_MODE_8BIT;
 695         if (bus_width >= 4)
 696                 cfg->host_caps |= MMC_MODE_4BIT;
 697         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 698
 699         /*
 700          * min freq is for card identification, and is the highest
 701          *  low-speed SDIO card frequency (actually 400KHz)
 702          * max freq is highest HS eMMC clock as per the SD/MMC spec
 703          *  (actually 52MHz)
 704          */
 705         cfg->f_min = 375000;
 706         cfg->f_max = 48000000;
 707
 708         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 709
 710         priv->reg = (void *)dev_read_addr(dev);
 711
 712         ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
 713         if (ret) {
 714                 debug("reset_get_by_name() failed: %d\n", ret);
 715                 return ret;
 716         }
 717         ret = clk_get_by_index(dev, 0, &priv->clk);
 718         if (ret) {
 719                 debug("clk_get_by_index() failed: %d\n", ret);
 720                 return ret;
 721         }
 722
 723         ret = reset_assert(&priv->reset_ctl);
 724         if (ret)
 725                 return ret;
 726         ret = clk_enable(&priv->clk);
 727         if (ret)
 728                 return ret;
 729         ret = clk_set_rate(&priv->clk, 20000000);
 730         if (IS_ERR_VALUE(ret))
 731                 return ret;
 732         ret = reset_deassert(&priv->reset_ctl);
 733         if (ret)
 734                 return ret;
 735
 736         /* These GPIOs are optional */
 737         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
 738         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 739         gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
 740                              GPIOD_IS_OUT);
 741         if (dm_gpio_is_valid(&priv->pwr_gpio))
 742                 dm_gpio_set_value(&priv->pwr_gpio, 1);
 743
 744         upriv->mmc = &plat->mmc;
 745
 746         return tegra_mmc_init(dev);
 747 }
 748
 749 static int tegra_mmc_bind(struct udevice *dev)
 750 {
 751         struct tegra_mmc_plat *plat = dev_get_platdata(dev);
 752
 753         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 754 }
 755
 756 static const struct udevice_id tegra_mmc_ids[] = {
 757         { .compatible = "nvidia,tegra20-sdhci" },
 758         { .compatible = "nvidia,tegra30-sdhci" },
 759         { .compatible = "nvidia,tegra114-sdhci" },
 760         { .compatible = "nvidia,tegra124-sdhci" },
 761         { .compatible = "nvidia,tegra210-sdhci" },
 762         { .compatible = "nvidia,tegra186-sdhci" },
 763         { }
 764 };
 765
 766 U_BOOT_DRIVER(tegra_mmc_drv) = {
 767         .name           = "tegra_mmc",
 768         .id             = UCLASS_MMC,
 769         .of_match       = tegra_mmc_ids,
 770         .bind           = tegra_mmc_bind,
 771         .probe          = tegra_mmc_probe,
 772         .ops            = &tegra_mmc_ops,
 773         .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
 774         .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
 775 };