drivers/mmc/tegra_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009 SAMSUNG Electronics
   4  * Minkyu Kang <mk7.kang@samsung.com>
   5  * Jaehoon Chung <jh80.chung@samsung.com>
   6  * Portions Copyright 2011-2019 NVIDIA Corporation
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <mmc.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <asm/arch-tegra/tegra_mmc.h>
  18 #include <linux/err.h>
  19 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  20 #include <asm/arch/clock.h>
  21 #endif
  22
  23 struct tegra_mmc_plat {
  24         struct mmc_config cfg;
  25         struct mmc mmc;
  26 };
  27
  28 struct tegra_mmc_priv {
  29         struct tegra_mmc *reg;
  30         struct reset_ctl reset_ctl;
  31         struct clk clk;
  32         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  33         struct gpio_desc pwr_gpio;      /* Power GPIO */
  34         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  35         unsigned int version;   /* SDHCI spec. version */
  36         unsigned int clock;     /* Current clock (MHz) */
  37         int mmc_id;             /* peripheral id */
  38 };
  39
  40 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  41                                 unsigned short power)
  42 {
  43         u8 pwr = 0;
  44         debug("%s: power = %x\n", __func__, power);
  45
  46         if (power != (unsigned short)-1) {
  47                 switch (1 << power) {
  48                 case MMC_VDD_165_195:
  49                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  50                         break;
  51                 case MMC_VDD_29_30:
  52                 case MMC_VDD_30_31:
  53                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  54                         break;
  55                 case MMC_VDD_32_33:
  56                 case MMC_VDD_33_34:
  57                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  58                         break;
  59                 }
  60         }
  61         debug("%s: pwr = %X\n", __func__, pwr);
  62
  63         /* Set the bus voltage first (if any) */
  64         writeb(pwr, &priv->reg->pwrcon);
  65         if (pwr == 0)
  66                 return;
  67
  68         /* Now enable bus power */
  69         pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  70         writeb(pwr, &priv->reg->pwrcon);
  71 }
  72
  73 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  74                                    struct mmc_data *data,
  75                                    struct bounce_buffer *bbstate)
  76 {
  77         unsigned char ctrl;
  78
  79
  80         debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  81                 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  82                 data->blocksize);
  83
  84         writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  85         /*
  86          * DMASEL[4:3]
  87          * 00 = Selects SDMA
  88          * 01 = Reserved
  89          * 10 = Selects 32-bit Address ADMA2
  90          * 11 = Selects 64-bit Address ADMA2
  91          */
  92         ctrl = readb(&priv->reg->hostctl);
  93         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  94         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  95         writeb(ctrl, &priv->reg->hostctl);
  96
  97         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  98         writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
  99         writew(data->blocks, &priv->reg->blkcnt);
 100 }
 101
 102 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
 103                                         struct mmc_data *data)
 104 {
 105         unsigned short mode;
 106         debug(" mmc_set_transfer_mode called\n");
 107         /*
 108          * TRNMOD
 109          * MUL1SIN0[5]  : Multi/Single Block Select
 110          * RD1WT0[4]    : Data Transfer Direction Select
 111          *      1 = read
 112          *      0 = write
 113          * ENACMD12[2]  : Auto CMD12 Enable
 114          * ENBLKCNT[1]  : Block Count Enable
 115          * ENDMA[0]     : DMA Enable
 116          */
 117         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 118                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 119
 120         if (data->blocks > 1)
 121                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 122
 123         if (data->flags & MMC_DATA_READ)
 124                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 125
 126         writew(mode, &priv->reg->trnmod);
 127 }
 128
 129 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
 130                                   struct mmc_cmd *cmd,
 131                                   struct mmc_data *data,
 132                                   unsigned int timeout)
 133 {
 134         /*
 135          * PRNSTS
 136          * CMDINHDAT[1] : Command Inhibit (DAT)
 137          * CMDINHCMD[0] : Command Inhibit (CMD)
 138          */
 139         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 140
 141         /*
 142          * We shouldn't wait for data inhibit for stop commands, even
 143          * though they might use busy signaling
 144          */
 145         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 146                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 147
 148         while (readl(&priv->reg->prnsts) & mask) {
 149                 if (timeout == 0) {
 150                         printf("%s: timeout error\n", __func__);
 151                         return -1;
 152                 }
 153                 timeout--;
 154                 udelay(1000);
 155         }
 156
 157         return 0;
 158 }
 159
 160 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
 161                                       struct mmc_data *data,
 162                                       struct bounce_buffer *bbstate)
 163 {
 164         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 165         int flags, i;
 166         int result;
 167         unsigned int mask = 0;
 168         unsigned int retry = 0x100000;
 169         debug(" mmc_send_cmd called\n");
 170
 171         result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
 172
 173         if (result < 0)
 174                 return result;
 175
 176         if (data)
 177                 tegra_mmc_prepare_data(priv, data, bbstate);
 178
 179         debug("cmd->arg: %08x\n", cmd->cmdarg);
 180         writel(cmd->cmdarg, &priv->reg->argument);
 181
 182         if (data)
 183                 tegra_mmc_set_transfer_mode(priv, data);
 184
 185         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 186                 return -1;
 187
 188         /*
 189          * CMDREG
 190          * CMDIDX[13:8] : Command index
 191          * DATAPRNT[5]  : Data Present Select
 192          * ENCMDIDX[4]  : Command Index Check Enable
 193          * ENCMDCRC[3]  : Command CRC Check Enable
 194          * RSPTYP[1:0]
 195          *      00 = No Response
 196          *      01 = Length 136
 197          *      10 = Length 48
 198          *      11 = Length 48 Check busy after response
 199          */
 200         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 201                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 202         else if (cmd->resp_type & MMC_RSP_136)
 203                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 204         else if (cmd->resp_type & MMC_RSP_BUSY)
 205                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 206         else
 207                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 208
 209         if (cmd->resp_type & MMC_RSP_CRC)
 210                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 211         if (cmd->resp_type & MMC_RSP_OPCODE)
 212                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 213         if (data)
 214                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 215
 216         debug("cmd: %d\n", cmd->cmdidx);
 217
 218         writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
 219
 220         for (i = 0; i < retry; i++) {
 221                 mask = readl(&priv->reg->norintsts);
 222                 /* Command Complete */
 223                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 224                         if (!data)
 225                                 writel(mask, &priv->reg->norintsts);
 226                         break;
 227                 }
 228         }
 229
 230         if (i == retry) {
 231                 printf("%s: waiting for status update\n", __func__);
 232                 writel(mask, &priv->reg->norintsts);
 233                 return -ETIMEDOUT;
 234         }
 235
 236         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 237                 /* Timeout Error */
 238                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 239                 writel(mask, &priv->reg->norintsts);
 240                 return -ETIMEDOUT;
 241         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 242                 /* Error Interrupt */
 243                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 244                 writel(mask, &priv->reg->norintsts);
 245                 return -1;
 246         }
 247
 248         if (cmd->resp_type & MMC_RSP_PRESENT) {
 249                 if (cmd->resp_type & MMC_RSP_136) {
 250                         /* CRC is stripped so we need to do some shifting. */
 251                         for (i = 0; i < 4; i++) {
 252                                 unsigned long offset = (unsigned long)
 253                                         (&priv->reg->rspreg3 - i);
 254                                 cmd->response[i] = readl(offset) << 8;
 255
 256                                 if (i != 3) {
 257                                         cmd->response[i] |=
 258                                                 readb(offset - 1);
 259                                 }
 260                                 debug("cmd->resp[%d]: %08x\n",
 261                                                 i, cmd->response[i]);
 262                         }
 263                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 264                         for (i = 0; i < retry; i++) {
 265                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 266                                 if (readl(&priv->reg->prnsts)
 267                                         & (1 << 20))    /* DAT[0] */
 268                                         break;
 269                         }
 270
 271                         if (i == retry) {
 272                                 printf("%s: card is still busy\n", __func__);
 273                                 writel(mask, &priv->reg->norintsts);
 274                                 return -ETIMEDOUT;
 275                         }
 276
 277                         cmd->response[0] = readl(&priv->reg->rspreg0);
 278                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 279                 } else {
 280                         cmd->response[0] = readl(&priv->reg->rspreg0);
 281                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 282                 }
 283         }
 284
 285         if (data) {
 286                 unsigned long   start = get_timer(0);
 287
 288                 while (1) {
 289                         mask = readl(&priv->reg->norintsts);
 290
 291                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 292                                 /* Error Interrupt */
 293                                 writel(mask, &priv->reg->norintsts);
 294                                 printf("%s: error during transfer: 0x%08x\n",
 295                                                 __func__, mask);
 296                                 return -1;
 297                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 298                                 /*
 299                                  * DMA Interrupt, restart the transfer where
 300                                  * it was interrupted.
 301                                  */
 302                                 unsigned int address = readl(&priv->reg->sysad);
 303
 304                                 debug("DMA end\n");
 305                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 306                                        &priv->reg->norintsts);
 307                                 writel(address, &priv->reg->sysad);
 308                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 309                                 /* Transfer Complete */
 310                                 debug("r/w is done\n");
 311                                 break;
 312                         } else if (get_timer(start) > 8000UL) {
 313                                 writel(mask, &priv->reg->norintsts);
 314                                 printf("%s: MMC Timeout\n"
 315                                        "    Interrupt status        0x%08x\n"
 316                                        "    Interrupt status enable 0x%08x\n"
 317                                        "    Interrupt signal enable 0x%08x\n"
 318                                        "    Present status          0x%08x\n",
 319                                        __func__, mask,
 320                                        readl(&priv->reg->norintstsen),
 321                                        readl(&priv->reg->norintsigen),
 322                                        readl(&priv->reg->prnsts));
 323                                 return -1;
 324                         }
 325                 }
 326                 writel(mask, &priv->reg->norintsts);
 327         }
 328
 329         udelay(1000);
 330         return 0;
 331 }
 332
 333 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 334                               struct mmc_data *data)
 335 {
 336         void *buf;
 337         unsigned int bbflags;
 338         size_t len;
 339         struct bounce_buffer bbstate;
 340         int ret;
 341
 342         if (data) {
 343                 if (data->flags & MMC_DATA_READ) {
 344                         buf = data->dest;
 345                         bbflags = GEN_BB_WRITE;
 346                 } else {
 347                         buf = (void *)data->src;
 348                         bbflags = GEN_BB_READ;
 349                 }
 350                 len = data->blocks * data->blocksize;
 351
 352                 bounce_buffer_start(&bbstate, buf, len, bbflags);
 353         }
 354
 355         ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
 356
 357         if (data)
 358                 bounce_buffer_stop(&bbstate);
 359
 360         return ret;
 361 }
 362
 363 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
 364 {
 365         ulong rate;
 366         int div;
 367         unsigned short clk;
 368         unsigned long timeout;
 369
 370         debug(" mmc_change_clock called\n");
 371
 372         /*
 373          * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
 374          */
 375         if (clock == 0)
 376                 goto out;
 377
 378         rate = clk_set_rate(&priv->clk, clock);
 379         div = (rate + clock - 1) / clock;
 380
 381 #if defined(CONFIG_TEGRA210)
 382         if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
 383                 /* clock_adjust_periph_pll_div() chooses a 'bad' clock
 384                  * on SDMMC1 T210, so skip it here and force a clock
 385                  * that's been spec'd in the table in the TRM for
 386                  * card-detect (400KHz).
 387                  */
 388                 uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
 389                                 CLOCK_ID_PERIPH, 24727273, NULL);
 390                 div = 62;
 391
 392                 debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
 393                       __func__, effective_rate, div, clock);
 394         } else {
 395                 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
 396                                             clock, &div);
 397         }
 398 #endif
 399         debug("div = %d\n", div);
 400
 401         writew(0, &priv->reg->clkcon);
 402
 403         /*
 404          * CLKCON
 405          * SELFREQ[15:8]        : base clock divided by value
 406          * ENSDCLK[2]           : SD Clock Enable
 407          * STBLINTCLK[1]        : Internal Clock Stable
 408          * ENINTCLK[0]          : Internal Clock Enable
 409          */
 410         div >>= 1;
 411         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 412                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 413         writew(clk, &priv->reg->clkcon);
 414
 415         /* Wait max 10 ms */
 416         timeout = 10;
 417         while (!(readw(&priv->reg->clkcon) &
 418                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 419                 if (timeout == 0) {
 420                         printf("%s: timeout error\n", __func__);
 421                         return;
 422                 }
 423                 timeout--;
 424                 udelay(1000);
 425         }
 426
 427         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 428         writew(clk, &priv->reg->clkcon);
 429
 430         debug("mmc_change_clock: clkcon = %08X\n", clk);
 431
 432 out:
 433         priv->clock = clock;
 434 }
 435
 436 static int tegra_mmc_set_ios(struct udevice *dev)
 437 {
 438         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 439         struct mmc *mmc = mmc_get_mmc_dev(dev);
 440         unsigned char ctrl;
 441         debug(" mmc_set_ios called\n");
 442
 443         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 444
 445         /* Change clock first */
 446         tegra_mmc_change_clock(priv, mmc->clock);
 447
 448         ctrl = readb(&priv->reg->hostctl);
 449
 450         /*
 451          * WIDE8[5]
 452          * 0 = Depend on WIDE4
 453          * 1 = 8-bit mode
 454          * WIDE4[1]
 455          * 1 = 4-bit mode
 456          * 0 = 1-bit mode
 457          */
 458         if (mmc->bus_width == 8)
 459                 ctrl |= (1 << 5);
 460         else if (mmc->bus_width == 4)
 461                 ctrl |= (1 << 1);
 462         else
 463                 ctrl &= ~(1 << 1 | 1 << 5);
 464
 465         writeb(ctrl, &priv->reg->hostctl);
 466         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 467
 468         return 0;
 469 }
 470
 471 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
 472 {
 473 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
 474         u32 val;
 475         u16 clk_con;
 476         int timeout;
 477         int id = priv->mmc_id;
 478
 479         debug("%s: sdmmc address = %p, id = %d\n", __func__,
 480                 priv->reg, id);
 481
 482         /* Set the pad drive strength for SDMMC1 or 3 only */
 483         if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
 484                 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
 485                         __func__);
 486                 return;
 487         }
 488
 489         val = readl(&priv->reg->sdmemcmppadctl);
 490         val &= 0xFFFFFFF0;
 491         val |= MEMCOMP_PADCTRL_VREF;
 492         writel(val, &priv->reg->sdmemcmppadctl);
 493
 494         /* Disable SD Clock Enable before running auto-cal as per TRM */
 495         clk_con = readw(&priv->reg->clkcon);
 496         debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 497         clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 498         writew(clk_con, &priv->reg->clkcon);
 499
 500         val = readl(&priv->reg->autocalcfg);
 501         val &= 0xFFFF0000;
 502         val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
 503         writel(val, &priv->reg->autocalcfg);
 504         val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
 505         writel(val, &priv->reg->autocalcfg);
 506         debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
 507         udelay(1);
 508         timeout = 100;                          /* 10 mSec max (100*100uS) */
 509         do {
 510                 val = readl(&priv->reg->autocalsts);
 511                 udelay(100);
 512         } while ((val & AUTO_CAL_ACTIVE) && --timeout);
 513         val = readl(&priv->reg->autocalsts);
 514         debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
 515               __func__, val, timeout);
 516
 517         /* Re-enable SD Clock Enable when auto-cal is done */
 518         clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 519         writew(clk_con, &priv->reg->clkcon);
 520         clk_con = readw(&priv->reg->clkcon);
 521         debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 522
 523         if (timeout == 0) {
 524                 printf("%s: Warning: Autocal timed out!\n", __func__);
 525                 /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
 526         }
 527
 528 #if defined(CONFIG_TEGRA210)
 529         u32 tap_value, trim_value;
 530
 531         /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
 532         val = readl(&priv->reg->venspictl);     /* aka VENDOR_SYS_SW_CNTL */
 533         val &= IO_TRIM_BYPASS_MASK;
 534         if (id == PERIPH_ID_SDMMC1) {
 535                 tap_value = 4;                  /* default */
 536                 if (val)
 537                         tap_value = 3;
 538                 trim_value = 2;
 539         } else {                                /* SDMMC3 */
 540                 tap_value = 3;
 541                 trim_value = 3;
 542         }
 543
 544         val = readl(&priv->reg->venclkctl);
 545         val &= ~TRIM_VAL_MASK;
 546         val |= (trim_value << TRIM_VAL_SHIFT);
 547         val &= ~TAP_VAL_MASK;
 548         val |= (tap_value << TAP_VAL_SHIFT);
 549         writel(val, &priv->reg->venclkctl);
 550         debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
 551 #endif  /* T210 */
 552 #endif  /* T30/T210 */
 553 }
 554
 555 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
 556 {
 557         unsigned int timeout;
 558         debug(" mmc_reset called\n");
 559
 560         /*
 561          * RSTALL[0] : Software reset for all
 562          * 1 = reset
 563          * 0 = work
 564          */
 565         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
 566
 567         priv->clock = 0;
 568
 569         /* Wait max 100 ms */
 570         timeout = 100;
 571
 572         /* hw clears the bit when it's done */
 573         while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 574                 if (timeout == 0) {
 575                         printf("%s: timeout error\n", __func__);
 576                         return;
 577                 }
 578                 timeout--;
 579                 udelay(1000);
 580         }
 581
 582         /* Set SD bus voltage & enable bus power */
 583         tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
 584         debug("%s: power control = %02X, host control = %02X\n", __func__,
 585                 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
 586
 587         /* Make sure SDIO pads are set up */
 588         tegra_mmc_pad_init(priv);
 589 }
 590
 591 static int tegra_mmc_init(struct udevice *dev)
 592 {
 593         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 594         struct mmc *mmc = mmc_get_mmc_dev(dev);
 595         unsigned int mask;
 596         debug(" tegra_mmc_init called\n");
 597
 598 #if defined(CONFIG_TEGRA210)
 599         priv->mmc_id = clock_decode_periph_id(dev);
 600         if (priv->mmc_id == PERIPH_ID_NONE) {
 601                 printf("%s: Missing/invalid peripheral ID\n", __func__);
 602                 return -EINVAL;
 603         }
 604 #endif
 605         tegra_mmc_reset(priv, mmc);
 606
 607 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
 608         /*
 609          * Disable the external clock loopback and use the internal one on
 610          * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
 611          * bits being set to 0xfffd according to the TRM.
 612          *
 613          * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
 614          * approach once proper kernel integration made it mainline.
 615          */
 616         if (priv->reg == (void *)0x700b0400) {
 617                 mask = readl(&priv->reg->venmiscctl);
 618                 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
 619                 writel(mask, &priv->reg->venmiscctl);
 620         }
 621 #endif
 622
 623         priv->version = readw(&priv->reg->hcver);
 624         debug("host version = %x\n", priv->version);
 625
 626         /* mask all */
 627         writel(0xffffffff, &priv->reg->norintstsen);
 628         writel(0xffffffff, &priv->reg->norintsigen);
 629
 630         writeb(0xe, &priv->reg->timeoutcon);    /* TMCLK * 2^27 */
 631         /*
 632          * NORMAL Interrupt Status Enable Register init
 633          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 634          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 635          * [3] ENSTADMAINT   : DMA boundary interrupt
 636          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 637          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 638         */
 639         mask = readl(&priv->reg->norintstsen);
 640         mask &= ~(0xffff);
 641         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 642                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 643                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 644                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 645                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 646         writel(mask, &priv->reg->norintstsen);
 647
 648         /*
 649          * NORMAL Interrupt Signal Enable Register init
 650          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 651          */
 652         mask = readl(&priv->reg->norintsigen);
 653         mask &= ~(0xffff);
 654         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 655         writel(mask, &priv->reg->norintsigen);
 656
 657         return 0;
 658 }
 659
 660 static int tegra_mmc_getcd(struct udevice *dev)
 661 {
 662         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 663
 664         debug("tegra_mmc_getcd called\n");
 665
 666         if (dm_gpio_is_valid(&priv->cd_gpio))
 667                 return dm_gpio_get_value(&priv->cd_gpio);
 668
 669         return 1;
 670 }
 671
 672 static const struct dm_mmc_ops tegra_mmc_ops = {
 673         .send_cmd       = tegra_mmc_send_cmd,
 674         .set_ios        = tegra_mmc_set_ios,
 675         .get_cd         = tegra_mmc_getcd,
 676 };
 677
 678 static int tegra_mmc_probe(struct udevice *dev)
 679 {
 680         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 681         struct tegra_mmc_plat *plat = dev_get_platdata(dev);
 682         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 683         struct mmc_config *cfg = &plat->cfg;
 684         int bus_width, ret;
 685
 686         cfg->name = dev->name;
 687
 688         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 689
 690         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 691         cfg->host_caps = 0;
 692         if (bus_width == 8)
 693                 cfg->host_caps |= MMC_MODE_8BIT;
 694         if (bus_width >= 4)
 695                 cfg->host_caps |= MMC_MODE_4BIT;
 696         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 697
 698         /*
 699          * min freq is for card identification, and is the highest
 700          *  low-speed SDIO card frequency (actually 400KHz)
 701          * max freq is highest HS eMMC clock as per the SD/MMC spec
 702          *  (actually 52MHz)
 703          */
 704         cfg->f_min = 375000;
 705         cfg->f_max = 48000000;
 706
 707         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 708
 709         priv->reg = (void *)dev_read_addr(dev);
 710
 711         ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
 712         if (ret) {
 713                 debug("reset_get_by_name() failed: %d\n", ret);
 714                 return ret;
 715         }
 716         ret = clk_get_by_index(dev, 0, &priv->clk);
 717         if (ret) {
 718                 debug("clk_get_by_index() failed: %d\n", ret);
 719                 return ret;
 720         }
 721
 722         ret = reset_assert(&priv->reset_ctl);
 723         if (ret)
 724                 return ret;
 725         ret = clk_enable(&priv->clk);
 726         if (ret)
 727                 return ret;
 728         ret = clk_set_rate(&priv->clk, 20000000);
 729         if (IS_ERR_VALUE(ret))
 730                 return ret;
 731         ret = reset_deassert(&priv->reset_ctl);
 732         if (ret)
 733                 return ret;
 734
 735         /* These GPIOs are optional */
 736         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
 737         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 738         gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
 739                              GPIOD_IS_OUT);
 740         if (dm_gpio_is_valid(&priv->pwr_gpio))
 741                 dm_gpio_set_value(&priv->pwr_gpio, 1);
 742
 743         upriv->mmc = &plat->mmc;
 744
 745         return tegra_mmc_init(dev);
 746 }
 747
 748 static int tegra_mmc_bind(struct udevice *dev)
 749 {
 750         struct tegra_mmc_plat *plat = dev_get_platdata(dev);
 751
 752         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 753 }
 754
 755 static const struct udevice_id tegra_mmc_ids[] = {
 756         { .compatible = "nvidia,tegra20-sdhci" },
 757         { .compatible = "nvidia,tegra30-sdhci" },
 758         { .compatible = "nvidia,tegra114-sdhci" },
 759         { .compatible = "nvidia,tegra124-sdhci" },
 760         { .compatible = "nvidia,tegra210-sdhci" },
 761         { .compatible = "nvidia,tegra186-sdhci" },
 762         { }
 763 };
 764
 765 U_BOOT_DRIVER(tegra_mmc_drv) = {
 766         .name           = "tegra_mmc",
 767         .id             = UCLASS_MMC,
 768         .of_match       = tegra_mmc_ids,
 769         .bind           = tegra_mmc_bind,
 770         .probe          = tegra_mmc_probe,
 771         .ops            = &tegra_mmc_ops,
 772         .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
 773         .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
 774 };