drivers/mmc/tegra_mmc.c

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Portions Copyright 2011-2013 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <bouncebuf.h>
  23 #include <common.h>
  24 #include <fdtdec.h>
  25 #include <asm/gpio.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch-tegra/clk_rst.h>
  29 #include <asm/arch-tegra/tegra_mmc.h>
  30 #include <mmc.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 struct mmc mmc_dev[MAX_HOSTS];
  35 struct mmc_host mmc_host[MAX_HOSTS];
  36
  37 #ifndef CONFIG_OF_CONTROL
  38 #error "Please enable device tree support to use this driver"
  39 #endif
  40
  41 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
  42                                 struct bounce_buffer *bbstate)
  43 {
  44         unsigned char ctrl;
  45
  46
  47         debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  48                 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  49                 data->blocksize);
  50
  51         writel((u32)bbstate->bounce_buffer, &host->reg->sysad);
  52         /*
  53          * DMASEL[4:3]
  54          * 00 = Selects SDMA
  55          * 01 = Reserved
  56          * 10 = Selects 32-bit Address ADMA2
  57          * 11 = Selects 64-bit Address ADMA2
  58          */
  59         ctrl = readb(&host->reg->hostctl);
  60         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  61         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  62         writeb(ctrl, &host->reg->hostctl);
  63
  64         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  65         writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
  66         writew(data->blocks, &host->reg->blkcnt);
  67 }
  68
  69 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
  70 {
  71         unsigned short mode;
  72         debug(" mmc_set_transfer_mode called\n");
  73         /*
  74          * TRNMOD
  75          * MUL1SIN0[5]  : Multi/Single Block Select
  76          * RD1WT0[4]    : Data Transfer Direction Select
  77          *      1 = read
  78          *      0 = write
  79          * ENACMD12[2]  : Auto CMD12 Enable
  80          * ENBLKCNT[1]  : Block Count Enable
  81          * ENDMA[0]     : DMA Enable
  82          */
  83         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
  84                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
  85
  86         if (data->blocks > 1)
  87                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
  88
  89         if (data->flags & MMC_DATA_READ)
  90                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
  91
  92         writew(mode, &host->reg->trnmod);
  93 }
  94
  95 static int mmc_wait_inhibit(struct mmc_host *host,
  96                             struct mmc_cmd *cmd,
  97                             struct mmc_data *data,
  98                             unsigned int timeout)
  99 {
 100         /*
 101          * PRNSTS
 102          * CMDINHDAT[1] : Command Inhibit (DAT)
 103          * CMDINHCMD[0] : Command Inhibit (CMD)
 104          */
 105         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 106
 107         /*
 108          * We shouldn't wait for data inhibit for stop commands, even
 109          * though they might use busy signaling
 110          */
 111         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 112                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 113
 114         while (readl(&host->reg->prnsts) & mask) {
 115                 if (timeout == 0) {
 116                         printf("%s: timeout error\n", __func__);
 117                         return -1;
 118                 }
 119                 timeout--;
 120                 udelay(1000);
 121         }
 122
 123         return 0;
 124 }
 125
 126 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
 127                         struct mmc_data *data, struct bounce_buffer *bbstate)
 128 {
 129         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 130         int flags, i;
 131         int result;
 132         unsigned int mask = 0;
 133         unsigned int retry = 0x100000;
 134         debug(" mmc_send_cmd called\n");
 135
 136         result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
 137
 138         if (result < 0)
 139                 return result;
 140
 141         if (data)
 142                 mmc_prepare_data(host, data, bbstate);
 143
 144         debug("cmd->arg: %08x\n", cmd->cmdarg);
 145         writel(cmd->cmdarg, &host->reg->argument);
 146
 147         if (data)
 148                 mmc_set_transfer_mode(host, data);
 149
 150         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 151                 return -1;
 152
 153         /*
 154          * CMDREG
 155          * CMDIDX[13:8] : Command index
 156          * DATAPRNT[5]  : Data Present Select
 157          * ENCMDIDX[4]  : Command Index Check Enable
 158          * ENCMDCRC[3]  : Command CRC Check Enable
 159          * RSPTYP[1:0]
 160          *      00 = No Response
 161          *      01 = Length 136
 162          *      10 = Length 48
 163          *      11 = Length 48 Check busy after response
 164          */
 165         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 166                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 167         else if (cmd->resp_type & MMC_RSP_136)
 168                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 169         else if (cmd->resp_type & MMC_RSP_BUSY)
 170                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 171         else
 172                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 173
 174         if (cmd->resp_type & MMC_RSP_CRC)
 175                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 176         if (cmd->resp_type & MMC_RSP_OPCODE)
 177                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 178         if (data)
 179                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 180
 181         debug("cmd: %d\n", cmd->cmdidx);
 182
 183         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
 184
 185         for (i = 0; i < retry; i++) {
 186                 mask = readl(&host->reg->norintsts);
 187                 /* Command Complete */
 188                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 189                         if (!data)
 190                                 writel(mask, &host->reg->norintsts);
 191                         break;
 192                 }
 193         }
 194
 195         if (i == retry) {
 196                 printf("%s: waiting for status update\n", __func__);
 197                 writel(mask, &host->reg->norintsts);
 198                 return TIMEOUT;
 199         }
 200
 201         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 202                 /* Timeout Error */
 203                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 204                 writel(mask, &host->reg->norintsts);
 205                 return TIMEOUT;
 206         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 207                 /* Error Interrupt */
 208                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 209                 writel(mask, &host->reg->norintsts);
 210                 return -1;
 211         }
 212
 213         if (cmd->resp_type & MMC_RSP_PRESENT) {
 214                 if (cmd->resp_type & MMC_RSP_136) {
 215                         /* CRC is stripped so we need to do some shifting. */
 216                         for (i = 0; i < 4; i++) {
 217                                 unsigned int offset =
 218                                         (unsigned int)(&host->reg->rspreg3 - i);
 219                                 cmd->response[i] = readl(offset) << 8;
 220
 221                                 if (i != 3) {
 222                                         cmd->response[i] |=
 223                                                 readb(offset - 1);
 224                                 }
 225                                 debug("cmd->resp[%d]: %08x\n",
 226                                                 i, cmd->response[i]);
 227                         }
 228                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 229                         for (i = 0; i < retry; i++) {
 230                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 231                                 if (readl(&host->reg->prnsts)
 232                                         & (1 << 20))    /* DAT[0] */
 233                                         break;
 234                         }
 235
 236                         if (i == retry) {
 237                                 printf("%s: card is still busy\n", __func__);
 238                                 writel(mask, &host->reg->norintsts);
 239                                 return TIMEOUT;
 240                         }
 241
 242                         cmd->response[0] = readl(&host->reg->rspreg0);
 243                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 244                 } else {
 245                         cmd->response[0] = readl(&host->reg->rspreg0);
 246                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 247                 }
 248         }
 249
 250         if (data) {
 251                 unsigned long   start = get_timer(0);
 252
 253                 while (1) {
 254                         mask = readl(&host->reg->norintsts);
 255
 256                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 257                                 /* Error Interrupt */
 258                                 writel(mask, &host->reg->norintsts);
 259                                 printf("%s: error during transfer: 0x%08x\n",
 260                                                 __func__, mask);
 261                                 return -1;
 262                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 263                                 /*
 264                                  * DMA Interrupt, restart the transfer where
 265                                  * it was interrupted.
 266                                  */
 267                                 unsigned int address = readl(&host->reg->sysad);
 268
 269                                 debug("DMA end\n");
 270                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 271                                        &host->reg->norintsts);
 272                                 writel(address, &host->reg->sysad);
 273                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 274                                 /* Transfer Complete */
 275                                 debug("r/w is done\n");
 276                                 break;
 277                         } else if (get_timer(start) > 2000UL) {
 278                                 writel(mask, &host->reg->norintsts);
 279                                 printf("%s: MMC Timeout\n"
 280                                        "    Interrupt status        0x%08x\n"
 281                                        "    Interrupt status enable 0x%08x\n"
 282                                        "    Interrupt signal enable 0x%08x\n"
 283                                        "    Present status          0x%08x\n",
 284                                        __func__, mask,
 285                                        readl(&host->reg->norintstsen),
 286                                        readl(&host->reg->norintsigen),
 287                                        readl(&host->reg->prnsts));
 288                                 return -1;
 289                         }
 290                 }
 291                 writel(mask, &host->reg->norintsts);
 292         }
 293
 294         udelay(1000);
 295         return 0;
 296 }
 297
 298 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 299                         struct mmc_data *data)
 300 {
 301         void *buf;
 302         unsigned int bbflags;
 303         size_t len;
 304         struct bounce_buffer bbstate;
 305         int ret;
 306
 307         if (data) {
 308                 if (data->flags & MMC_DATA_READ) {
 309                         buf = data->dest;
 310                         bbflags = GEN_BB_WRITE;
 311                 } else {
 312                         buf = (void *)data->src;
 313                         bbflags = GEN_BB_READ;
 314                 }
 315                 len = data->blocks * data->blocksize;
 316
 317                 bounce_buffer_start(&bbstate, buf, len, bbflags);
 318         }
 319
 320         ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
 321
 322         if (data)
 323                 bounce_buffer_stop(&bbstate);
 324
 325         return ret;
 326 }
 327
 328 static void mmc_change_clock(struct mmc_host *host, uint clock)
 329 {
 330         int div;
 331         unsigned short clk;
 332         unsigned long timeout;
 333
 334         debug(" mmc_change_clock called\n");
 335
 336         /*
 337          * Change Tegra SDMMCx clock divisor here. Source is 216MHz,
 338          * PLLP_OUT0
 339          */
 340         if (clock == 0)
 341                 goto out;
 342         clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 343                                     &div);
 344         debug("div = %d\n", div);
 345
 346         writew(0, &host->reg->clkcon);
 347
 348         /*
 349          * CLKCON
 350          * SELFREQ[15:8]        : base clock divided by value
 351          * ENSDCLK[2]           : SD Clock Enable
 352          * STBLINTCLK[1]        : Internal Clock Stable
 353          * ENINTCLK[0]          : Internal Clock Enable
 354          */
 355         div >>= 1;
 356         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 357                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 358         writew(clk, &host->reg->clkcon);
 359
 360         /* Wait max 10 ms */
 361         timeout = 10;
 362         while (!(readw(&host->reg->clkcon) &
 363                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 364                 if (timeout == 0) {
 365                         printf("%s: timeout error\n", __func__);
 366                         return;
 367                 }
 368                 timeout--;
 369                 udelay(1000);
 370         }
 371
 372         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 373         writew(clk, &host->reg->clkcon);
 374
 375         debug("mmc_change_clock: clkcon = %08X\n", clk);
 376
 377 out:
 378         host->clock = clock;
 379 }
 380
 381 static void mmc_set_ios(struct mmc *mmc)
 382 {
 383         struct mmc_host *host = mmc->priv;
 384         unsigned char ctrl;
 385         debug(" mmc_set_ios called\n");
 386
 387         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 388
 389         /* Change clock first */
 390         mmc_change_clock(host, mmc->clock);
 391
 392         ctrl = readb(&host->reg->hostctl);
 393
 394         /*
 395          * WIDE8[5]
 396          * 0 = Depend on WIDE4
 397          * 1 = 8-bit mode
 398          * WIDE4[1]
 399          * 1 = 4-bit mode
 400          * 0 = 1-bit mode
 401          */
 402         if (mmc->bus_width == 8)
 403                 ctrl |= (1 << 5);
 404         else if (mmc->bus_width == 4)
 405                 ctrl |= (1 << 1);
 406         else
 407                 ctrl &= ~(1 << 1);
 408
 409         writeb(ctrl, &host->reg->hostctl);
 410         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 411 }
 412
 413 static void mmc_reset(struct mmc_host *host)
 414 {
 415         unsigned int timeout;
 416         debug(" mmc_reset called\n");
 417
 418         /*
 419          * RSTALL[0] : Software reset for all
 420          * 1 = reset
 421          * 0 = work
 422          */
 423         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
 424
 425         host->clock = 0;
 426
 427         /* Wait max 100 ms */
 428         timeout = 100;
 429
 430         /* hw clears the bit when it's done */
 431         while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 432                 if (timeout == 0) {
 433                         printf("%s: timeout error\n", __func__);
 434                         return;
 435                 }
 436                 timeout--;
 437                 udelay(1000);
 438         }
 439 }
 440
 441 static int mmc_core_init(struct mmc *mmc)
 442 {
 443         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 444         unsigned int mask;
 445         debug(" mmc_core_init called\n");
 446
 447         mmc_reset(host);
 448
 449         host->version = readw(&host->reg->hcver);
 450         debug("host version = %x\n", host->version);
 451
 452         /* mask all */
 453         writel(0xffffffff, &host->reg->norintstsen);
 454         writel(0xffffffff, &host->reg->norintsigen);
 455
 456         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
 457         /*
 458          * NORMAL Interrupt Status Enable Register init
 459          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 460          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 461          * [3] ENSTADMAINT   : DMA boundary interrupt
 462          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 463          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 464         */
 465         mask = readl(&host->reg->norintstsen);
 466         mask &= ~(0xffff);
 467         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 468                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 469                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 470                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 471                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 472         writel(mask, &host->reg->norintstsen);
 473
 474         /*
 475          * NORMAL Interrupt Signal Enable Register init
 476          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 477          */
 478         mask = readl(&host->reg->norintsigen);
 479         mask &= ~(0xffff);
 480         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 481         writel(mask, &host->reg->norintsigen);
 482
 483         return 0;
 484 }
 485
 486 int tegra_mmc_getcd(struct mmc *mmc)
 487 {
 488         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 489
 490         debug("tegra_mmc_getcd called\n");
 491
 492         if (fdt_gpio_isvalid(&host->cd_gpio))
 493                 return fdtdec_get_gpio(&host->cd_gpio);
 494
 495         return 1;
 496 }
 497
 498 static int do_mmc_init(int dev_index)
 499 {
 500         struct mmc_host *host;
 501         char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
 502         struct mmc *mmc;
 503
 504         /* DT should have been read & host config filled in */
 505         host = &mmc_host[dev_index];
 506         if (!host->enabled)
 507                 return -1;
 508
 509         debug(" do_mmc_init: index %d, bus width %d "
 510                 "pwr_gpio %d cd_gpio %d\n",
 511                 dev_index, host->width,
 512                 host->pwr_gpio.gpio, host->cd_gpio.gpio);
 513
 514         host->clock = 0;
 515         clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 516
 517         if (fdt_gpio_isvalid(&host->pwr_gpio)) {
 518                 sprintf(gpusage, "SD/MMC%d PWR", dev_index);
 519                 gpio_request(host->pwr_gpio.gpio, gpusage);
 520                 gpio_direction_output(host->pwr_gpio.gpio, 1);
 521                 debug(" Power GPIO name = %s\n", host->pwr_gpio.name);
 522         }
 523
 524         if (fdt_gpio_isvalid(&host->cd_gpio)) {
 525                 sprintf(gpusage, "SD/MMC%d CD", dev_index);
 526                 gpio_request(host->cd_gpio.gpio, gpusage);
 527                 gpio_direction_input(host->cd_gpio.gpio);
 528                 debug(" CD GPIO name = %s\n", host->cd_gpio.name);
 529         }
 530
 531         mmc = &mmc_dev[dev_index];
 532
 533         sprintf(mmc->name, "Tegra SD/MMC");
 534         mmc->priv = host;
 535         mmc->send_cmd = mmc_send_cmd;
 536         mmc->set_ios = mmc_set_ios;
 537         mmc->init = mmc_core_init;
 538         mmc->getcd = tegra_mmc_getcd;
 539         mmc->getwp = NULL;
 540
 541         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 542         mmc->host_caps = 0;
 543         if (host->width == 8)
 544                 mmc->host_caps |= MMC_MODE_8BIT;
 545         if (host->width >= 4)
 546                 mmc->host_caps |= MMC_MODE_4BIT;
 547         mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 548
 549         /*
 550          * min freq is for card identification, and is the highest
 551          *  low-speed SDIO card frequency (actually 400KHz)
 552          * max freq is highest HS eMMC clock as per the SD/MMC spec
 553          *  (actually 52MHz)
 554          */
 555         mmc->f_min = 375000;
 556         mmc->f_max = 48000000;
 557
 558         mmc_register(mmc);
 559
 560         return 0;
 561 }
 562
 563 /**
 564  * Get the host address and peripheral ID for a node.
 565  *
 566  * @param blob          fdt blob
 567  * @param node          Device index (0-3)
 568  * @param host          Structure to fill in (reg, width, mmc_id)
 569  */
 570 static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
 571 {
 572         debug("%s: node = %d\n", __func__, node);
 573
 574         host->enabled = fdtdec_get_is_enabled(blob, node);
 575
 576         host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
 577         if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
 578                 debug("%s: no sdmmc base reg info found\n", __func__);
 579                 return -FDT_ERR_NOTFOUND;
 580         }
 581
 582         host->mmc_id = clock_decode_periph_id(blob, node);
 583         if (host->mmc_id == PERIPH_ID_NONE) {
 584                 debug("%s: could not decode periph id\n", __func__);
 585                 return -FDT_ERR_NOTFOUND;
 586         }
 587
 588         /*
 589          * NOTE: mmc->bus_width is determined by mmc.c dynamically.
 590          * TBD: Override it with this value?
 591          */
 592         host->width = fdtdec_get_int(blob, node, "bus-width", 0);
 593         if (!host->width)
 594                 debug("%s: no sdmmc width found\n", __func__);
 595
 596         /* These GPIOs are optional */
 597         fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
 598         fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio);
 599         fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio);
 600
 601         debug("%s: found controller at %p, width = %d, periph_id = %d\n",
 602                 __func__, host->reg, host->width, host->mmc_id);
 603         return 0;
 604 }
 605
 606 /*
 607  * Process a list of nodes, adding them to our list of SDMMC ports.
 608  *
 609  * @param blob          fdt blob
 610  * @param node_list     list of nodes to process (any <=0 are ignored)
 611  * @param count         number of nodes to process
 612  * @return 0 if ok, -1 on error
 613  */
 614 static int process_nodes(const void *blob, int node_list[], int count)
 615 {
 616         struct mmc_host *host;
 617         int i, node;
 618
 619         debug("%s: count = %d\n", __func__, count);
 620
 621         /* build mmc_host[] for each controller */
 622         for (i = 0; i < count; i++) {
 623                 node = node_list[i];
 624                 if (node <= 0)
 625                         continue;
 626
 627                 host = &mmc_host[i];
 628                 host->id = i;
 629
 630                 if (mmc_get_config(blob, node, host)) {
 631                         printf("%s: failed to decode dev %d\n", __func__, i);
 632                         return -1;
 633                 }
 634                 do_mmc_init(i);
 635         }
 636         return 0;
 637 }
 638
 639 void tegra_mmc_init(void)
 640 {
 641         int node_list[MAX_HOSTS], count;
 642         const void *blob = gd->fdt_blob;
 643         debug("%s entry\n", __func__);
 644
 645         count = fdtdec_find_aliases_for_id(blob, "sdhci",
 646                 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
 647         debug("%s: count of sdhci nodes is %d\n", __func__, count);
 648
 649         if (process_nodes(blob, node_list, count)) {
 650                 printf("%s: Error processing mmc node(s)!\n", __func__);
 651                 return;
 652         }
 653 }