drivers/mmc/sunxi_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2011
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Aaron <leafy.myeh@allwinnertech.com>
   6  *
   7  * MMC driver for allwinner sunxi platform.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <clk.h>
  17 #include <reset.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc.h>
  23 #include <asm-generic/gpio.h>
  24
  25 #ifdef CONFIG_DM_MMC
  26 struct sunxi_mmc_variant {
  27         u16 mclk_offset;
  28 };
  29 #endif
  30
  31 struct sunxi_mmc_plat {
  32         struct mmc_config cfg;
  33         struct mmc mmc;
  34 };
  35
  36 struct sunxi_mmc_priv {
  37         unsigned mmc_no;
  38         uint32_t *mclkreg;
  39         unsigned fatal_err;
  40         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  41         int cd_inverted;                /* Inverted Card Detect */
  42         struct sunxi_mmc *reg;
  43         struct mmc_config cfg;
  44 #ifdef CONFIG_DM_MMC
  45         const struct sunxi_mmc_variant *variant;
  46 #endif
  47 };
  48
  49 #if !CONFIG_IS_ENABLED(DM_MMC)
  50 /* support 4 mmc hosts */
  51 struct sunxi_mmc_priv mmc_host[4];
  52
  53 static int sunxi_mmc_getcd_gpio(int sdc_no)
  54 {
  55         switch (sdc_no) {
  56         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  57         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  58         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  59         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  60         }
  61         return -EINVAL;
  62 }
  63
  64 static int mmc_resource_init(int sdc_no)
  65 {
  66         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  67         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  68         int cd_pin, ret = 0;
  69
  70         debug("init mmc %d resource\n", sdc_no);
  71
  72         switch (sdc_no) {
  73         case 0:
  74                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  75                 priv->mclkreg = &ccm->sd0_clk_cfg;
  76                 break;
  77         case 1:
  78                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  79                 priv->mclkreg = &ccm->sd1_clk_cfg;
  80                 break;
  81         case 2:
  82                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  83                 priv->mclkreg = &ccm->sd2_clk_cfg;
  84                 break;
  85 #ifdef SUNXI_MMC3_BASE
  86         case 3:
  87                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  88                 priv->mclkreg = &ccm->sd3_clk_cfg;
  89                 break;
  90 #endif
  91         default:
  92                 printf("Wrong mmc number %d\n", sdc_no);
  93                 return -1;
  94         }
  95         priv->mmc_no = sdc_no;
  96
  97         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  98         if (cd_pin >= 0) {
  99                 ret = gpio_request(cd_pin, "mmc_cd");
 100                 if (!ret) {
 101                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 102                         ret = gpio_direction_input(cd_pin);
 103                 }
 104         }
 105
 106         return ret;
 107 }
 108 #endif
 109
 110 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 111 {
 112         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 113         bool new_mode = true;
 114         bool calibrate = false;
 115         u32 val = 0;
 116
 117         if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
 118                 new_mode = false;
 119
 120         /* A83T support new mode only on eMMC */
 121         if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
 122                 new_mode = false;
 123
 124 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
 125         calibrate = true;
 126 #endif
 127
 128         if (hz <= 24000000) {
 129                 pll = CCM_MMC_CTRL_OSCM24;
 130                 pll_hz = 24000000;
 131         } else {
 132 #ifdef CONFIG_MACH_SUN9I
 133                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
 134                 pll_hz = clock_get_pll4_periph0();
 135 #elif defined(CONFIG_MACH_SUN50I_H6)
 136                 pll = CCM_MMC_CTRL_PLL6X2;
 137                 pll_hz = clock_get_pll6() * 2;
 138 #else
 139                 pll = CCM_MMC_CTRL_PLL6;
 140                 pll_hz = clock_get_pll6();
 141 #endif
 142         }
 143
 144         div = pll_hz / hz;
 145         if (pll_hz % hz)
 146                 div++;
 147
 148         n = 0;
 149         while (div > 16) {
 150                 n++;
 151                 div = (div + 1) / 2;
 152         }
 153
 154         if (n > 3) {
 155                 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
 156                        hz);
 157                 return -1;
 158         }
 159
 160         /* determine delays */
 161         if (hz <= 400000) {
 162                 oclk_dly = 0;
 163                 sclk_dly = 0;
 164         } else if (hz <= 25000000) {
 165                 oclk_dly = 0;
 166                 sclk_dly = 5;
 167 #ifdef CONFIG_MACH_SUN9I
 168         } else if (hz <= 52000000) {
 169                 oclk_dly = 5;
 170                 sclk_dly = 4;
 171         } else {
 172                 /* hz > 52000000 */
 173                 oclk_dly = 2;
 174                 sclk_dly = 4;
 175 #else
 176         } else if (hz <= 52000000) {
 177                 oclk_dly = 3;
 178                 sclk_dly = 4;
 179         } else {
 180                 /* hz > 52000000 */
 181                 oclk_dly = 1;
 182                 sclk_dly = 4;
 183 #endif
 184         }
 185
 186         if (new_mode) {
 187 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
 188 #ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
 189                 val = CCM_MMC_CTRL_MODE_SEL_NEW;
 190 #endif
 191                 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 192 #endif
 193         } else if (!calibrate) {
 194                 /*
 195                  * Use hardcoded delay values if controller doesn't support
 196                  * calibration
 197                  */
 198                 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 199                         CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 200         }
 201
 202         writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
 203                CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
 204
 205         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 206               priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
 207
 208         return 0;
 209 }
 210
 211 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
 212 {
 213         unsigned int cmd;
 214         unsigned timeout_msecs = 2000;
 215         unsigned long start = get_timer(0);
 216
 217         cmd = SUNXI_MMC_CMD_START |
 218               SUNXI_MMC_CMD_UPCLK_ONLY |
 219               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 220
 221         writel(cmd, &priv->reg->cmd);
 222         while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
 223                 if (get_timer(start) > timeout_msecs)
 224                         return -1;
 225         }
 226
 227         /* clock update sets various irq status bits, clear these */
 228         writel(readl(&priv->reg->rint), &priv->reg->rint);
 229
 230         return 0;
 231 }
 232
 233 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 234 {
 235         unsigned rval = readl(&priv->reg->clkcr);
 236
 237         /* Disable Clock */
 238         rval &= ~SUNXI_MMC_CLK_ENABLE;
 239         writel(rval, &priv->reg->clkcr);
 240         if (mmc_update_clk(priv))
 241                 return -1;
 242
 243         /* Set mod_clk to new rate */
 244         if (mmc_set_mod_clk(priv, mmc->clock))
 245                 return -1;
 246
 247         /* Clear internal divider */
 248         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 249         writel(rval, &priv->reg->clkcr);
 250
 251 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
 252         /* A64 supports calibration of delays on MMC controller and we
 253          * have to set delay of zero before starting calibration.
 254          * Allwinner BSP driver sets a delay only in the case of
 255          * using HS400 which is not supported by mainline U-Boot or
 256          * Linux at the moment
 257          */
 258         writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
 259 #endif
 260
 261         /* Re-enable Clock */
 262         rval |= SUNXI_MMC_CLK_ENABLE;
 263         writel(rval, &priv->reg->clkcr);
 264         if (mmc_update_clk(priv))
 265                 return -1;
 266
 267         return 0;
 268 }
 269
 270 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
 271                                     struct mmc *mmc)
 272 {
 273         debug("set ios: bus_width: %x, clock: %d\n",
 274               mmc->bus_width, mmc->clock);
 275
 276         /* Change clock first */
 277         if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
 278                 priv->fatal_err = 1;
 279                 return -EINVAL;
 280         }
 281
 282         /* Change bus width */
 283         if (mmc->bus_width == 8)
 284                 writel(0x2, &priv->reg->width);
 285         else if (mmc->bus_width == 4)
 286                 writel(0x1, &priv->reg->width);
 287         else
 288                 writel(0x0, &priv->reg->width);
 289
 290         return 0;
 291 }
 292
 293 #if !CONFIG_IS_ENABLED(DM_MMC)
 294 static int sunxi_mmc_core_init(struct mmc *mmc)
 295 {
 296         struct sunxi_mmc_priv *priv = mmc->priv;
 297
 298         /* Reset controller */
 299         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 300         udelay(1000);
 301
 302         return 0;
 303 }
 304 #endif
 305
 306 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 307                                  struct mmc_data *data)
 308 {
 309         const int reading = !!(data->flags & MMC_DATA_READ);
 310         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 311                                               SUNXI_MMC_STATUS_FIFO_FULL;
 312         unsigned i;
 313         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 314         unsigned byte_cnt = data->blocksize * data->blocks;
 315         unsigned timeout_msecs = byte_cnt >> 8;
 316         unsigned long  start;
 317
 318         if (timeout_msecs < 2000)
 319                 timeout_msecs = 2000;
 320
 321         /* Always read / write data through the CPU */
 322         setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 323
 324         start = get_timer(0);
 325
 326         for (i = 0; i < (byte_cnt >> 2); i++) {
 327                 while (readl(&priv->reg->status) & status_bit) {
 328                         if (get_timer(start) > timeout_msecs)
 329                                 return -1;
 330                 }
 331
 332                 if (reading)
 333                         buff[i] = readl(&priv->reg->fifo);
 334                 else
 335                         writel(buff[i], &priv->reg->fifo);
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 342                          uint timeout_msecs, uint done_bit, const char *what)
 343 {
 344         unsigned int status;
 345         unsigned long start = get_timer(0);
 346
 347         do {
 348                 status = readl(&priv->reg->rint);
 349                 if ((get_timer(start) > timeout_msecs) ||
 350                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 351                         debug("%s timeout %x\n", what,
 352                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 353                         return -ETIMEDOUT;
 354                 }
 355         } while (!(status & done_bit));
 356
 357         return 0;
 358 }
 359
 360 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 361                                      struct mmc *mmc, struct mmc_cmd *cmd,
 362                                      struct mmc_data *data)
 363 {
 364         unsigned int cmdval = SUNXI_MMC_CMD_START;
 365         unsigned int timeout_msecs;
 366         int error = 0;
 367         unsigned int status = 0;
 368         unsigned int bytecnt = 0;
 369
 370         if (priv->fatal_err)
 371                 return -1;
 372         if (cmd->resp_type & MMC_RSP_BUSY)
 373                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 374         if (cmd->cmdidx == 12)
 375                 return 0;
 376
 377         if (!cmd->cmdidx)
 378                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 379         if (cmd->resp_type & MMC_RSP_PRESENT)
 380                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 381         if (cmd->resp_type & MMC_RSP_136)
 382                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 383         if (cmd->resp_type & MMC_RSP_CRC)
 384                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 385
 386         if (data) {
 387                 if ((u32)(long)data->dest & 0x3) {
 388                         error = -1;
 389                         goto out;
 390                 }
 391
 392                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 393                 if (data->flags & MMC_DATA_WRITE)
 394                         cmdval |= SUNXI_MMC_CMD_WRITE;
 395                 if (data->blocks > 1)
 396                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 397                 writel(data->blocksize, &priv->reg->blksz);
 398                 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 399         }
 400
 401         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
 402               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 403         writel(cmd->cmdarg, &priv->reg->arg);
 404
 405         if (!data)
 406                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 407
 408         /*
 409          * transfer data and check status
 410          * STATREG[2] : FIFO empty
 411          * STATREG[3] : FIFO full
 412          */
 413         if (data) {
 414                 int ret = 0;
 415
 416                 bytecnt = data->blocksize * data->blocks;
 417                 debug("trans data %d bytes\n", bytecnt);
 418                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 419                 ret = mmc_trans_data_by_cpu(priv, mmc, data);
 420                 if (ret) {
 421                         error = readl(&priv->reg->rint) &
 422                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 423                         error = -ETIMEDOUT;
 424                         goto out;
 425                 }
 426         }
 427
 428         error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
 429                               "cmd");
 430         if (error)
 431                 goto out;
 432
 433         if (data) {
 434                 timeout_msecs = 120;
 435                 debug("cacl timeout %x msec\n", timeout_msecs);
 436                 error = mmc_rint_wait(priv, mmc, timeout_msecs,
 437                                       data->blocks > 1 ?
 438                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 439                                       SUNXI_MMC_RINT_DATA_OVER,
 440                                       "data");
 441                 if (error)
 442                         goto out;
 443         }
 444
 445         if (cmd->resp_type & MMC_RSP_BUSY) {
 446                 unsigned long start = get_timer(0);
 447                 timeout_msecs = 2000;
 448
 449                 do {
 450                         status = readl(&priv->reg->status);
 451                         if (get_timer(start) > timeout_msecs) {
 452                                 debug("busy timeout\n");
 453                                 error = -ETIMEDOUT;
 454                                 goto out;
 455                         }
 456                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 457         }
 458
 459         if (cmd->resp_type & MMC_RSP_136) {
 460                 cmd->response[0] = readl(&priv->reg->resp3);
 461                 cmd->response[1] = readl(&priv->reg->resp2);
 462                 cmd->response[2] = readl(&priv->reg->resp1);
 463                 cmd->response[3] = readl(&priv->reg->resp0);
 464                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 465                       cmd->response[3], cmd->response[2],
 466                       cmd->response[1], cmd->response[0]);
 467         } else {
 468                 cmd->response[0] = readl(&priv->reg->resp0);
 469                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 470         }
 471 out:
 472         if (error < 0) {
 473                 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 474                 mmc_update_clk(priv);
 475         }
 476         writel(0xffffffff, &priv->reg->rint);
 477         writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 478                &priv->reg->gctrl);
 479
 480         return error;
 481 }
 482
 483 #if !CONFIG_IS_ENABLED(DM_MMC)
 484 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
 485 {
 486         struct sunxi_mmc_priv *priv = mmc->priv;
 487
 488         return sunxi_mmc_set_ios_common(priv, mmc);
 489 }
 490
 491 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
 492                                      struct mmc_data *data)
 493 {
 494         struct sunxi_mmc_priv *priv = mmc->priv;
 495
 496         return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
 497 }
 498
 499 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
 500 {
 501         struct sunxi_mmc_priv *priv = mmc->priv;
 502         int cd_pin;
 503
 504         cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
 505         if (cd_pin < 0)
 506                 return 1;
 507
 508         return !gpio_get_value(cd_pin);
 509 }
 510
 511 static const struct mmc_ops sunxi_mmc_ops = {
 512         .send_cmd       = sunxi_mmc_send_cmd_legacy,
 513         .set_ios        = sunxi_mmc_set_ios_legacy,
 514         .init           = sunxi_mmc_core_init,
 515         .getcd          = sunxi_mmc_getcd_legacy,
 516 };
 517
 518 struct mmc *sunxi_mmc_init(int sdc_no)
 519 {
 520         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 521         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
 522         struct mmc_config *cfg = &priv->cfg;
 523         int ret;
 524
 525         memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
 526
 527         cfg->name = "SUNXI SD/MMC";
 528         cfg->ops  = &sunxi_mmc_ops;
 529
 530         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 531         cfg->host_caps = MMC_MODE_4BIT;
 532 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
 533         if (sdc_no == 2)
 534                 cfg->host_caps = MMC_MODE_8BIT;
 535 #endif
 536         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 537         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 538
 539         cfg->f_min = 400000;
 540         cfg->f_max = 52000000;
 541
 542         if (mmc_resource_init(sdc_no) != 0)
 543                 return NULL;
 544
 545         /* config ahb clock */
 546         debug("init mmc %d clock and io\n", sdc_no);
 547 #if !defined(CONFIG_MACH_SUN50I_H6)
 548         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 549
 550 #ifdef CONFIG_SUNXI_GEN_SUN6I
 551         /* unassert reset */
 552         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 553 #endif
 554 #if defined(CONFIG_MACH_SUN9I)
 555         /* sun9i has a mmc-common module, also set the gate and reset there */
 556         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 557                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 558 #endif
 559 #else /* CONFIG_MACH_SUN50I_H6 */
 560         setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
 561         /* unassert reset */
 562         setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
 563 #endif
 564         ret = mmc_set_mod_clk(priv, 24000000);
 565         if (ret)
 566                 return NULL;
 567
 568         return mmc_create(cfg, priv);
 569 }
 570 #else
 571
 572 static int sunxi_mmc_set_ios(struct udevice *dev)
 573 {
 574         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 575         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 576
 577         return sunxi_mmc_set_ios_common(priv, &plat->mmc);
 578 }
 579
 580 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 581                               struct mmc_data *data)
 582 {
 583         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 584         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 585
 586         return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
 587 }
 588
 589 static int sunxi_mmc_getcd(struct udevice *dev)
 590 {
 591         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 592
 593         if (dm_gpio_is_valid(&priv->cd_gpio)) {
 594                 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
 595
 596                 return cd_state ^ priv->cd_inverted;
 597         }
 598         return 1;
 599 }
 600
 601 static const struct dm_mmc_ops sunxi_mmc_ops = {
 602         .send_cmd       = sunxi_mmc_send_cmd,
 603         .set_ios        = sunxi_mmc_set_ios,
 604         .get_cd         = sunxi_mmc_getcd,
 605 };
 606
 607 static int sunxi_mmc_probe(struct udevice *dev)
 608 {
 609         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 610         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 611         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 612         struct reset_ctl_bulk reset_bulk;
 613         struct clk gate_clk;
 614         struct mmc_config *cfg = &plat->cfg;
 615         struct ofnode_phandle_args args;
 616         u32 *ccu_reg;
 617         int bus_width, ret;
 618
 619         cfg->name = dev->name;
 620         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 621
 622         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 623         cfg->host_caps = 0;
 624         if (bus_width == 8)
 625                 cfg->host_caps |= MMC_MODE_8BIT;
 626         if (bus_width >= 4)
 627                 cfg->host_caps |= MMC_MODE_4BIT;
 628         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 629         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 630
 631         cfg->f_min = 400000;
 632         cfg->f_max = 52000000;
 633
 634         priv->reg = (void *)dev_read_addr(dev);
 635         priv->variant =
 636                 (const struct sunxi_mmc_variant *)dev_get_driver_data(dev);
 637
 638         /* We don't have a sunxi clock driver so find the clock address here */
 639         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 640                                           1, &args);
 641         if (ret)
 642                 return ret;
 643         ccu_reg = (u32 *)ofnode_get_addr(args.node);
 644
 645         priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
 646         priv->mclkreg = (void *)ccu_reg +
 647                         (priv->variant->mclk_offset + (priv->mmc_no * 4));
 648
 649         ret = clk_get_by_name(dev, "ahb", &gate_clk);
 650         if (!ret)
 651                 clk_enable(&gate_clk);
 652
 653         ret = reset_get_bulk(dev, &reset_bulk);
 654         if (!ret)
 655                 reset_deassert_bulk(&reset_bulk);
 656
 657         ret = mmc_set_mod_clk(priv, 24000000);
 658         if (ret)
 659                 return ret;
 660
 661         /* This GPIO is optional */
 662         if (!dev_read_bool(dev, "non-removable") &&
 663             !gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 664                                   GPIOD_IS_IN)) {
 665                 int cd_pin = gpio_get_number(&priv->cd_gpio);
 666
 667                 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 668         }
 669
 670         /* Check if card detect is inverted */
 671         priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
 672
 673         upriv->mmc = &plat->mmc;
 674
 675         /* Reset controller */
 676         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 677         udelay(1000);
 678
 679         return 0;
 680 }
 681
 682 static int sunxi_mmc_bind(struct udevice *dev)
 683 {
 684         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 685
 686         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 687 }
 688
 689 static const struct sunxi_mmc_variant sun4i_a10_variant = {
 690         .mclk_offset = 0x88,
 691 };
 692
 693 static const struct sunxi_mmc_variant sun9i_a80_variant = {
 694         .mclk_offset = 0x410,
 695 };
 696
 697 static const struct sunxi_mmc_variant sun50i_h6_variant = {
 698         .mclk_offset = 0x830,
 699 };
 700
 701 static const struct udevice_id sunxi_mmc_ids[] = {
 702         {
 703           .compatible = "allwinner,sun4i-a10-mmc",
 704           .data = (ulong)&sun4i_a10_variant,
 705         },
 706         {
 707           .compatible = "allwinner,sun5i-a13-mmc",
 708           .data = (ulong)&sun4i_a10_variant,
 709         },
 710         {
 711           .compatible = "allwinner,sun7i-a20-mmc",
 712           .data = (ulong)&sun4i_a10_variant,
 713         },
 714         {
 715           .compatible = "allwinner,sun8i-a83t-emmc",
 716           .data = (ulong)&sun4i_a10_variant,
 717         },
 718         {
 719           .compatible = "allwinner,sun9i-a80-mmc",
 720           .data = (ulong)&sun9i_a80_variant,
 721         },
 722         {
 723           .compatible = "allwinner,sun50i-a64-mmc",
 724           .data = (ulong)&sun4i_a10_variant,
 725         },
 726         {
 727           .compatible = "allwinner,sun50i-a64-emmc",
 728           .data = (ulong)&sun4i_a10_variant,
 729         },
 730         {
 731           .compatible = "allwinner,sun50i-h6-mmc",
 732           .data = (ulong)&sun50i_h6_variant,
 733         },
 734         {
 735           .compatible = "allwinner,sun50i-h6-emmc",
 736           .data = (ulong)&sun50i_h6_variant,
 737         },
 738         { /* sentinel */ }
 739 };
 740
 741 U_BOOT_DRIVER(sunxi_mmc_drv) = {
 742         .name           = "sunxi_mmc",
 743         .id             = UCLASS_MMC,
 744         .of_match       = sunxi_mmc_ids,
 745         .bind           = sunxi_mmc_bind,
 746         .probe          = sunxi_mmc_probe,
 747         .ops            = &sunxi_mmc_ops,
 748         .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
 749         .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
 750 };
 751 #endif