drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <asm/cache.h>
  15 #include <linux/delay.h>
  16 #include <linux/libfdt.h>
  17 #include <mmc.h>
  18 #include <reset.h>
  19 #include <asm/io.h>
  20 #include <asm/gpio.h>
  21 #include <linux/iopoll.h>
  22 #include <watchdog.h>
  23
  24 struct stm32_sdmmc2_plat {
  25         struct mmc_config cfg;
  26         struct mmc mmc;
  27 };
  28
  29 struct stm32_sdmmc2_priv {
  30         fdt_addr_t base;
  31         struct clk clk;
  32         struct reset_ctl reset_ctl;
  33         struct gpio_desc cd_gpio;
  34         u32 clk_reg_msk;
  35         u32 pwr_reg_msk;
  36 };
  37
  38 struct stm32_sdmmc2_ctx {
  39         u32 cache_start;
  40         u32 cache_end;
  41         u32 data_length;
  42         bool dpsm_abort;
  43 };
  44
  45 /* SDMMC REGISTERS OFFSET */
  46 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  47 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  48 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  49 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  50 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  51 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  52 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  53 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  54 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  55 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  56 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  57 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  58 #define SDMMC_STA               0x34    /* SDMMC status                    */
  59 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  60 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  61 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  62 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  63
  64 /* SDMMC_POWER register */
  65 #define SDMMC_POWER_PWRCTRL_MASK        GENMASK(1, 0)
  66 #define SDMMC_POWER_PWRCTRL_OFF         0
  67 #define SDMMC_POWER_PWRCTRL_CYCLE       2
  68 #define SDMMC_POWER_PWRCTRL_ON          3
  69 #define SDMMC_POWER_VSWITCH             BIT(2)
  70 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  71 #define SDMMC_POWER_DIRPOL              BIT(4)
  72
  73 /* SDMMC_CLKCR register */
  74 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  75 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  76 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  77 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  78 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  79 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  80 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  81 #define SDMMC_CLKCR_DDR                 BIT(18)
  82 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  83 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  84 #define SDMMC_CLKCR_SELCLKRX_CK         0
  85 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  86 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  87
  88 /* SDMMC_CMD register */
  89 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  90 #define SDMMC_CMD_CMDTRANS              BIT(6)
  91 #define SDMMC_CMD_CMDSTOP               BIT(7)
  92 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
  93 #define SDMMC_CMD_WAITRESP_0            BIT(8)
  94 #define SDMMC_CMD_WAITRESP_1            BIT(9)
  95 #define SDMMC_CMD_WAITINT               BIT(10)
  96 #define SDMMC_CMD_WAITPEND              BIT(11)
  97 #define SDMMC_CMD_CPSMEN                BIT(12)
  98 #define SDMMC_CMD_DTHOLD                BIT(13)
  99 #define SDMMC_CMD_BOOTMODE              BIT(14)
 100 #define SDMMC_CMD_BOOTEN                BIT(15)
 101 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
 102
 103 /* SDMMC_DCTRL register */
 104 #define SDMMC_DCTRL_DTEN                BIT(0)
 105 #define SDMMC_DCTRL_DTDIR               BIT(1)
 106 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
 107 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
 108 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 109 #define SDMMC_DCTRL_RWSTART             BIT(8)
 110 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 111 #define SDMMC_DCTRL_RWMOD               BIT(10)
 112 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 113 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 114 #define SDMMC_DCTRL_FIFORST             BIT(13)
 115
 116 /* SDMMC_STA register */
 117 #define SDMMC_STA_CCRCFAIL              BIT(0)
 118 #define SDMMC_STA_DCRCFAIL              BIT(1)
 119 #define SDMMC_STA_CTIMEOUT              BIT(2)
 120 #define SDMMC_STA_DTIMEOUT              BIT(3)
 121 #define SDMMC_STA_TXUNDERR              BIT(4)
 122 #define SDMMC_STA_RXOVERR               BIT(5)
 123 #define SDMMC_STA_CMDREND               BIT(6)
 124 #define SDMMC_STA_CMDSENT               BIT(7)
 125 #define SDMMC_STA_DATAEND               BIT(8)
 126 #define SDMMC_STA_DHOLD                 BIT(9)
 127 #define SDMMC_STA_DBCKEND               BIT(10)
 128 #define SDMMC_STA_DABORT                BIT(11)
 129 #define SDMMC_STA_DPSMACT               BIT(12)
 130 #define SDMMC_STA_CPSMACT               BIT(13)
 131 #define SDMMC_STA_TXFIFOHE              BIT(14)
 132 #define SDMMC_STA_RXFIFOHF              BIT(15)
 133 #define SDMMC_STA_TXFIFOF               BIT(16)
 134 #define SDMMC_STA_RXFIFOF               BIT(17)
 135 #define SDMMC_STA_TXFIFOE               BIT(18)
 136 #define SDMMC_STA_RXFIFOE               BIT(19)
 137 #define SDMMC_STA_BUSYD0                BIT(20)
 138 #define SDMMC_STA_BUSYD0END             BIT(21)
 139 #define SDMMC_STA_SDMMCIT               BIT(22)
 140 #define SDMMC_STA_ACKFAIL               BIT(23)
 141 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 142 #define SDMMC_STA_VSWEND                BIT(25)
 143 #define SDMMC_STA_CKSTOP                BIT(26)
 144 #define SDMMC_STA_IDMATE                BIT(27)
 145 #define SDMMC_STA_IDMABTC               BIT(28)
 146
 147 /* SDMMC_ICR register */
 148 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 149 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 150 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 151 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 152 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 153 #define SDMMC_ICR_RXOVERRC              BIT(5)
 154 #define SDMMC_ICR_CMDRENDC              BIT(6)
 155 #define SDMMC_ICR_CMDSENTC              BIT(7)
 156 #define SDMMC_ICR_DATAENDC              BIT(8)
 157 #define SDMMC_ICR_DHOLDC                BIT(9)
 158 #define SDMMC_ICR_DBCKENDC              BIT(10)
 159 #define SDMMC_ICR_DABORTC               BIT(11)
 160 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 161 #define SDMMC_ICR_SDMMCITC              BIT(22)
 162 #define SDMMC_ICR_ACKFAILC              BIT(23)
 163 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 164 #define SDMMC_ICR_VSWENDC               BIT(25)
 165 #define SDMMC_ICR_CKSTOPC               BIT(26)
 166 #define SDMMC_ICR_IDMATEC               BIT(27)
 167 #define SDMMC_ICR_IDMABTCC              BIT(28)
 168 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 169
 170 /* SDMMC_MASK register */
 171 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 172 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 173 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 174 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 175 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 176 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 177 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 178 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 179 #define SDMMC_MASK_DATAENDIE            BIT(8)
 180 #define SDMMC_MASK_DHOLDIE              BIT(9)
 181 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 182 #define SDMMC_MASK_DABORTIE             BIT(11)
 183 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 184 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 185 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 186 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 187 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 188 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 189 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 190 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 191 #define SDMMC_MASK_VSWENDIE             BIT(25)
 192 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 193 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 194
 195 /* SDMMC_IDMACTRL register */
 196 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 197
 198 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 199 #define SDMMC_BUSYD0END_TIMEOUT_US      2000000
 200
 201 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
 202                                     struct mmc_data *data,
 203                                     struct stm32_sdmmc2_ctx *ctx)
 204 {
 205         u32 data_ctrl, idmabase0;
 206
 207         /* Configure the SDMMC DPSM (Data Path State Machine) */
 208         data_ctrl = (__ilog2(data->blocksize) <<
 209                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 210                     SDMMC_DCTRL_DBLOCKSIZE;
 211
 212         if (data->flags & MMC_DATA_READ) {
 213                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 214                 idmabase0 = (u32)data->dest;
 215         } else {
 216                 idmabase0 = (u32)data->src;
 217         }
 218
 219         /* Set the SDMMC DataLength value */
 220         writel(ctx->data_length, priv->base + SDMMC_DLEN);
 221
 222         /* Write to SDMMC DCTRL */
 223         writel(data_ctrl, priv->base + SDMMC_DCTRL);
 224
 225         /* Cache align */
 226         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 227         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 228                                  ARCH_DMA_MINALIGN);
 229
 230         /*
 231          * Flush data cache before DMA start (clean and invalidate)
 232          * Clean also needed for read
 233          * Avoid issue on buffer not cached-aligned
 234          */
 235         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 236
 237         /* Enable internal DMA */
 238         writel(idmabase0, priv->base + SDMMC_IDMABASE0);
 239         writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
 240 }
 241
 242 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
 243                                    struct mmc_cmd *cmd, u32 cmd_param,
 244                                    struct stm32_sdmmc2_ctx *ctx)
 245 {
 246         u32 timeout = 0;
 247
 248         if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 249                 writel(0, priv->base + SDMMC_CMD);
 250
 251         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 252         if (cmd->resp_type & MMC_RSP_PRESENT) {
 253                 if (cmd->resp_type & MMC_RSP_136)
 254                         cmd_param |= SDMMC_CMD_WAITRESP;
 255                 else if (cmd->resp_type & MMC_RSP_CRC)
 256                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 257                 else
 258                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 259         }
 260
 261         /*
 262          * SDMMC_DTIME must be set in two case:
 263          * - on data transfert.
 264          * - on busy request.
 265          * If not done or too short, the dtimeout flag occurs and DPSM stays
 266          * enabled/busy and waits for abort (stop transmission cmd).
 267          * Next data command is not possible whereas DPSM is activated.
 268          */
 269         if (ctx->data_length) {
 270                 timeout = SDMMC_CMD_TIMEOUT;
 271         } else {
 272                 writel(0, priv->base + SDMMC_DCTRL);
 273
 274                 if (cmd->resp_type & MMC_RSP_BUSY)
 275                         timeout = SDMMC_CMD_TIMEOUT;
 276         }
 277
 278         /* Set the SDMMC Data TimeOut value */
 279         writel(timeout, priv->base + SDMMC_DTIMER);
 280
 281         /* Clear flags */
 282         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 283
 284         /* Set SDMMC argument value */
 285         writel(cmd->cmdarg, priv->base + SDMMC_ARG);
 286
 287         /* Set SDMMC command parameters */
 288         writel(cmd_param, priv->base + SDMMC_CMD);
 289 }
 290
 291 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
 292                                 struct mmc_cmd *cmd,
 293                                 struct stm32_sdmmc2_ctx *ctx)
 294 {
 295         u32 mask = SDMMC_STA_CTIMEOUT;
 296         u32 status;
 297         int ret;
 298
 299         if (cmd->resp_type & MMC_RSP_PRESENT) {
 300                 mask |= SDMMC_STA_CMDREND;
 301                 if (cmd->resp_type & MMC_RSP_CRC)
 302                         mask |= SDMMC_STA_CCRCFAIL;
 303         } else {
 304                 mask |= SDMMC_STA_CMDSENT;
 305         }
 306
 307         /* Polling status register */
 308         ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
 309                                  10000);
 310
 311         if (ret < 0) {
 312                 debug("%s: timeout reading SDMMC_STA register\n", __func__);
 313                 ctx->dpsm_abort = true;
 314                 return ret;
 315         }
 316
 317         /* Check status */
 318         if (status & SDMMC_STA_CTIMEOUT) {
 319                 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 320                       __func__, status, cmd->cmdidx);
 321                 ctx->dpsm_abort = true;
 322                 return -ETIMEDOUT;
 323         }
 324
 325         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 326                 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 327                       __func__, status, cmd->cmdidx);
 328                 ctx->dpsm_abort = true;
 329                 return -EILSEQ;
 330         }
 331
 332         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 333                 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
 334                 if (cmd->resp_type & MMC_RSP_136) {
 335                         cmd->response[1] = readl(priv->base + SDMMC_RESP2);
 336                         cmd->response[2] = readl(priv->base + SDMMC_RESP3);
 337                         cmd->response[3] = readl(priv->base + SDMMC_RESP4);
 338                 }
 339
 340                 /* Wait for BUSYD0END flag if busy status is detected */
 341                 if (cmd->resp_type & MMC_RSP_BUSY &&
 342                     status & SDMMC_STA_BUSYD0) {
 343                         mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
 344
 345                         /* Polling status register */
 346                         ret = readl_poll_timeout(priv->base + SDMMC_STA,
 347                                                  status, status & mask,
 348                                                  SDMMC_BUSYD0END_TIMEOUT_US);
 349
 350                         if (ret < 0) {
 351                                 debug("%s: timeout reading SDMMC_STA\n",
 352                                       __func__);
 353                                 ctx->dpsm_abort = true;
 354                                 return ret;
 355                         }
 356
 357                         if (status & SDMMC_STA_DTIMEOUT) {
 358                                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
 359                                       __func__, status);
 360                                 ctx->dpsm_abort = true;
 361                                 return -ETIMEDOUT;
 362                         }
 363                 }
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
 370                                  struct mmc_cmd *cmd,
 371                                  struct mmc_data *data,
 372                                  struct stm32_sdmmc2_ctx *ctx)
 373 {
 374         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 375                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 376         u32 status;
 377
 378         if (data->flags & MMC_DATA_READ)
 379                 mask |= SDMMC_STA_RXOVERR;
 380         else
 381                 mask |= SDMMC_STA_TXUNDERR;
 382
 383         status = readl(priv->base + SDMMC_STA);
 384         while (!(status & mask))
 385                 status = readl(priv->base + SDMMC_STA);
 386
 387         /*
 388          * Need invalidate the dcache again to avoid any
 389          * cache-refill during the DMA operations (pre-fetching)
 390          */
 391         if (data->flags & MMC_DATA_READ)
 392                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 393
 394         if (status & SDMMC_STA_DCRCFAIL) {
 395                 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 396                       __func__, status, cmd->cmdidx);
 397                 if (readl(priv->base + SDMMC_DCOUNT))
 398                         ctx->dpsm_abort = true;
 399                 return -EILSEQ;
 400         }
 401
 402         if (status & SDMMC_STA_DTIMEOUT) {
 403                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 404                       __func__, status, cmd->cmdidx);
 405                 ctx->dpsm_abort = true;
 406                 return -ETIMEDOUT;
 407         }
 408
 409         if (status & SDMMC_STA_TXUNDERR) {
 410                 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 411                       __func__, status, cmd->cmdidx);
 412                 ctx->dpsm_abort = true;
 413                 return -EIO;
 414         }
 415
 416         if (status & SDMMC_STA_RXOVERR) {
 417                 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 418                       __func__, status, cmd->cmdidx);
 419                 ctx->dpsm_abort = true;
 420                 return -EIO;
 421         }
 422
 423         if (status & SDMMC_STA_IDMATE) {
 424                 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 425                       __func__, status, cmd->cmdidx);
 426                 ctx->dpsm_abort = true;
 427                 return -EIO;
 428         }
 429
 430         return 0;
 431 }
 432
 433 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 434                                  struct mmc_data *data)
 435 {
 436         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 437         struct stm32_sdmmc2_ctx ctx;
 438         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 439         int ret, retry = 3;
 440
 441         WATCHDOG_RESET();
 442
 443 retry_cmd:
 444         ctx.data_length = 0;
 445         ctx.dpsm_abort = false;
 446
 447         if (data) {
 448                 ctx.data_length = data->blocks * data->blocksize;
 449                 stm32_sdmmc2_start_data(priv, data, &ctx);
 450         }
 451
 452         stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
 453
 454         debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
 455               __func__, cmd->cmdidx,
 456               data ? ctx.data_length : 0, (unsigned int)data);
 457
 458         ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
 459
 460         if (data && !ret)
 461                 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
 462
 463         /* Clear flags */
 464         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 465         if (data)
 466                 writel(0x0, priv->base + SDMMC_IDMACTRL);
 467
 468         /*
 469          * To stop Data Path State Machine, a stop_transmission command
 470          * shall be send on cmd or data errors.
 471          */
 472         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 473                 struct mmc_cmd stop_cmd;
 474
 475                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 476                 stop_cmd.cmdarg = 0;
 477                 stop_cmd.resp_type = MMC_RSP_R1b;
 478
 479                 debug("%s: send STOP command to abort dpsm treatments\n",
 480                       __func__);
 481
 482                 ctx.data_length = 0;
 483
 484                 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
 485                                        SDMMC_CMD_CMDSTOP, &ctx);
 486                 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
 487
 488                 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 489         }
 490
 491         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 492                 printf("%s: cmd %d failed, retrying ...\n",
 493                        __func__, cmd->cmdidx);
 494                 retry--;
 495                 goto retry_cmd;
 496         }
 497
 498         debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
 499
 500         return ret;
 501 }
 502
 503 /*
 504  * Reset the SDMMC with the RCC.SDMMCxRST register bit.
 505  * This will reset the SDMMC to the reset state and the CPSM and DPSM
 506  * to the Idle state. SDMMC is disabled, Signals Hiz.
 507  */
 508 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
 509 {
 510         /* Reset */
 511         reset_assert(&priv->reset_ctl);
 512         udelay(2);
 513         reset_deassert(&priv->reset_ctl);
 514
 515         /* init the needed SDMMC register after reset */
 516         writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
 517 }
 518
 519 /*
 520  * Set the SDMMC in power-cycle state.
 521  * This will make that the SDMMC_D[7:0],
 522  * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
 523  * supplied through the signal lines.
 524  */
 525 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
 526 {
 527         if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
 528             SDMMC_POWER_PWRCTRL_CYCLE)
 529                 return;
 530
 531         stm32_sdmmc2_reset(priv);
 532 }
 533
 534 /*
 535  * set the SDMMC state Power-on: the card is clocked
 536  * manage the SDMMC state control:
 537  * Reset => Power-Cycle => Power-Off => Power
 538  *    PWRCTRL=10     PWCTRL=00    PWCTRL=11
 539  */
 540 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
 541 {
 542         u32 pwrctrl =
 543                 readl(priv->base + SDMMC_POWER) &  SDMMC_POWER_PWRCTRL_MASK;
 544
 545         if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
 546                 return;
 547
 548         /* warning: same PWRCTRL value after reset and for power-off state
 549          * it is the reset state here = the only managed by the driver
 550          */
 551         if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
 552                 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 553                        priv->base + SDMMC_POWER);
 554         }
 555
 556         /*
 557          * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
 558          * switch to Power-Off state: SDMCC disable, signals drive 1
 559          */
 560         writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
 561                priv->base + SDMMC_POWER);
 562
 563         /* After the 1ms delay set the SDMMC to power-on */
 564         mdelay(1);
 565         writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
 566                priv->base + SDMMC_POWER);
 567
 568         /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
 569 }
 570
 571 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 572 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 573 {
 574         struct mmc *mmc = mmc_get_mmc_dev(dev);
 575         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 576         u32 desired = mmc->clock;
 577         u32 sys_clock = clk_get_rate(&priv->clk);
 578         u32 clk = 0;
 579
 580         debug("%s: bus_with = %d, clock = %d\n", __func__,
 581               mmc->bus_width, mmc->clock);
 582
 583         if (mmc->clk_disable)
 584                 stm32_sdmmc2_pwrcycle(priv);
 585         else
 586                 stm32_sdmmc2_pwron(priv);
 587
 588         /*
 589          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 590          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 591          * SDMMCCLK rising edge
 592          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 593          * SDMMCCLK falling edge
 594          */
 595         if (desired && ((sys_clock > desired) ||
 596                         IS_RISING_EDGE(priv->clk_reg_msk))) {
 597                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 598                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 599                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 600         }
 601
 602         if (mmc->bus_width == 4)
 603                 clk |= SDMMC_CLKCR_WIDBUS_4;
 604         if (mmc->bus_width == 8)
 605                 clk |= SDMMC_CLKCR_WIDBUS_8;
 606
 607         writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 608                priv->base + SDMMC_CLKCR);
 609
 610         return 0;
 611 }
 612
 613 static int stm32_sdmmc2_getcd(struct udevice *dev)
 614 {
 615         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 616
 617         debug("stm32_sdmmc2_getcd called\n");
 618
 619         if (dm_gpio_is_valid(&priv->cd_gpio))
 620                 return dm_gpio_get_value(&priv->cd_gpio);
 621
 622         return 1;
 623 }
 624
 625 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
 626 {
 627         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 628
 629         writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 630                priv->base + SDMMC_POWER);
 631
 632         return 0;
 633 }
 634
 635 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 636         .send_cmd = stm32_sdmmc2_send_cmd,
 637         .set_ios = stm32_sdmmc2_set_ios,
 638         .get_cd = stm32_sdmmc2_getcd,
 639         .host_power_cycle = stm32_sdmmc2_host_power_cycle,
 640 };
 641
 642 static int stm32_sdmmc2_probe(struct udevice *dev)
 643 {
 644         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 645         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 646         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 647         struct mmc_config *cfg = &plat->cfg;
 648         int ret;
 649
 650         priv->base = dev_read_addr(dev);
 651         if (priv->base == FDT_ADDR_T_NONE)
 652                 return -EINVAL;
 653
 654         if (dev_read_bool(dev, "st,neg-edge"))
 655                 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 656         if (dev_read_bool(dev, "st,sig-dir"))
 657                 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 658         if (dev_read_bool(dev, "st,use-ckin"))
 659                 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 660
 661         ret = clk_get_by_index(dev, 0, &priv->clk);
 662         if (ret)
 663                 return ret;
 664
 665         ret = clk_enable(&priv->clk);
 666         if (ret)
 667                 goto clk_free;
 668
 669         ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 670         if (ret)
 671                 goto clk_disable;
 672
 673         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 674                              GPIOD_IS_IN);
 675
 676         cfg->f_min = 400000;
 677         cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
 678         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 679         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 680         cfg->name = "STM32 SD/MMC";
 681
 682         cfg->host_caps = 0;
 683         if (cfg->f_max > 25000000)
 684                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 685
 686         switch (dev_read_u32_default(dev, "bus-width", 1)) {
 687         case 8:
 688                 cfg->host_caps |= MMC_MODE_8BIT;
 689                 /* fall through */
 690         case 4:
 691                 cfg->host_caps |= MMC_MODE_4BIT;
 692                 break;
 693         case 1:
 694                 break;
 695         default:
 696                 pr_err("invalid \"bus-width\" property, force to 1\n");
 697         }
 698
 699         upriv->mmc = &plat->mmc;
 700
 701         /* SDMMC init */
 702         stm32_sdmmc2_reset(priv);
 703         return 0;
 704
 705 clk_disable:
 706         clk_disable(&priv->clk);
 707 clk_free:
 708         clk_free(&priv->clk);
 709
 710         return ret;
 711 }
 712
 713 static int stm32_sdmmc_bind(struct udevice *dev)
 714 {
 715         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 716
 717         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 718 }
 719
 720 static const struct udevice_id stm32_sdmmc2_ids[] = {
 721         { .compatible = "st,stm32-sdmmc2" },
 722         { }
 723 };
 724
 725 U_BOOT_DRIVER(stm32_sdmmc2) = {
 726         .name = "stm32_sdmmc2",
 727         .id = UCLASS_MMC,
 728         .of_match = stm32_sdmmc2_ids,
 729         .ops = &stm32_sdmmc2_ops,
 730         .probe = stm32_sdmmc2_probe,
 731         .bind = stm32_sdmmc_bind,
 732         .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
 733         .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
 734 };