drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <asm/cache.h>
  15 #include <linux/libfdt.h>
  16 #include <mmc.h>
  17 #include <reset.h>
  18 #include <asm/io.h>
  19 #include <asm/gpio.h>
  20 #include <linux/iopoll.h>
  21 #include <watchdog.h>
  22
  23 struct stm32_sdmmc2_plat {
  24         struct mmc_config cfg;
  25         struct mmc mmc;
  26 };
  27
  28 struct stm32_sdmmc2_priv {
  29         fdt_addr_t base;
  30         struct clk clk;
  31         struct reset_ctl reset_ctl;
  32         struct gpio_desc cd_gpio;
  33         u32 clk_reg_msk;
  34         u32 pwr_reg_msk;
  35 };
  36
  37 struct stm32_sdmmc2_ctx {
  38         u32 cache_start;
  39         u32 cache_end;
  40         u32 data_length;
  41         bool dpsm_abort;
  42 };
  43
  44 /* SDMMC REGISTERS OFFSET */
  45 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  46 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  47 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  48 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  49 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  50 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  51 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  52 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  53 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  54 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  55 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  56 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  57 #define SDMMC_STA               0x34    /* SDMMC status                    */
  58 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  59 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  60 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  61 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  62
  63 /* SDMMC_POWER register */
  64 #define SDMMC_POWER_PWRCTRL_MASK        GENMASK(1, 0)
  65 #define SDMMC_POWER_PWRCTRL_OFF         0
  66 #define SDMMC_POWER_PWRCTRL_CYCLE       2
  67 #define SDMMC_POWER_PWRCTRL_ON          3
  68 #define SDMMC_POWER_VSWITCH             BIT(2)
  69 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  70 #define SDMMC_POWER_DIRPOL              BIT(4)
  71
  72 /* SDMMC_CLKCR register */
  73 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  74 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  75 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  76 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  77 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  78 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  79 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  80 #define SDMMC_CLKCR_DDR                 BIT(18)
  81 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  82 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  83 #define SDMMC_CLKCR_SELCLKRX_CK         0
  84 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  85 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  86
  87 /* SDMMC_CMD register */
  88 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  89 #define SDMMC_CMD_CMDTRANS              BIT(6)
  90 #define SDMMC_CMD_CMDSTOP               BIT(7)
  91 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
  92 #define SDMMC_CMD_WAITRESP_0            BIT(8)
  93 #define SDMMC_CMD_WAITRESP_1            BIT(9)
  94 #define SDMMC_CMD_WAITINT               BIT(10)
  95 #define SDMMC_CMD_WAITPEND              BIT(11)
  96 #define SDMMC_CMD_CPSMEN                BIT(12)
  97 #define SDMMC_CMD_DTHOLD                BIT(13)
  98 #define SDMMC_CMD_BOOTMODE              BIT(14)
  99 #define SDMMC_CMD_BOOTEN                BIT(15)
 100 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
 101
 102 /* SDMMC_DCTRL register */
 103 #define SDMMC_DCTRL_DTEN                BIT(0)
 104 #define SDMMC_DCTRL_DTDIR               BIT(1)
 105 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
 106 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
 107 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 108 #define SDMMC_DCTRL_RWSTART             BIT(8)
 109 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 110 #define SDMMC_DCTRL_RWMOD               BIT(10)
 111 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 112 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 113 #define SDMMC_DCTRL_FIFORST             BIT(13)
 114
 115 /* SDMMC_STA register */
 116 #define SDMMC_STA_CCRCFAIL              BIT(0)
 117 #define SDMMC_STA_DCRCFAIL              BIT(1)
 118 #define SDMMC_STA_CTIMEOUT              BIT(2)
 119 #define SDMMC_STA_DTIMEOUT              BIT(3)
 120 #define SDMMC_STA_TXUNDERR              BIT(4)
 121 #define SDMMC_STA_RXOVERR               BIT(5)
 122 #define SDMMC_STA_CMDREND               BIT(6)
 123 #define SDMMC_STA_CMDSENT               BIT(7)
 124 #define SDMMC_STA_DATAEND               BIT(8)
 125 #define SDMMC_STA_DHOLD                 BIT(9)
 126 #define SDMMC_STA_DBCKEND               BIT(10)
 127 #define SDMMC_STA_DABORT                BIT(11)
 128 #define SDMMC_STA_DPSMACT               BIT(12)
 129 #define SDMMC_STA_CPSMACT               BIT(13)
 130 #define SDMMC_STA_TXFIFOHE              BIT(14)
 131 #define SDMMC_STA_RXFIFOHF              BIT(15)
 132 #define SDMMC_STA_TXFIFOF               BIT(16)
 133 #define SDMMC_STA_RXFIFOF               BIT(17)
 134 #define SDMMC_STA_TXFIFOE               BIT(18)
 135 #define SDMMC_STA_RXFIFOE               BIT(19)
 136 #define SDMMC_STA_BUSYD0                BIT(20)
 137 #define SDMMC_STA_BUSYD0END             BIT(21)
 138 #define SDMMC_STA_SDMMCIT               BIT(22)
 139 #define SDMMC_STA_ACKFAIL               BIT(23)
 140 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 141 #define SDMMC_STA_VSWEND                BIT(25)
 142 #define SDMMC_STA_CKSTOP                BIT(26)
 143 #define SDMMC_STA_IDMATE                BIT(27)
 144 #define SDMMC_STA_IDMABTC               BIT(28)
 145
 146 /* SDMMC_ICR register */
 147 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 148 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 149 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 150 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 151 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 152 #define SDMMC_ICR_RXOVERRC              BIT(5)
 153 #define SDMMC_ICR_CMDRENDC              BIT(6)
 154 #define SDMMC_ICR_CMDSENTC              BIT(7)
 155 #define SDMMC_ICR_DATAENDC              BIT(8)
 156 #define SDMMC_ICR_DHOLDC                BIT(9)
 157 #define SDMMC_ICR_DBCKENDC              BIT(10)
 158 #define SDMMC_ICR_DABORTC               BIT(11)
 159 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 160 #define SDMMC_ICR_SDMMCITC              BIT(22)
 161 #define SDMMC_ICR_ACKFAILC              BIT(23)
 162 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 163 #define SDMMC_ICR_VSWENDC               BIT(25)
 164 #define SDMMC_ICR_CKSTOPC               BIT(26)
 165 #define SDMMC_ICR_IDMATEC               BIT(27)
 166 #define SDMMC_ICR_IDMABTCC              BIT(28)
 167 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 168
 169 /* SDMMC_MASK register */
 170 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 171 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 172 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 173 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 174 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 175 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 176 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 177 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 178 #define SDMMC_MASK_DATAENDIE            BIT(8)
 179 #define SDMMC_MASK_DHOLDIE              BIT(9)
 180 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 181 #define SDMMC_MASK_DABORTIE             BIT(11)
 182 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 183 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 184 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 185 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 186 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 187 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 188 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 189 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 190 #define SDMMC_MASK_VSWENDIE             BIT(25)
 191 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 192 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 193
 194 /* SDMMC_IDMACTRL register */
 195 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 196
 197 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 198 #define SDMMC_BUSYD0END_TIMEOUT_US      2000000
 199
 200 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
 201                                     struct mmc_data *data,
 202                                     struct stm32_sdmmc2_ctx *ctx)
 203 {
 204         u32 data_ctrl, idmabase0;
 205
 206         /* Configure the SDMMC DPSM (Data Path State Machine) */
 207         data_ctrl = (__ilog2(data->blocksize) <<
 208                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 209                     SDMMC_DCTRL_DBLOCKSIZE;
 210
 211         if (data->flags & MMC_DATA_READ) {
 212                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 213                 idmabase0 = (u32)data->dest;
 214         } else {
 215                 idmabase0 = (u32)data->src;
 216         }
 217
 218         /* Set the SDMMC DataLength value */
 219         writel(ctx->data_length, priv->base + SDMMC_DLEN);
 220
 221         /* Write to SDMMC DCTRL */
 222         writel(data_ctrl, priv->base + SDMMC_DCTRL);
 223
 224         /* Cache align */
 225         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 226         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 227                                  ARCH_DMA_MINALIGN);
 228
 229         /*
 230          * Flush data cache before DMA start (clean and invalidate)
 231          * Clean also needed for read
 232          * Avoid issue on buffer not cached-aligned
 233          */
 234         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 235
 236         /* Enable internal DMA */
 237         writel(idmabase0, priv->base + SDMMC_IDMABASE0);
 238         writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
 239 }
 240
 241 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
 242                                    struct mmc_cmd *cmd, u32 cmd_param,
 243                                    struct stm32_sdmmc2_ctx *ctx)
 244 {
 245         u32 timeout = 0;
 246
 247         if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 248                 writel(0, priv->base + SDMMC_CMD);
 249
 250         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 251         if (cmd->resp_type & MMC_RSP_PRESENT) {
 252                 if (cmd->resp_type & MMC_RSP_136)
 253                         cmd_param |= SDMMC_CMD_WAITRESP;
 254                 else if (cmd->resp_type & MMC_RSP_CRC)
 255                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 256                 else
 257                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 258         }
 259
 260         /*
 261          * SDMMC_DTIME must be set in two case:
 262          * - on data transfert.
 263          * - on busy request.
 264          * If not done or too short, the dtimeout flag occurs and DPSM stays
 265          * enabled/busy and waits for abort (stop transmission cmd).
 266          * Next data command is not possible whereas DPSM is activated.
 267          */
 268         if (ctx->data_length) {
 269                 timeout = SDMMC_CMD_TIMEOUT;
 270         } else {
 271                 writel(0, priv->base + SDMMC_DCTRL);
 272
 273                 if (cmd->resp_type & MMC_RSP_BUSY)
 274                         timeout = SDMMC_CMD_TIMEOUT;
 275         }
 276
 277         /* Set the SDMMC Data TimeOut value */
 278         writel(timeout, priv->base + SDMMC_DTIMER);
 279
 280         /* Clear flags */
 281         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 282
 283         /* Set SDMMC argument value */
 284         writel(cmd->cmdarg, priv->base + SDMMC_ARG);
 285
 286         /* Set SDMMC command parameters */
 287         writel(cmd_param, priv->base + SDMMC_CMD);
 288 }
 289
 290 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
 291                                 struct mmc_cmd *cmd,
 292                                 struct stm32_sdmmc2_ctx *ctx)
 293 {
 294         u32 mask = SDMMC_STA_CTIMEOUT;
 295         u32 status;
 296         int ret;
 297
 298         if (cmd->resp_type & MMC_RSP_PRESENT) {
 299                 mask |= SDMMC_STA_CMDREND;
 300                 if (cmd->resp_type & MMC_RSP_CRC)
 301                         mask |= SDMMC_STA_CCRCFAIL;
 302         } else {
 303                 mask |= SDMMC_STA_CMDSENT;
 304         }
 305
 306         /* Polling status register */
 307         ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
 308                                  10000);
 309
 310         if (ret < 0) {
 311                 debug("%s: timeout reading SDMMC_STA register\n", __func__);
 312                 ctx->dpsm_abort = true;
 313                 return ret;
 314         }
 315
 316         /* Check status */
 317         if (status & SDMMC_STA_CTIMEOUT) {
 318                 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 319                       __func__, status, cmd->cmdidx);
 320                 ctx->dpsm_abort = true;
 321                 return -ETIMEDOUT;
 322         }
 323
 324         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 325                 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 326                       __func__, status, cmd->cmdidx);
 327                 ctx->dpsm_abort = true;
 328                 return -EILSEQ;
 329         }
 330
 331         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 332                 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
 333                 if (cmd->resp_type & MMC_RSP_136) {
 334                         cmd->response[1] = readl(priv->base + SDMMC_RESP2);
 335                         cmd->response[2] = readl(priv->base + SDMMC_RESP3);
 336                         cmd->response[3] = readl(priv->base + SDMMC_RESP4);
 337                 }
 338
 339                 /* Wait for BUSYD0END flag if busy status is detected */
 340                 if (cmd->resp_type & MMC_RSP_BUSY &&
 341                     status & SDMMC_STA_BUSYD0) {
 342                         mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
 343
 344                         /* Polling status register */
 345                         ret = readl_poll_timeout(priv->base + SDMMC_STA,
 346                                                  status, status & mask,
 347                                                  SDMMC_BUSYD0END_TIMEOUT_US);
 348
 349                         if (ret < 0) {
 350                                 debug("%s: timeout reading SDMMC_STA\n",
 351                                       __func__);
 352                                 ctx->dpsm_abort = true;
 353                                 return ret;
 354                         }
 355
 356                         if (status & SDMMC_STA_DTIMEOUT) {
 357                                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
 358                                       __func__, status);
 359                                 ctx->dpsm_abort = true;
 360                                 return -ETIMEDOUT;
 361                         }
 362                 }
 363         }
 364
 365         return 0;
 366 }
 367
 368 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
 369                                  struct mmc_cmd *cmd,
 370                                  struct mmc_data *data,
 371                                  struct stm32_sdmmc2_ctx *ctx)
 372 {
 373         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 374                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 375         u32 status;
 376
 377         if (data->flags & MMC_DATA_READ)
 378                 mask |= SDMMC_STA_RXOVERR;
 379         else
 380                 mask |= SDMMC_STA_TXUNDERR;
 381
 382         status = readl(priv->base + SDMMC_STA);
 383         while (!(status & mask))
 384                 status = readl(priv->base + SDMMC_STA);
 385
 386         /*
 387          * Need invalidate the dcache again to avoid any
 388          * cache-refill during the DMA operations (pre-fetching)
 389          */
 390         if (data->flags & MMC_DATA_READ)
 391                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 392
 393         if (status & SDMMC_STA_DCRCFAIL) {
 394                 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 395                       __func__, status, cmd->cmdidx);
 396                 if (readl(priv->base + SDMMC_DCOUNT))
 397                         ctx->dpsm_abort = true;
 398                 return -EILSEQ;
 399         }
 400
 401         if (status & SDMMC_STA_DTIMEOUT) {
 402                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 403                       __func__, status, cmd->cmdidx);
 404                 ctx->dpsm_abort = true;
 405                 return -ETIMEDOUT;
 406         }
 407
 408         if (status & SDMMC_STA_TXUNDERR) {
 409                 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 410                       __func__, status, cmd->cmdidx);
 411                 ctx->dpsm_abort = true;
 412                 return -EIO;
 413         }
 414
 415         if (status & SDMMC_STA_RXOVERR) {
 416                 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 417                       __func__, status, cmd->cmdidx);
 418                 ctx->dpsm_abort = true;
 419                 return -EIO;
 420         }
 421
 422         if (status & SDMMC_STA_IDMATE) {
 423                 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 424                       __func__, status, cmd->cmdidx);
 425                 ctx->dpsm_abort = true;
 426                 return -EIO;
 427         }
 428
 429         return 0;
 430 }
 431
 432 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 433                                  struct mmc_data *data)
 434 {
 435         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 436         struct stm32_sdmmc2_ctx ctx;
 437         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 438         int ret, retry = 3;
 439
 440         WATCHDOG_RESET();
 441
 442 retry_cmd:
 443         ctx.data_length = 0;
 444         ctx.dpsm_abort = false;
 445
 446         if (data) {
 447                 ctx.data_length = data->blocks * data->blocksize;
 448                 stm32_sdmmc2_start_data(priv, data, &ctx);
 449         }
 450
 451         stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
 452
 453         debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
 454               __func__, cmd->cmdidx,
 455               data ? ctx.data_length : 0, (unsigned int)data);
 456
 457         ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
 458
 459         if (data && !ret)
 460                 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
 461
 462         /* Clear flags */
 463         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 464         if (data)
 465                 writel(0x0, priv->base + SDMMC_IDMACTRL);
 466
 467         /*
 468          * To stop Data Path State Machine, a stop_transmission command
 469          * shall be send on cmd or data errors.
 470          */
 471         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 472                 struct mmc_cmd stop_cmd;
 473
 474                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 475                 stop_cmd.cmdarg = 0;
 476                 stop_cmd.resp_type = MMC_RSP_R1b;
 477
 478                 debug("%s: send STOP command to abort dpsm treatments\n",
 479                       __func__);
 480
 481                 ctx.data_length = 0;
 482
 483                 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
 484                                        SDMMC_CMD_CMDSTOP, &ctx);
 485                 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
 486
 487                 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 488         }
 489
 490         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 491                 printf("%s: cmd %d failed, retrying ...\n",
 492                        __func__, cmd->cmdidx);
 493                 retry--;
 494                 goto retry_cmd;
 495         }
 496
 497         debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
 498
 499         return ret;
 500 }
 501
 502 /*
 503  * Reset the SDMMC with the RCC.SDMMCxRST register bit.
 504  * This will reset the SDMMC to the reset state and the CPSM and DPSM
 505  * to the Idle state. SDMMC is disabled, Signals Hiz.
 506  */
 507 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
 508 {
 509         /* Reset */
 510         reset_assert(&priv->reset_ctl);
 511         udelay(2);
 512         reset_deassert(&priv->reset_ctl);
 513
 514         /* init the needed SDMMC register after reset */
 515         writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
 516 }
 517
 518 /*
 519  * Set the SDMMC in power-cycle state.
 520  * This will make that the SDMMC_D[7:0],
 521  * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
 522  * supplied through the signal lines.
 523  */
 524 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
 525 {
 526         if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
 527             SDMMC_POWER_PWRCTRL_CYCLE)
 528                 return;
 529
 530         stm32_sdmmc2_reset(priv);
 531 }
 532
 533 /*
 534  * set the SDMMC state Power-on: the card is clocked
 535  * manage the SDMMC state control:
 536  * Reset => Power-Cycle => Power-Off => Power
 537  *    PWRCTRL=10     PWCTRL=00    PWCTRL=11
 538  */
 539 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
 540 {
 541         u32 pwrctrl =
 542                 readl(priv->base + SDMMC_POWER) &  SDMMC_POWER_PWRCTRL_MASK;
 543
 544         if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
 545                 return;
 546
 547         /* warning: same PWRCTRL value after reset and for power-off state
 548          * it is the reset state here = the only managed by the driver
 549          */
 550         if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
 551                 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 552                        priv->base + SDMMC_POWER);
 553         }
 554
 555         /*
 556          * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
 557          * switch to Power-Off state: SDMCC disable, signals drive 1
 558          */
 559         writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
 560                priv->base + SDMMC_POWER);
 561
 562         /* After the 1ms delay set the SDMMC to power-on */
 563         mdelay(1);
 564         writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
 565                priv->base + SDMMC_POWER);
 566
 567         /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
 568 }
 569
 570 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 571 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 572 {
 573         struct mmc *mmc = mmc_get_mmc_dev(dev);
 574         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 575         u32 desired = mmc->clock;
 576         u32 sys_clock = clk_get_rate(&priv->clk);
 577         u32 clk = 0;
 578
 579         debug("%s: bus_with = %d, clock = %d\n", __func__,
 580               mmc->bus_width, mmc->clock);
 581
 582         if (mmc->clk_disable)
 583                 stm32_sdmmc2_pwrcycle(priv);
 584         else
 585                 stm32_sdmmc2_pwron(priv);
 586
 587         /*
 588          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 589          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 590          * SDMMCCLK rising edge
 591          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 592          * SDMMCCLK falling edge
 593          */
 594         if (desired && ((sys_clock > desired) ||
 595                         IS_RISING_EDGE(priv->clk_reg_msk))) {
 596                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 597                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 598                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 599         }
 600
 601         if (mmc->bus_width == 4)
 602                 clk |= SDMMC_CLKCR_WIDBUS_4;
 603         if (mmc->bus_width == 8)
 604                 clk |= SDMMC_CLKCR_WIDBUS_8;
 605
 606         writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 607                priv->base + SDMMC_CLKCR);
 608
 609         return 0;
 610 }
 611
 612 static int stm32_sdmmc2_getcd(struct udevice *dev)
 613 {
 614         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 615
 616         debug("stm32_sdmmc2_getcd called\n");
 617
 618         if (dm_gpio_is_valid(&priv->cd_gpio))
 619                 return dm_gpio_get_value(&priv->cd_gpio);
 620
 621         return 1;
 622 }
 623
 624 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
 625 {
 626         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 627
 628         writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 629                priv->base + SDMMC_POWER);
 630
 631         return 0;
 632 }
 633
 634 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 635         .send_cmd = stm32_sdmmc2_send_cmd,
 636         .set_ios = stm32_sdmmc2_set_ios,
 637         .get_cd = stm32_sdmmc2_getcd,
 638         .host_power_cycle = stm32_sdmmc2_host_power_cycle,
 639 };
 640
 641 static int stm32_sdmmc2_probe(struct udevice *dev)
 642 {
 643         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 644         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 645         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 646         struct mmc_config *cfg = &plat->cfg;
 647         int ret;
 648
 649         priv->base = dev_read_addr(dev);
 650         if (priv->base == FDT_ADDR_T_NONE)
 651                 return -EINVAL;
 652
 653         if (dev_read_bool(dev, "st,neg-edge"))
 654                 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 655         if (dev_read_bool(dev, "st,sig-dir"))
 656                 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 657         if (dev_read_bool(dev, "st,use-ckin"))
 658                 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 659
 660         ret = clk_get_by_index(dev, 0, &priv->clk);
 661         if (ret)
 662                 return ret;
 663
 664         ret = clk_enable(&priv->clk);
 665         if (ret)
 666                 goto clk_free;
 667
 668         ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 669         if (ret)
 670                 goto clk_disable;
 671
 672         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 673                              GPIOD_IS_IN);
 674
 675         cfg->f_min = 400000;
 676         cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
 677         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 678         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 679         cfg->name = "STM32 SD/MMC";
 680
 681         cfg->host_caps = 0;
 682         if (cfg->f_max > 25000000)
 683                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 684
 685         switch (dev_read_u32_default(dev, "bus-width", 1)) {
 686         case 8:
 687                 cfg->host_caps |= MMC_MODE_8BIT;
 688                 /* fall through */
 689         case 4:
 690                 cfg->host_caps |= MMC_MODE_4BIT;
 691                 break;
 692         case 1:
 693                 break;
 694         default:
 695                 pr_err("invalid \"bus-width\" property, force to 1\n");
 696         }
 697
 698         upriv->mmc = &plat->mmc;
 699
 700         /* SDMMC init */
 701         stm32_sdmmc2_reset(priv);
 702         return 0;
 703
 704 clk_disable:
 705         clk_disable(&priv->clk);
 706 clk_free:
 707         clk_free(&priv->clk);
 708
 709         return ret;
 710 }
 711
 712 static int stm32_sdmmc_bind(struct udevice *dev)
 713 {
 714         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 715
 716         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 717 }
 718
 719 static const struct udevice_id stm32_sdmmc2_ids[] = {
 720         { .compatible = "st,stm32-sdmmc2" },
 721         { }
 722 };
 723
 724 U_BOOT_DRIVER(stm32_sdmmc2) = {
 725         .name = "stm32_sdmmc2",
 726         .id = UCLASS_MMC,
 727         .of_match = stm32_sdmmc2_ids,
 728         .ops = &stm32_sdmmc2_ops,
 729         .probe = stm32_sdmmc2_probe,
 730         .bind = stm32_sdmmc_bind,
 731         .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
 732         .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
 733 };