drivers/mmc/sh_sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * drivers/mmc/sh_sdhi.c
   4  *
   5  * SD/MMC driver for Renesas rmobile ARM SoCs.
   6  *
   7  * Copyright (C) 2011,2013-2017 Renesas Electronics Corporation
   8  * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   9  * Copyright (C) 2008-2009 Renesas Solutions Corp.
  10  */
  11
  12 #include <common.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <dm.h>
  17 #include <part.h>
  18 #include <dm/device_compat.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <linux/compat.h>
  22 #include <linux/io.h>
  23 #include <linux/sizes.h>
  24 #include <asm/arch/rmobile.h>
  25 #include <asm/arch/sh_sdhi.h>
  26 #include <clk.h>
  27
  28 #define DRIVER_NAME "sh-sdhi"
  29
  30 struct sh_sdhi_host {
  31         void __iomem *addr;
  32         int ch;
  33         int bus_shift;
  34         unsigned long quirks;
  35         unsigned char wait_int;
  36         unsigned char sd_error;
  37         unsigned char detect_waiting;
  38         unsigned char app_cmd;
  39 };
  40
  41 static inline void sh_sdhi_writeq(struct sh_sdhi_host *host, int reg, u64 val)
  42 {
  43         writeq(val, host->addr + (reg << host->bus_shift));
  44 }
  45
  46 static inline u64 sh_sdhi_readq(struct sh_sdhi_host *host, int reg)
  47 {
  48         return readq(host->addr + (reg << host->bus_shift));
  49 }
  50
  51 static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val)
  52 {
  53         writew(val, host->addr + (reg << host->bus_shift));
  54 }
  55
  56 static inline u16 sh_sdhi_readw(struct sh_sdhi_host *host, int reg)
  57 {
  58         return readw(host->addr + (reg << host->bus_shift));
  59 }
  60
  61 static void sh_sdhi_detect(struct sh_sdhi_host *host)
  62 {
  63         sh_sdhi_writew(host, SDHI_OPTION,
  64                        OPT_BUS_WIDTH_1 | sh_sdhi_readw(host, SDHI_OPTION));
  65
  66         host->detect_waiting = 0;
  67 }
  68
  69 static int sh_sdhi_intr(void *dev_id)
  70 {
  71         struct sh_sdhi_host *host = dev_id;
  72         int state1 = 0, state2 = 0;
  73
  74         state1 = sh_sdhi_readw(host, SDHI_INFO1);
  75         state2 = sh_sdhi_readw(host, SDHI_INFO2);
  76
  77         debug("%s: state1 = %x, state2 = %x\n", __func__, state1, state2);
  78
  79         /* CARD Insert */
  80         if (state1 & INFO1_CARD_IN) {
  81                 sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_IN);
  82                 if (!host->detect_waiting) {
  83                         host->detect_waiting = 1;
  84                         sh_sdhi_detect(host);
  85                 }
  86                 sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
  87                                INFO1M_ACCESS_END | INFO1M_CARD_IN |
  88                                INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
  89                 return -EAGAIN;
  90         }
  91         /* CARD Removal */
  92         if (state1 & INFO1_CARD_RE) {
  93                 sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_RE);
  94                 if (!host->detect_waiting) {
  95                         host->detect_waiting = 1;
  96                         sh_sdhi_detect(host);
  97                 }
  98                 sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
  99                                INFO1M_ACCESS_END | INFO1M_CARD_RE |
 100                                INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
 101                 sh_sdhi_writew(host, SDHI_SDIO_INFO1_MASK, SDIO_INFO1M_ON);
 102                 sh_sdhi_writew(host, SDHI_SDIO_MODE, SDIO_MODE_OFF);
 103                 return -EAGAIN;
 104         }
 105
 106         if (state2 & INFO2_ALL_ERR) {
 107                 sh_sdhi_writew(host, SDHI_INFO2,
 108                                (unsigned short)~(INFO2_ALL_ERR));
 109                 sh_sdhi_writew(host, SDHI_INFO2_MASK,
 110                                INFO2M_ALL_ERR |
 111                                sh_sdhi_readw(host, SDHI_INFO2_MASK));
 112                 host->sd_error = 1;
 113                 host->wait_int = 1;
 114                 return 0;
 115         }
 116         /* Respons End */
 117         if (state1 & INFO1_RESP_END) {
 118                 sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
 119                 sh_sdhi_writew(host, SDHI_INFO1_MASK,
 120                                INFO1M_RESP_END |
 121                                sh_sdhi_readw(host, SDHI_INFO1_MASK));
 122                 host->wait_int = 1;
 123                 return 0;
 124         }
 125         /* SD_BUF Read Enable */
 126         if (state2 & INFO2_BRE_ENABLE) {
 127                 sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BRE_ENABLE);
 128                 sh_sdhi_writew(host, SDHI_INFO2_MASK,
 129                                INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ |
 130                                sh_sdhi_readw(host, SDHI_INFO2_MASK));
 131                 host->wait_int = 1;
 132                 return 0;
 133         }
 134         /* SD_BUF Write Enable */
 135         if (state2 & INFO2_BWE_ENABLE) {
 136                 sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BWE_ENABLE);
 137                 sh_sdhi_writew(host, SDHI_INFO2_MASK,
 138                                INFO2_BWE_ENABLE | INFO2M_BUF_ILL_WRITE |
 139                                sh_sdhi_readw(host, SDHI_INFO2_MASK));
 140                 host->wait_int = 1;
 141                 return 0;
 142         }
 143         /* Access End */
 144         if (state1 & INFO1_ACCESS_END) {
 145                 sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_ACCESS_END);
 146                 sh_sdhi_writew(host, SDHI_INFO1_MASK,
 147                                INFO1_ACCESS_END |
 148                                sh_sdhi_readw(host, SDHI_INFO1_MASK));
 149                 host->wait_int = 1;
 150                 return 0;
 151         }
 152         return -EAGAIN;
 153 }
 154
 155 static int sh_sdhi_wait_interrupt_flag(struct sh_sdhi_host *host)
 156 {
 157         int timeout = 10000000;
 158
 159         while (1) {
 160                 timeout--;
 161                 if (timeout < 0) {
 162                         debug(DRIVER_NAME": %s timeout\n", __func__);
 163                         return 0;
 164                 }
 165
 166                 if (!sh_sdhi_intr(host))
 167                         break;
 168
 169                 udelay(1);      /* 1 usec */
 170         }
 171
 172         return 1; /* Return value: NOT 0 = complete waiting */
 173 }
 174
 175 static int sh_sdhi_clock_control(struct sh_sdhi_host *host, unsigned long clk)
 176 {
 177         u32 clkdiv, i, timeout;
 178
 179         if (sh_sdhi_readw(host, SDHI_INFO2) & (1 << 14)) {
 180                 printf(DRIVER_NAME": Busy state ! Cannot change the clock\n");
 181                 return -EBUSY;
 182         }
 183
 184         sh_sdhi_writew(host, SDHI_CLK_CTRL,
 185                        ~CLK_ENABLE & sh_sdhi_readw(host, SDHI_CLK_CTRL));
 186
 187         if (clk == 0)
 188                 return -EIO;
 189
 190         clkdiv = 0x80;
 191         i = CONFIG_SH_SDHI_FREQ >> (0x8 + 1);
 192         for (; clkdiv && clk >= (i << 1); (clkdiv >>= 1))
 193                 i <<= 1;
 194
 195         sh_sdhi_writew(host, SDHI_CLK_CTRL, clkdiv);
 196
 197         timeout = 100000;
 198         /* Waiting for SD Bus busy to be cleared */
 199         while (timeout--) {
 200                 if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
 201                         break;
 202         }
 203
 204         if (timeout)
 205                 sh_sdhi_writew(host, SDHI_CLK_CTRL,
 206                                CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
 207         else
 208                 return -EBUSY;
 209
 210         return 0;
 211 }
 212
 213 static int sh_sdhi_sync_reset(struct sh_sdhi_host *host)
 214 {
 215         u32 timeout;
 216         sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_ON);
 217         sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_OFF);
 218         sh_sdhi_writew(host, SDHI_CLK_CTRL,
 219                        CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
 220
 221         timeout = 100000;
 222         while (timeout--) {
 223                 if (!(sh_sdhi_readw(host, SDHI_INFO2) & INFO2_CBUSY))
 224                         break;
 225                 udelay(100);
 226         }
 227
 228         if (!timeout)
 229                 return -EBUSY;
 230
 231         if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
 232                 sh_sdhi_writew(host, SDHI_HOST_MODE, 1);
 233
 234         return 0;
 235 }
 236
 237 static int sh_sdhi_error_manage(struct sh_sdhi_host *host)
 238 {
 239         unsigned short e_state1, e_state2;
 240         int ret;
 241
 242         host->sd_error = 0;
 243         host->wait_int = 0;
 244
 245         e_state1 = sh_sdhi_readw(host, SDHI_ERR_STS1);
 246         e_state2 = sh_sdhi_readw(host, SDHI_ERR_STS2);
 247         if (e_state2 & ERR_STS2_SYS_ERROR) {
 248                 if (e_state2 & ERR_STS2_RES_STOP_TIMEOUT)
 249                         ret = -ETIMEDOUT;
 250                 else
 251                         ret = -EILSEQ;
 252                 debug("%s: ERR_STS2 = %04x\n",
 253                       DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS2));
 254                 sh_sdhi_sync_reset(host);
 255
 256                 sh_sdhi_writew(host, SDHI_INFO1_MASK,
 257                                INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
 258                 return ret;
 259         }
 260         if (e_state1 & ERR_STS1_CRC_ERROR || e_state1 & ERR_STS1_CMD_ERROR)
 261                 ret = -EILSEQ;
 262         else
 263                 ret = -ETIMEDOUT;
 264
 265         debug("%s: ERR_STS1 = %04x\n",
 266               DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS1));
 267         sh_sdhi_sync_reset(host);
 268         sh_sdhi_writew(host, SDHI_INFO1_MASK,
 269                        INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
 270         return ret;
 271 }
 272
 273 static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data)
 274 {
 275         long time;
 276         unsigned short blocksize, i;
 277         unsigned short *p = (unsigned short *)data->dest;
 278         u64 *q = (u64 *)data->dest;
 279
 280         if ((unsigned long)p & 0x00000001) {
 281                 debug(DRIVER_NAME": %s: The data pointer is unaligned.",
 282                       __func__);
 283                 return -EIO;
 284         }
 285
 286         host->wait_int = 0;
 287         sh_sdhi_writew(host, SDHI_INFO2_MASK,
 288                        ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
 289                        sh_sdhi_readw(host, SDHI_INFO2_MASK));
 290         sh_sdhi_writew(host, SDHI_INFO1_MASK,
 291                        ~INFO1M_ACCESS_END &
 292                        sh_sdhi_readw(host, SDHI_INFO1_MASK));
 293         time = sh_sdhi_wait_interrupt_flag(host);
 294         if (time == 0 || host->sd_error != 0)
 295                 return sh_sdhi_error_manage(host);
 296
 297         host->wait_int = 0;
 298         blocksize = sh_sdhi_readw(host, SDHI_SIZE);
 299         if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
 300                 for (i = 0; i < blocksize / 8; i++)
 301                         *q++ = sh_sdhi_readq(host, SDHI_BUF0);
 302         else
 303                 for (i = 0; i < blocksize / 2; i++)
 304                         *p++ = sh_sdhi_readw(host, SDHI_BUF0);
 305
 306         time = sh_sdhi_wait_interrupt_flag(host);
 307         if (time == 0 || host->sd_error != 0)
 308                 return sh_sdhi_error_manage(host);
 309
 310         host->wait_int = 0;
 311         return 0;
 312 }
 313
 314 static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data)
 315 {
 316         long time;
 317         unsigned short blocksize, i, sec;
 318         unsigned short *p = (unsigned short *)data->dest;
 319         u64 *q = (u64 *)data->dest;
 320
 321         if ((unsigned long)p & 0x00000001) {
 322                 debug(DRIVER_NAME": %s: The data pointer is unaligned.",
 323                       __func__);
 324                 return -EIO;
 325         }
 326
 327         debug("%s: blocks = %d, blocksize = %d\n",
 328               __func__, data->blocks, data->blocksize);
 329
 330         host->wait_int = 0;
 331         for (sec = 0; sec < data->blocks; sec++) {
 332                 sh_sdhi_writew(host, SDHI_INFO2_MASK,
 333                                ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
 334                                sh_sdhi_readw(host, SDHI_INFO2_MASK));
 335
 336                 time = sh_sdhi_wait_interrupt_flag(host);
 337                 if (time == 0 || host->sd_error != 0)
 338                         return sh_sdhi_error_manage(host);
 339
 340                 host->wait_int = 0;
 341                 blocksize = sh_sdhi_readw(host, SDHI_SIZE);
 342                 if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
 343                         for (i = 0; i < blocksize / 8; i++)
 344                                 *q++ = sh_sdhi_readq(host, SDHI_BUF0);
 345                 else
 346                         for (i = 0; i < blocksize / 2; i++)
 347                                 *p++ = sh_sdhi_readw(host, SDHI_BUF0);
 348         }
 349
 350         return 0;
 351 }
 352
 353 static int sh_sdhi_single_write(struct sh_sdhi_host *host,
 354                 struct mmc_data *data)
 355 {
 356         long time;
 357         unsigned short blocksize, i;
 358         const unsigned short *p = (const unsigned short *)data->src;
 359         const u64 *q = (const u64 *)data->src;
 360
 361         if ((unsigned long)p & 0x00000001) {
 362                 debug(DRIVER_NAME": %s: The data pointer is unaligned.",
 363                       __func__);
 364                 return -EIO;
 365         }
 366
 367         debug("%s: blocks = %d, blocksize = %d\n",
 368               __func__, data->blocks, data->blocksize);
 369
 370         host->wait_int = 0;
 371         sh_sdhi_writew(host, SDHI_INFO2_MASK,
 372                        ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
 373                        sh_sdhi_readw(host, SDHI_INFO2_MASK));
 374         sh_sdhi_writew(host, SDHI_INFO1_MASK,
 375                        ~INFO1M_ACCESS_END &
 376                        sh_sdhi_readw(host, SDHI_INFO1_MASK));
 377
 378         time = sh_sdhi_wait_interrupt_flag(host);
 379         if (time == 0 || host->sd_error != 0)
 380                 return sh_sdhi_error_manage(host);
 381
 382         host->wait_int = 0;
 383         blocksize = sh_sdhi_readw(host, SDHI_SIZE);
 384         if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
 385                 for (i = 0; i < blocksize / 8; i++)
 386                         sh_sdhi_writeq(host, SDHI_BUF0, *q++);
 387         else
 388                 for (i = 0; i < blocksize / 2; i++)
 389                         sh_sdhi_writew(host, SDHI_BUF0, *p++);
 390
 391         time = sh_sdhi_wait_interrupt_flag(host);
 392         if (time == 0 || host->sd_error != 0)
 393                 return sh_sdhi_error_manage(host);
 394
 395         host->wait_int = 0;
 396         return 0;
 397 }
 398
 399 static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data)
 400 {
 401         long time;
 402         unsigned short i, sec, blocksize;
 403         const unsigned short *p = (const unsigned short *)data->src;
 404         const u64 *q = (const u64 *)data->src;
 405
 406         debug("%s: blocks = %d, blocksize = %d\n",
 407               __func__, data->blocks, data->blocksize);
 408
 409         host->wait_int = 0;
 410         for (sec = 0; sec < data->blocks; sec++) {
 411                 sh_sdhi_writew(host, SDHI_INFO2_MASK,
 412                                ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
 413                                sh_sdhi_readw(host, SDHI_INFO2_MASK));
 414
 415                 time = sh_sdhi_wait_interrupt_flag(host);
 416                 if (time == 0 || host->sd_error != 0)
 417                         return sh_sdhi_error_manage(host);
 418
 419                 host->wait_int = 0;
 420                 blocksize = sh_sdhi_readw(host, SDHI_SIZE);
 421                 if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
 422                         for (i = 0; i < blocksize / 8; i++)
 423                                 sh_sdhi_writeq(host, SDHI_BUF0, *q++);
 424                 else
 425                         for (i = 0; i < blocksize / 2; i++)
 426                                 sh_sdhi_writew(host, SDHI_BUF0, *p++);
 427         }
 428
 429         return 0;
 430 }
 431
 432 static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
 433 {
 434         unsigned short i, j, cnt = 1;
 435         unsigned short resp[8];
 436
 437         if (cmd->resp_type & MMC_RSP_136) {
 438                 cnt = 4;
 439                 resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
 440                 resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
 441                 resp[2] = sh_sdhi_readw(host, SDHI_RSP02);
 442                 resp[3] = sh_sdhi_readw(host, SDHI_RSP03);
 443                 resp[4] = sh_sdhi_readw(host, SDHI_RSP04);
 444                 resp[5] = sh_sdhi_readw(host, SDHI_RSP05);
 445                 resp[6] = sh_sdhi_readw(host, SDHI_RSP06);
 446                 resp[7] = sh_sdhi_readw(host, SDHI_RSP07);
 447
 448                 /* SDHI REGISTER SPECIFICATION */
 449                 for (i = 7, j = 6; i > 0; i--) {
 450                         resp[i] = (resp[i] << 8) & 0xff00;
 451                         resp[i] |= (resp[j--] >> 8) & 0x00ff;
 452                 }
 453                 resp[0] = (resp[0] << 8) & 0xff00;
 454         } else {
 455                 resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
 456                 resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
 457         }
 458
 459 #if defined(__BIG_ENDIAN_BITFIELD)
 460         if (cnt == 4) {
 461                 cmd->response[0] = (resp[6] << 16) | resp[7];
 462                 cmd->response[1] = (resp[4] << 16) | resp[5];
 463                 cmd->response[2] = (resp[2] << 16) | resp[3];
 464                 cmd->response[3] = (resp[0] << 16) | resp[1];
 465         } else {
 466                 cmd->response[0] = (resp[0] << 16) | resp[1];
 467         }
 468 #else
 469         if (cnt == 4) {
 470                 cmd->response[0] = (resp[7] << 16) | resp[6];
 471                 cmd->response[1] = (resp[5] << 16) | resp[4];
 472                 cmd->response[2] = (resp[3] << 16) | resp[2];
 473                 cmd->response[3] = (resp[1] << 16) | resp[0];
 474         } else {
 475                 cmd->response[0] = (resp[1] << 16) | resp[0];
 476         }
 477 #endif /* __BIG_ENDIAN_BITFIELD */
 478 }
 479
 480 static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host,
 481                         struct mmc_data *data, unsigned short opc)
 482 {
 483         if (host->app_cmd) {
 484                 if (!data)
 485                         host->app_cmd = 0;
 486                 return opc | BIT(6);
 487         }
 488
 489         switch (opc) {
 490         case MMC_CMD_SWITCH:
 491                 return opc | (data ? 0x1c00 : 0x40);
 492         case MMC_CMD_SEND_EXT_CSD:
 493                 return opc | (data ? 0x1c00 : 0);
 494         case MMC_CMD_SEND_OP_COND:
 495                 return opc | 0x0700;
 496         case MMC_CMD_APP_CMD:
 497                 host->app_cmd = 1;
 498         default:
 499                 return opc;
 500         }
 501 }
 502
 503 static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host,
 504                         struct mmc_data *data, unsigned short opc)
 505 {
 506         if (host->app_cmd) {
 507                 host->app_cmd = 0;
 508                 switch (opc) {
 509                 case SD_CMD_APP_SEND_SCR:
 510                 case SD_CMD_APP_SD_STATUS:
 511                         return sh_sdhi_single_read(host, data);
 512                 default:
 513                         printf(DRIVER_NAME": SD: NOT SUPPORT APP CMD = d'%04d\n",
 514                                 opc);
 515                         return -EINVAL;
 516                 }
 517         } else {
 518                 switch (opc) {
 519                 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
 520                         return sh_sdhi_multi_write(host, data);
 521                 case MMC_CMD_READ_MULTIPLE_BLOCK:
 522                         return sh_sdhi_multi_read(host, data);
 523                 case MMC_CMD_WRITE_SINGLE_BLOCK:
 524                         return sh_sdhi_single_write(host, data);
 525                 case MMC_CMD_READ_SINGLE_BLOCK:
 526                 case MMC_CMD_SWITCH:
 527                 case MMC_CMD_SEND_EXT_CSD:;
 528                         return sh_sdhi_single_read(host, data);
 529                 default:
 530                         printf(DRIVER_NAME": SD: NOT SUPPORT CMD = d'%04d\n", opc);
 531                         return -EINVAL;
 532                 }
 533         }
 534 }
 535
 536 static int sh_sdhi_start_cmd(struct sh_sdhi_host *host,
 537                         struct mmc_data *data, struct mmc_cmd *cmd)
 538 {
 539         long time;
 540         unsigned short shcmd, opc = cmd->cmdidx;
 541         int ret = 0;
 542         unsigned long timeout;
 543
 544         debug("opc = %d, arg = %x, resp_type = %x\n",
 545               opc, cmd->cmdarg, cmd->resp_type);
 546
 547         if (opc == MMC_CMD_STOP_TRANSMISSION) {
 548                 /* SDHI sends the STOP command automatically by STOP reg */
 549                 sh_sdhi_writew(host, SDHI_INFO1_MASK, ~INFO1M_ACCESS_END &
 550                                sh_sdhi_readw(host, SDHI_INFO1_MASK));
 551
 552                 time = sh_sdhi_wait_interrupt_flag(host);
 553                 if (time == 0 || host->sd_error != 0)
 554                         return sh_sdhi_error_manage(host);
 555
 556                 sh_sdhi_get_response(host, cmd);
 557                 return 0;
 558         }
 559
 560         if (data) {
 561                 if ((opc == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 562                     opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
 563                         sh_sdhi_writew(host, SDHI_STOP, STOP_SEC_ENABLE);
 564                         sh_sdhi_writew(host, SDHI_SECCNT, data->blocks);
 565                 }
 566                 sh_sdhi_writew(host, SDHI_SIZE, data->blocksize);
 567         }
 568
 569         shcmd = sh_sdhi_set_cmd(host, data, opc);
 570
 571         /*
 572          *  U-Boot cannot use interrupt.
 573          *  So this flag may not be clear by timing
 574          */
 575         sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
 576
 577         sh_sdhi_writew(host, SDHI_INFO1_MASK,
 578                        INFO1M_RESP_END | sh_sdhi_readw(host, SDHI_INFO1_MASK));
 579         sh_sdhi_writew(host, SDHI_ARG0,
 580                        (unsigned short)(cmd->cmdarg & ARG0_MASK));
 581         sh_sdhi_writew(host, SDHI_ARG1,
 582                        (unsigned short)((cmd->cmdarg >> 16) & ARG1_MASK));
 583
 584         timeout = 100000;
 585         /* Waiting for SD Bus busy to be cleared */
 586         while (timeout--) {
 587                 if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
 588                         break;
 589         }
 590
 591         host->wait_int = 0;
 592         sh_sdhi_writew(host, SDHI_INFO1_MASK,
 593                        ~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK));
 594         sh_sdhi_writew(host, SDHI_INFO2_MASK,
 595                        ~(INFO2M_CMD_ERROR | INFO2M_CRC_ERROR |
 596                        INFO2M_END_ERROR | INFO2M_TIMEOUT |
 597                        INFO2M_RESP_TIMEOUT | INFO2M_ILA) &
 598                        sh_sdhi_readw(host, SDHI_INFO2_MASK));
 599
 600         sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(shcmd & CMD_MASK));
 601         time = sh_sdhi_wait_interrupt_flag(host);
 602         if (!time) {
 603                 host->app_cmd = 0;
 604                 return sh_sdhi_error_manage(host);
 605         }
 606
 607         if (host->sd_error) {
 608                 switch (cmd->cmdidx) {
 609                 case MMC_CMD_ALL_SEND_CID:
 610                 case MMC_CMD_SELECT_CARD:
 611                 case SD_CMD_SEND_IF_COND:
 612                 case MMC_CMD_APP_CMD:
 613                         ret = -ETIMEDOUT;
 614                         break;
 615                 default:
 616                         debug(DRIVER_NAME": Cmd(d'%d) err\n", opc);
 617                         debug(DRIVER_NAME": cmdidx = %d\n", cmd->cmdidx);
 618                         ret = sh_sdhi_error_manage(host);
 619                         break;
 620                 }
 621                 host->sd_error = 0;
 622                 host->wait_int = 0;
 623                 host->app_cmd = 0;
 624                 return ret;
 625         }
 626
 627         if (sh_sdhi_readw(host, SDHI_INFO1) & INFO1_RESP_END) {
 628                 host->app_cmd = 0;
 629                 return -EINVAL;
 630         }
 631
 632         if (host->wait_int) {
 633                 sh_sdhi_get_response(host, cmd);
 634                 host->wait_int = 0;
 635         }
 636
 637         if (data)
 638                 ret = sh_sdhi_data_trans(host, data, opc);
 639
 640         debug("ret = %d, resp = %08x, %08x, %08x, %08x\n",
 641               ret, cmd->response[0], cmd->response[1],
 642               cmd->response[2], cmd->response[3]);
 643         return ret;
 644 }
 645
 646 static int sh_sdhi_send_cmd_common(struct sh_sdhi_host *host,
 647                                    struct mmc_cmd *cmd, struct mmc_data *data)
 648 {
 649         host->sd_error = 0;
 650
 651         return sh_sdhi_start_cmd(host, data, cmd);
 652 }
 653
 654 static int sh_sdhi_set_ios_common(struct sh_sdhi_host *host, struct mmc *mmc)
 655 {
 656         int ret;
 657
 658         ret = sh_sdhi_clock_control(host, mmc->clock);
 659         if (ret)
 660                 return -EINVAL;
 661
 662         if (mmc->bus_width == 8)
 663                 sh_sdhi_writew(host, SDHI_OPTION,
 664                                OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M &
 665                                sh_sdhi_readw(host, SDHI_OPTION)));
 666         else if (mmc->bus_width == 4)
 667                 sh_sdhi_writew(host, SDHI_OPTION,
 668                                OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M &
 669                                sh_sdhi_readw(host, SDHI_OPTION)));
 670         else
 671                 sh_sdhi_writew(host, SDHI_OPTION,
 672                                OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M &
 673                                sh_sdhi_readw(host, SDHI_OPTION)));
 674
 675         debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
 676
 677         return 0;
 678 }
 679
 680 static int sh_sdhi_initialize_common(struct sh_sdhi_host *host)
 681 {
 682         int ret = sh_sdhi_sync_reset(host);
 683
 684         sh_sdhi_writew(host, SDHI_PORTSEL, USE_1PORT);
 685
 686 #if defined(__BIG_ENDIAN_BITFIELD)
 687         sh_sdhi_writew(host, SDHI_EXT_SWAP, SET_SWAP);
 688 #endif
 689
 690         sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
 691                        INFO1M_ACCESS_END | INFO1M_CARD_RE |
 692                        INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
 693
 694         return ret;
 695 }
 696
 697 #ifndef CONFIG_DM_MMC
 698 static void *mmc_priv(struct mmc *mmc)
 699 {
 700         return (void *)mmc->priv;
 701 }
 702
 703 static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 704                             struct mmc_data *data)
 705 {
 706         struct sh_sdhi_host *host = mmc_priv(mmc);
 707
 708         return sh_sdhi_send_cmd_common(host, cmd, data);
 709 }
 710
 711 static int sh_sdhi_set_ios(struct mmc *mmc)
 712 {
 713         struct sh_sdhi_host *host = mmc_priv(mmc);
 714
 715         return sh_sdhi_set_ios_common(host, mmc);
 716 }
 717
 718 static int sh_sdhi_initialize(struct mmc *mmc)
 719 {
 720         struct sh_sdhi_host *host = mmc_priv(mmc);
 721
 722         return sh_sdhi_initialize_common(host);
 723 }
 724
 725 static const struct mmc_ops sh_sdhi_ops = {
 726         .send_cmd       = sh_sdhi_send_cmd,
 727         .set_ios        = sh_sdhi_set_ios,
 728         .init           = sh_sdhi_initialize,
 729 };
 730
 731 #ifdef CONFIG_RCAR_GEN3
 732 static struct mmc_config sh_sdhi_cfg = {
 733         .name           = DRIVER_NAME,
 734         .ops            = &sh_sdhi_ops,
 735         .f_min          = CLKDEV_INIT,
 736         .f_max          = CLKDEV_HS_DATA,
 737         .voltages       = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
 738         .host_caps      = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS |
 739                           MMC_MODE_HS_52MHz,
 740         .part_type      = PART_TYPE_DOS,
 741         .b_max          = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 742 };
 743 #else
 744 static struct mmc_config sh_sdhi_cfg = {
 745         .name           = DRIVER_NAME,
 746         .ops            = &sh_sdhi_ops,
 747         .f_min          = CLKDEV_INIT,
 748         .f_max          = CLKDEV_HS_DATA,
 749         .voltages       = MMC_VDD_32_33 | MMC_VDD_33_34,
 750         .host_caps      = MMC_MODE_4BIT | MMC_MODE_HS,
 751         .part_type      = PART_TYPE_DOS,
 752         .b_max          = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 753 };
 754 #endif
 755
 756 int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks)
 757 {
 758         int ret = 0;
 759         struct mmc *mmc;
 760         struct sh_sdhi_host *host = NULL;
 761
 762         if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL)
 763                 return -ENODEV;
 764
 765         host = malloc(sizeof(struct sh_sdhi_host));
 766         if (!host)
 767                 return -ENOMEM;
 768
 769         mmc = mmc_create(&sh_sdhi_cfg, host);
 770         if (!mmc) {
 771                 ret = -1;
 772                 goto error;
 773         }
 774
 775         host->ch = ch;
 776         host->addr = (void __iomem *)addr;
 777         host->quirks = quirks;
 778
 779         if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
 780                 host->bus_shift = 2;
 781         else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
 782                 host->bus_shift = 1;
 783
 784         return ret;
 785 error:
 786         if (host)
 787                 free(host);
 788         return ret;
 789 }
 790
 791 #else
 792
 793 struct sh_sdhi_plat {
 794         struct mmc_config cfg;
 795         struct mmc mmc;
 796 };
 797
 798 int sh_sdhi_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 799                         struct mmc_data *data)
 800 {
 801         struct sh_sdhi_host *host = dev_get_priv(dev);
 802
 803         return sh_sdhi_send_cmd_common(host, cmd, data);
 804 }
 805
 806 int sh_sdhi_dm_set_ios(struct udevice *dev)
 807 {
 808         struct sh_sdhi_host *host = dev_get_priv(dev);
 809         struct mmc *mmc = mmc_get_mmc_dev(dev);
 810
 811         return sh_sdhi_set_ios_common(host, mmc);
 812 }
 813
 814 static const struct dm_mmc_ops sh_sdhi_dm_ops = {
 815         .send_cmd       = sh_sdhi_dm_send_cmd,
 816         .set_ios        = sh_sdhi_dm_set_ios,
 817 };
 818
 819 static int sh_sdhi_dm_bind(struct udevice *dev)
 820 {
 821         struct sh_sdhi_plat *plat = dev_get_platdata(dev);
 822
 823         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 824 }
 825
 826 static int sh_sdhi_dm_probe(struct udevice *dev)
 827 {
 828         struct sh_sdhi_plat *plat = dev_get_platdata(dev);
 829         struct sh_sdhi_host *host = dev_get_priv(dev);
 830         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 831         struct clk sh_sdhi_clk;
 832         const u32 quirks = dev_get_driver_data(dev);
 833         fdt_addr_t base;
 834         int ret;
 835
 836         base = devfdt_get_addr(dev);
 837         if (base == FDT_ADDR_T_NONE)
 838                 return -EINVAL;
 839
 840         host->addr = devm_ioremap(dev, base, SZ_2K);
 841         if (!host->addr)
 842                 return -ENOMEM;
 843
 844         ret = clk_get_by_index(dev, 0, &sh_sdhi_clk);
 845         if (ret) {
 846                 debug("failed to get clock, ret=%d\n", ret);
 847                 return ret;
 848         }
 849
 850         ret = clk_enable(&sh_sdhi_clk);
 851         if (ret) {
 852                 debug("failed to enable clock, ret=%d\n", ret);
 853                 return ret;
 854         }
 855
 856         host->quirks = quirks;
 857
 858         if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
 859                 host->bus_shift = 2;
 860         else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
 861                 host->bus_shift = 1;
 862
 863         plat->cfg.name = dev->name;
 864         plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 865
 866         switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
 867                                1)) {
 868         case 8:
 869                 plat->cfg.host_caps |= MMC_MODE_8BIT;
 870                 break;
 871         case 4:
 872                 plat->cfg.host_caps |= MMC_MODE_4BIT;
 873                 break;
 874         case 1:
 875                 break;
 876         default:
 877                 dev_err(dev, "Invalid \"bus-width\" value\n");
 878                 return -EINVAL;
 879         }
 880
 881         sh_sdhi_initialize_common(host);
 882
 883         plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
 884         plat->cfg.f_min = CLKDEV_INIT;
 885         plat->cfg.f_max = CLKDEV_HS_DATA;
 886         plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 887
 888         upriv->mmc = &plat->mmc;
 889
 890         return 0;
 891 }
 892
 893 static const struct udevice_id sh_sdhi_sd_match[] = {
 894         { .compatible = "renesas,sdhi-r8a7795", .data = SH_SDHI_QUIRK_64BIT_BUF },
 895         { .compatible = "renesas,sdhi-r8a7796", .data = SH_SDHI_QUIRK_64BIT_BUF },
 896         { /* sentinel */ }
 897 };
 898
 899 U_BOOT_DRIVER(sh_sdhi_mmc) = {
 900         .name                   = "sh-sdhi-mmc",
 901         .id                     = UCLASS_MMC,
 902         .of_match               = sh_sdhi_sd_match,
 903         .bind                   = sh_sdhi_dm_bind,
 904         .probe                  = sh_sdhi_dm_probe,
 905         .priv_auto_alloc_size   = sizeof(struct sh_sdhi_host),
 906         .platdata_auto_alloc_size = sizeof(struct sh_sdhi_plat),
 907         .ops                    = &sh_sdhi_dm_ops,
 908 };
 909 #endif