drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <sdhci.h>
  17 #include <dm.h>
  18 #include <linux/dma-mapping.h>
  19 #include <phys2bus.h>
  20
  21 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  22 {
  23         unsigned long timeout;
  24
  25         /* Wait max 100 ms */
  26         timeout = 100;
  27         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  28         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  29                 if (timeout == 0) {
  30                         printf("%s: Reset 0x%x never completed.\n",
  31                                __func__, (int)mask);
  32                         return;
  33                 }
  34                 timeout--;
  35                 udelay(1000);
  36         }
  37 }
  38
  39 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  40 {
  41         int i;
  42         if (cmd->resp_type & MMC_RSP_136) {
  43                 /* CRC is stripped so we need to do some shifting. */
  44                 for (i = 0; i < 4; i++) {
  45                         cmd->response[i] = sdhci_readl(host,
  46                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  47                         if (i != 3)
  48                                 cmd->response[i] |= sdhci_readb(host,
  49                                                 SDHCI_RESPONSE + (3-i)*4-1);
  50                 }
  51         } else {
  52                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  53         }
  54 }
  55
  56 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  57 {
  58         int i;
  59         char *offs;
  60         for (i = 0; i < data->blocksize; i += 4) {
  61                 offs = data->dest + i;
  62                 if (data->flags == MMC_DATA_READ)
  63                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  64                 else
  65                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  66         }
  67 }
  68
  69 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  70 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
  71                             u16 len, bool end)
  72 {
  73         struct sdhci_adma_desc *desc;
  74         u8 attr;
  75
  76         desc = &host->adma_desc_table[host->desc_slot];
  77
  78         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  79         if (!end)
  80                 host->desc_slot++;
  81         else
  82                 attr |= ADMA_DESC_ATTR_END;
  83
  84         desc->attr = attr;
  85         desc->len = len;
  86         desc->reserved = 0;
  87         desc->addr_lo = lower_32_bits(dma_addr);
  88 #ifdef CONFIG_DMA_ADDR_T_64BIT
  89         desc->addr_hi = upper_32_bits(dma_addr);
  90 #endif
  91 }
  92
  93 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  94                                      struct mmc_data *data)
  95 {
  96         uint trans_bytes = data->blocksize * data->blocks;
  97         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  98         int i = desc_count;
  99         dma_addr_t dma_addr = host->start_addr;
 100
 101         host->desc_slot = 0;
 102
 103         while (--i) {
 104                 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
 105                 dma_addr += ADMA_MAX_LEN;
 106                 trans_bytes -= ADMA_MAX_LEN;
 107         }
 108
 109         sdhci_adma_desc(host, dma_addr, trans_bytes, true);
 110
 111         flush_cache((dma_addr_t)host->adma_desc_table,
 112                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 113                           ARCH_DMA_MINALIGN));
 114 }
 115 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 116 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 117                                      struct mmc_data *data)
 118 {}
 119 #endif
 120 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 121 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 122                               int *is_aligned, int trans_bytes)
 123 {
 124         unsigned char ctrl;
 125         void *buf;
 126
 127         if (data->flags == MMC_DATA_READ)
 128                 buf = data->dest;
 129         else
 130                 buf = (void *)data->src;
 131
 132         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 133         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 134         if (host->flags & USE_ADMA64)
 135                 ctrl |= SDHCI_CTRL_ADMA64;
 136         else if (host->flags & USE_ADMA)
 137                 ctrl |= SDHCI_CTRL_ADMA32;
 138         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 139
 140         if (host->flags & USE_SDMA &&
 141             (host->force_align_buffer ||
 142              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
 143               ((unsigned long)buf & 0x7) != 0x0))) {
 144                 *is_aligned = 0;
 145                 if (data->flags != MMC_DATA_READ)
 146                         memcpy(host->align_buffer, buf, trans_bytes);
 147                 buf = host->align_buffer;
 148         }
 149
 150         host->start_addr = dma_map_single(buf, trans_bytes,
 151                                           mmc_get_dma_dir(data));
 152
 153         if (host->flags & USE_SDMA) {
 154                 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
 155                                 SDHCI_DMA_ADDRESS);
 156         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 157                 sdhci_prepare_adma_table(host, data);
 158
 159                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 160                              SDHCI_ADMA_ADDRESS);
 161                 if (host->flags & USE_ADMA64)
 162                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 163                                      SDHCI_ADMA_ADDRESS_HI);
 164         }
 165 }
 166 #else
 167 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 168                               int *is_aligned, int trans_bytes)
 169 {}
 170 #endif
 171 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 172 {
 173         dma_addr_t start_addr = host->start_addr;
 174         unsigned int stat, rdy, mask, timeout, block = 0;
 175         bool transfer_done = false;
 176
 177         timeout = 1000000;
 178         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 179         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 180         do {
 181                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 182                 if (stat & SDHCI_INT_ERROR) {
 183                         pr_debug("%s: Error detected in status(0x%X)!\n",
 184                                  __func__, stat);
 185                         return -EIO;
 186                 }
 187                 if (!transfer_done && (stat & rdy)) {
 188                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 189                                 continue;
 190                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 191                         sdhci_transfer_pio(host, data);
 192                         data->dest += data->blocksize;
 193                         if (++block >= data->blocks) {
 194                                 /* Keep looping until the SDHCI_INT_DATA_END is
 195                                  * cleared, even if we finished sending all the
 196                                  * blocks.
 197                                  */
 198                                 transfer_done = true;
 199                                 continue;
 200                         }
 201                 }
 202                 if ((host->flags & USE_DMA) && !transfer_done &&
 203                     (stat & SDHCI_INT_DMA_END)) {
 204                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 205                         if (host->flags & USE_SDMA) {
 206                                 start_addr &=
 207                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 208                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 209                                 sdhci_writel(host, phys_to_bus((ulong)start_addr),
 210                                              SDHCI_DMA_ADDRESS);
 211                         }
 212                 }
 213                 if (timeout-- > 0)
 214                         udelay(10);
 215                 else {
 216                         printf("%s: Transfer data timeout\n", __func__);
 217                         return -ETIMEDOUT;
 218                 }
 219         } while (!(stat & SDHCI_INT_DATA_END));
 220
 221         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 222                          mmc_get_dma_dir(data));
 223
 224         return 0;
 225 }
 226
 227 /*
 228  * No command will be sent by driver if card is busy, so driver must wait
 229  * for card ready state.
 230  * Every time when card is busy after timeout then (last) timeout value will be
 231  * increased twice but only if it doesn't exceed global defined maximum.
 232  * Each function call will use last timeout value.
 233  */
 234 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 235 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 236 #define SDHCI_READ_STATUS_TIMEOUT               1000
 237
 238 #ifdef CONFIG_DM_MMC
 239 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 240                               struct mmc_data *data)
 241 {
 242         struct mmc *mmc = mmc_get_mmc_dev(dev);
 243
 244 #else
 245 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 246                               struct mmc_data *data)
 247 {
 248 #endif
 249         struct sdhci_host *host = mmc->priv;
 250         unsigned int stat = 0;
 251         int ret = 0;
 252         int trans_bytes = 0, is_aligned = 1;
 253         u32 mask, flags, mode;
 254         unsigned int time = 0;
 255         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 256         ulong start = get_timer(0);
 257
 258         host->start_addr = 0;
 259         /* Timeout unit - ms */
 260         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 261
 262         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 263
 264         /* We shouldn't wait for data inihibit for stop commands, even
 265            though they might use busy signaling */
 266         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 267             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 268               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 269                 mask &= ~SDHCI_DATA_INHIBIT;
 270
 271         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 272                 if (time >= cmd_timeout) {
 273                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 274                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 275                                 cmd_timeout += cmd_timeout;
 276                                 printf("timeout increasing to: %u ms.\n",
 277                                        cmd_timeout);
 278                         } else {
 279                                 puts("timeout.\n");
 280                                 return -ECOMM;
 281                         }
 282                 }
 283                 time++;
 284                 udelay(1000);
 285         }
 286
 287         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 288
 289         mask = SDHCI_INT_RESPONSE;
 290         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 291              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 292                 mask = SDHCI_INT_DATA_AVAIL;
 293
 294         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 295                 flags = SDHCI_CMD_RESP_NONE;
 296         else if (cmd->resp_type & MMC_RSP_136)
 297                 flags = SDHCI_CMD_RESP_LONG;
 298         else if (cmd->resp_type & MMC_RSP_BUSY) {
 299                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 300                 if (data)
 301                         mask |= SDHCI_INT_DATA_END;
 302         } else
 303                 flags = SDHCI_CMD_RESP_SHORT;
 304
 305         if (cmd->resp_type & MMC_RSP_CRC)
 306                 flags |= SDHCI_CMD_CRC;
 307         if (cmd->resp_type & MMC_RSP_OPCODE)
 308                 flags |= SDHCI_CMD_INDEX;
 309         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 310             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 311                 flags |= SDHCI_CMD_DATA;
 312
 313         /* Set Transfer mode regarding to data flag */
 314         if (data) {
 315                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 316                 mode = SDHCI_TRNS_BLK_CNT_EN;
 317                 trans_bytes = data->blocks * data->blocksize;
 318                 if (data->blocks > 1)
 319                         mode |= SDHCI_TRNS_MULTI;
 320
 321                 if (data->flags == MMC_DATA_READ)
 322                         mode |= SDHCI_TRNS_READ;
 323
 324                 if (host->flags & USE_DMA) {
 325                         mode |= SDHCI_TRNS_DMA;
 326                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 327                 }
 328
 329                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 330                                 data->blocksize),
 331                                 SDHCI_BLOCK_SIZE);
 332                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 333                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 334         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 335                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 336         }
 337
 338         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 339         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 340         start = get_timer(0);
 341         do {
 342                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 343                 if (stat & SDHCI_INT_ERROR)
 344                         break;
 345
 346                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 347                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 348                                 return 0;
 349                         } else {
 350                                 printf("%s: Timeout for status update!\n",
 351                                        __func__);
 352                                 return -ETIMEDOUT;
 353                         }
 354                 }
 355         } while ((stat & mask) != mask);
 356
 357         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 358                 sdhci_cmd_done(host, cmd);
 359                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 360         } else
 361                 ret = -1;
 362
 363         if (!ret && data)
 364                 ret = sdhci_transfer_data(host, data);
 365
 366         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 367                 udelay(1000);
 368
 369         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 370         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 371         if (!ret) {
 372                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 373                                 !is_aligned && (data->flags == MMC_DATA_READ))
 374                         memcpy(data->dest, host->align_buffer, trans_bytes);
 375                 return 0;
 376         }
 377
 378         sdhci_reset(host, SDHCI_RESET_CMD);
 379         sdhci_reset(host, SDHCI_RESET_DATA);
 380         if (stat & SDHCI_INT_TIMEOUT)
 381                 return -ETIMEDOUT;
 382         else
 383                 return -ECOMM;
 384 }
 385
 386 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 387 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 388 {
 389         int err;
 390         struct mmc *mmc = mmc_get_mmc_dev(dev);
 391         struct sdhci_host *host = mmc->priv;
 392
 393         debug("%s\n", __func__);
 394
 395         if (host->ops && host->ops->platform_execute_tuning) {
 396                 err = host->ops->platform_execute_tuning(mmc, opcode);
 397                 if (err)
 398                         return err;
 399                 return 0;
 400         }
 401         return 0;
 402 }
 403 #endif
 404 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 405 {
 406         struct sdhci_host *host = mmc->priv;
 407         unsigned int div, clk = 0, timeout;
 408
 409         /* Wait max 20 ms */
 410         timeout = 200;
 411         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 412                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 413                 if (timeout == 0) {
 414                         printf("%s: Timeout to wait cmd & data inhibit\n",
 415                                __func__);
 416                         return -EBUSY;
 417                 }
 418
 419                 timeout--;
 420                 udelay(100);
 421         }
 422
 423         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 424
 425         if (clock == 0)
 426                 return 0;
 427
 428         if (host->ops && host->ops->set_delay)
 429                 host->ops->set_delay(host);
 430
 431         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 432                 /*
 433                  * Check if the Host Controller supports Programmable Clock
 434                  * Mode.
 435                  */
 436                 if (host->clk_mul) {
 437                         for (div = 1; div <= 1024; div++) {
 438                                 if ((host->max_clk / div) <= clock)
 439                                         break;
 440                         }
 441
 442                         /*
 443                          * Set Programmable Clock Mode in the Clock
 444                          * Control register.
 445                          */
 446                         clk = SDHCI_PROG_CLOCK_MODE;
 447                         div--;
 448                 } else {
 449                         /* Version 3.00 divisors must be a multiple of 2. */
 450                         if (host->max_clk <= clock) {
 451                                 div = 1;
 452                         } else {
 453                                 for (div = 2;
 454                                      div < SDHCI_MAX_DIV_SPEC_300;
 455                                      div += 2) {
 456                                         if ((host->max_clk / div) <= clock)
 457                                                 break;
 458                                 }
 459                         }
 460                         div >>= 1;
 461                 }
 462         } else {
 463                 /* Version 2.00 divisors must be a power of 2. */
 464                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 465                         if ((host->max_clk / div) <= clock)
 466                                 break;
 467                 }
 468                 div >>= 1;
 469         }
 470
 471         if (host->ops && host->ops->set_clock)
 472                 host->ops->set_clock(host, div);
 473
 474         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 475         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 476                 << SDHCI_DIVIDER_HI_SHIFT;
 477         clk |= SDHCI_CLOCK_INT_EN;
 478         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 479
 480         /* Wait max 20 ms */
 481         timeout = 20;
 482         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 483                 & SDHCI_CLOCK_INT_STABLE)) {
 484                 if (timeout == 0) {
 485                         printf("%s: Internal clock never stabilised.\n",
 486                                __func__);
 487                         return -EBUSY;
 488                 }
 489                 timeout--;
 490                 udelay(1000);
 491         }
 492
 493         clk |= SDHCI_CLOCK_CARD_EN;
 494         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 495         return 0;
 496 }
 497
 498 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 499 {
 500         u8 pwr = 0;
 501
 502         if (power != (unsigned short)-1) {
 503                 switch (1 << power) {
 504                 case MMC_VDD_165_195:
 505                         pwr = SDHCI_POWER_180;
 506                         break;
 507                 case MMC_VDD_29_30:
 508                 case MMC_VDD_30_31:
 509                         pwr = SDHCI_POWER_300;
 510                         break;
 511                 case MMC_VDD_32_33:
 512                 case MMC_VDD_33_34:
 513                         pwr = SDHCI_POWER_330;
 514                         break;
 515                 }
 516         }
 517
 518         if (pwr == 0) {
 519                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 520                 return;
 521         }
 522
 523         pwr |= SDHCI_POWER_ON;
 524
 525         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 526 }
 527
 528 void sdhci_set_uhs_timing(struct sdhci_host *host)
 529 {
 530         struct mmc *mmc = host->mmc;
 531         u32 reg;
 532
 533         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 534         reg &= ~SDHCI_CTRL_UHS_MASK;
 535
 536         switch (mmc->selected_mode) {
 537         case UHS_SDR50:
 538         case MMC_HS_52:
 539                 reg |= SDHCI_CTRL_UHS_SDR50;
 540                 break;
 541         case UHS_DDR50:
 542         case MMC_DDR_52:
 543                 reg |= SDHCI_CTRL_UHS_DDR50;
 544                 break;
 545         case UHS_SDR104:
 546         case MMC_HS_200:
 547                 reg |= SDHCI_CTRL_UHS_SDR104;
 548                 break;
 549         default:
 550                 reg |= SDHCI_CTRL_UHS_SDR12;
 551         }
 552
 553         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 554 }
 555
 556 #ifdef CONFIG_DM_MMC
 557 static int sdhci_set_ios(struct udevice *dev)
 558 {
 559         struct mmc *mmc = mmc_get_mmc_dev(dev);
 560 #else
 561 static int sdhci_set_ios(struct mmc *mmc)
 562 {
 563 #endif
 564         u32 ctrl;
 565         struct sdhci_host *host = mmc->priv;
 566
 567         if (host->ops && host->ops->set_control_reg)
 568                 host->ops->set_control_reg(host);
 569
 570         if (mmc->clock != host->clock)
 571                 sdhci_set_clock(mmc, mmc->clock);
 572
 573         if (mmc->clk_disable)
 574                 sdhci_set_clock(mmc, 0);
 575
 576         /* Set bus width */
 577         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 578         if (mmc->bus_width == 8) {
 579                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 580                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 581                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 582                         ctrl |= SDHCI_CTRL_8BITBUS;
 583         } else {
 584                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 585                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 586                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 587                 if (mmc->bus_width == 4)
 588                         ctrl |= SDHCI_CTRL_4BITBUS;
 589                 else
 590                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 591         }
 592
 593         if (mmc->clock > 26000000)
 594                 ctrl |= SDHCI_CTRL_HISPD;
 595         else
 596                 ctrl &= ~SDHCI_CTRL_HISPD;
 597
 598         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 599             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 600                 ctrl &= ~SDHCI_CTRL_HISPD;
 601
 602         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 603
 604         /* If available, call the driver specific "post" set_ios() function */
 605         if (host->ops && host->ops->set_ios_post)
 606                 return host->ops->set_ios_post(host);
 607
 608         return 0;
 609 }
 610
 611 static int sdhci_init(struct mmc *mmc)
 612 {
 613         struct sdhci_host *host = mmc->priv;
 614 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 615         struct udevice *dev = mmc->dev;
 616
 617         gpio_request_by_name(dev, "cd-gpios", 0,
 618                              &host->cd_gpio, GPIOD_IS_IN);
 619 #endif
 620
 621         sdhci_reset(host, SDHCI_RESET_ALL);
 622
 623 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 624         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 625         /*
 626          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 627          * is defined.
 628          */
 629         host->force_align_buffer = true;
 630 #else
 631         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 632                 host->align_buffer = memalign(8, 512 * 1024);
 633                 if (!host->align_buffer) {
 634                         printf("%s: Aligned buffer alloc failed!!!\n",
 635                                __func__);
 636                         return -ENOMEM;
 637                 }
 638         }
 639 #endif
 640
 641         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 642
 643         if (host->ops && host->ops->get_cd)
 644                 host->ops->get_cd(host);
 645
 646         /* Enable only interrupts served by the SD controller */
 647         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 648                      SDHCI_INT_ENABLE);
 649         /* Mask all sdhci interrupt sources */
 650         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 651
 652         return 0;
 653 }
 654
 655 #ifdef CONFIG_DM_MMC
 656 int sdhci_probe(struct udevice *dev)
 657 {
 658         struct mmc *mmc = mmc_get_mmc_dev(dev);
 659
 660         return sdhci_init(mmc);
 661 }
 662
 663 static int sdhci_deferred_probe(struct udevice *dev)
 664 {
 665         int err;
 666         struct mmc *mmc = mmc_get_mmc_dev(dev);
 667         struct sdhci_host *host = mmc->priv;
 668
 669         if (host->ops && host->ops->deferred_probe) {
 670                 err = host->ops->deferred_probe(host);
 671                 if (err)
 672                         return err;
 673         }
 674         return 0;
 675 }
 676
 677 static int sdhci_get_cd(struct udevice *dev)
 678 {
 679         struct mmc *mmc = mmc_get_mmc_dev(dev);
 680         struct sdhci_host *host = mmc->priv;
 681         int value;
 682
 683         /* If nonremovable, assume that the card is always present. */
 684         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 685                 return 1;
 686         /* If polling, assume that the card is always present. */
 687         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 688                 return 1;
 689
 690 #if CONFIG_IS_ENABLED(DM_GPIO)
 691         value = dm_gpio_get_value(&host->cd_gpio);
 692         if (value >= 0) {
 693                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 694                         return !value;
 695                 else
 696                         return value;
 697         }
 698 #endif
 699         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 700                    SDHCI_CARD_PRESENT);
 701         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 702                 return !value;
 703         else
 704                 return value;
 705 }
 706
 707 const struct dm_mmc_ops sdhci_ops = {
 708         .send_cmd       = sdhci_send_command,
 709         .set_ios        = sdhci_set_ios,
 710         .get_cd         = sdhci_get_cd,
 711         .deferred_probe = sdhci_deferred_probe,
 712 #ifdef MMC_SUPPORTS_TUNING
 713         .execute_tuning = sdhci_execute_tuning,
 714 #endif
 715 };
 716 #else
 717 static const struct mmc_ops sdhci_ops = {
 718         .send_cmd       = sdhci_send_command,
 719         .set_ios        = sdhci_set_ios,
 720         .init           = sdhci_init,
 721 };
 722 #endif
 723
 724 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 725                 u32 f_max, u32 f_min)
 726 {
 727         u32 caps, caps_1 = 0;
 728 #if CONFIG_IS_ENABLED(DM_MMC)
 729         u64 dt_caps, dt_caps_mask;
 730
 731         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 732                                             "sdhci-caps-mask", 0);
 733         dt_caps = dev_read_u64_default(host->mmc->dev,
 734                                        "sdhci-caps", 0);
 735         caps = ~(u32)dt_caps_mask &
 736                sdhci_readl(host, SDHCI_CAPABILITIES);
 737         caps |= (u32)dt_caps;
 738 #else
 739         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 740 #endif
 741         debug("%s, caps: 0x%x\n", __func__, caps);
 742
 743 #ifdef CONFIG_MMC_SDHCI_SDMA
 744         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 745                 printf("%s: Your controller doesn't support SDMA!!\n",
 746                        __func__);
 747                 return -EINVAL;
 748         }
 749
 750         host->flags |= USE_SDMA;
 751 #endif
 752 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 753         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 754                 printf("%s: Your controller doesn't support SDMA!!\n",
 755                        __func__);
 756                 return -EINVAL;
 757         }
 758         host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 759
 760         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 761 #ifdef CONFIG_DMA_ADDR_T_64BIT
 762         host->flags |= USE_ADMA64;
 763 #else
 764         host->flags |= USE_ADMA;
 765 #endif
 766 #endif
 767         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 768                 host->version =
 769                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 770         else
 771                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 772
 773         cfg->name = host->name;
 774 #ifndef CONFIG_DM_MMC
 775         cfg->ops = &sdhci_ops;
 776 #endif
 777
 778         /* Check whether the clock multiplier is supported or not */
 779         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 780 #if CONFIG_IS_ENABLED(DM_MMC)
 781                 caps_1 = ~(u32)(dt_caps_mask >> 32) &
 782                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 783                 caps_1 |= (u32)(dt_caps >> 32);
 784 #else
 785                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 786 #endif
 787                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 788                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 789                                 SDHCI_CLOCK_MUL_SHIFT;
 790         }
 791
 792         if (host->max_clk == 0) {
 793                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 794                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 795                                 SDHCI_CLOCK_BASE_SHIFT;
 796                 else
 797                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 798                                 SDHCI_CLOCK_BASE_SHIFT;
 799                 host->max_clk *= 1000000;
 800                 if (host->clk_mul)
 801                         host->max_clk *= host->clk_mul;
 802         }
 803         if (host->max_clk == 0) {
 804                 printf("%s: Hardware doesn't specify base clock frequency\n",
 805                        __func__);
 806                 return -EINVAL;
 807         }
 808         if (f_max && (f_max < host->max_clk))
 809                 cfg->f_max = f_max;
 810         else
 811                 cfg->f_max = host->max_clk;
 812         if (f_min)
 813                 cfg->f_min = f_min;
 814         else {
 815                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 816                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 817                 else
 818                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 819         }
 820         cfg->voltages = 0;
 821         if (caps & SDHCI_CAN_VDD_330)
 822                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 823         if (caps & SDHCI_CAN_VDD_300)
 824                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 825         if (caps & SDHCI_CAN_VDD_180)
 826                 cfg->voltages |= MMC_VDD_165_195;
 827
 828         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 829                 cfg->voltages |= host->voltages;
 830
 831         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 832
 833         /* Since Host Controller Version3.0 */
 834         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 835                 if (!(caps & SDHCI_CAN_DO_8BIT))
 836                         cfg->host_caps &= ~MMC_MODE_8BIT;
 837         }
 838
 839         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 840                 cfg->host_caps &= ~MMC_MODE_HS;
 841                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 842         }
 843
 844         if (!(cfg->voltages & MMC_VDD_165_195))
 845                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 846                             SDHCI_SUPPORT_DDR50);
 847
 848         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 849                       SDHCI_SUPPORT_DDR50))
 850                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 851
 852         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 853                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 854                 /*
 855                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 856                  * field can be promoted to support HS200.
 857                  */
 858                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 859         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 860                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 861         }
 862
 863         if (caps_1 & SDHCI_SUPPORT_DDR50)
 864                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 865
 866         if (host->host_caps)
 867                 cfg->host_caps |= host->host_caps;
 868
 869         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 870
 871         return 0;
 872 }
 873
 874 #ifdef CONFIG_BLK
 875 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 876 {
 877         return mmc_bind(dev, mmc, cfg);
 878 }
 879 #else
 880 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 881 {
 882         int ret;
 883
 884         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 885         if (ret)
 886                 return ret;
 887
 888         host->mmc = mmc_create(&host->cfg, host);
 889         if (host->mmc == NULL) {
 890                 printf("%s: mmc create fail!\n", __func__);
 891                 return -ENOMEM;
 892         }
 893
 894         return 0;
 895 }
 896 #endif