drivers/mmc/sdhci-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <dm/device_compat.h>
  10 #include <linux/bitfield.h>
  11 #include <linux/bug.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/sizes.h>
  15 #include <linux/libfdt.h>
  16 #include <mmc.h>
  17 #include <sdhci.h>
  18
  19 /* HRS - Host Register Set (specific to Cadence) */
  20 #define SDHCI_CDNS_HRS04                0x10            /* PHY access port */
  21 #define   SDHCI_CDNS_HRS04_ACK                  BIT(26)
  22 #define   SDHCI_CDNS_HRS04_RD                   BIT(25)
  23 #define   SDHCI_CDNS_HRS04_WR                   BIT(24)
  24 #define   SDHCI_CDNS_HRS04_RDATA                GENMASK(23, 16)
  25 #define   SDHCI_CDNS_HRS04_WDATA                GENMASK(15, 8)
  26 #define   SDHCI_CDNS_HRS04_ADDR                 GENMASK(5, 0)
  27
  28 #define SDHCI_CDNS_HRS06                0x18            /* eMMC control */
  29 #define   SDHCI_CDNS_HRS06_TUNE_UP              BIT(15)
  30 #define   SDHCI_CDNS_HRS06_TUNE                 GENMASK(13, 8)
  31 #define   SDHCI_CDNS_HRS06_MODE                 GENMASK(2, 0)
  32 #define   SDHCI_CDNS_HRS06_MODE_SD              0x0
  33 #define   SDHCI_CDNS_HRS06_MODE_MMC_SDR         0x2
  34 #define   SDHCI_CDNS_HRS06_MODE_MMC_DDR         0x3
  35 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS200       0x4
  36 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400       0x5
  37 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES     0x6
  38
  39 /* SRS - Slot Register Set (SDHCI-compatible) */
  40 #define SDHCI_CDNS_SRS_BASE             0x200
  41
  42 /* PHY */
  43 #define SDHCI_CDNS_PHY_DLY_SD_HS        0x00
  44 #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT   0x01
  45 #define SDHCI_CDNS_PHY_DLY_UHS_SDR12    0x02
  46 #define SDHCI_CDNS_PHY_DLY_UHS_SDR25    0x03
  47 #define SDHCI_CDNS_PHY_DLY_UHS_SDR50    0x04
  48 #define SDHCI_CDNS_PHY_DLY_UHS_DDR50    0x05
  49 #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY  0x06
  50 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR     0x07
  51 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR     0x08
  52 #define SDHCI_CDNS_PHY_DLY_SDCLK        0x0b
  53 #define SDHCI_CDNS_PHY_DLY_HSMMC        0x0c
  54 #define SDHCI_CDNS_PHY_DLY_STROBE       0x0d
  55
  56 /*
  57  * The tuned val register is 6 bit-wide, but not the whole of the range is
  58  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
  59  * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
  60  */
  61 #define SDHCI_CDNS_MAX_TUNING_LOOP      40
  62
  63 struct sdhci_cdns_plat {
  64         struct mmc_config cfg;
  65         struct mmc mmc;
  66         void __iomem *hrs_addr;
  67 };
  68
  69 struct sdhci_cdns_phy_cfg {
  70         const char *property;
  71         u8 addr;
  72 };
  73
  74 static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  75         { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  76         { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  77         { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  78         { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  79         { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  80         { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  81         { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  82         { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  83         { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  84         { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  85         { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  86 };
  87
  88 static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
  89                                     u8 addr, u8 data)
  90 {
  91         void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
  92         u32 tmp;
  93         int ret;
  94
  95         tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
  96               FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
  97         writel(tmp, reg);
  98
  99         tmp |= SDHCI_CDNS_HRS04_WR;
 100         writel(tmp, reg);
 101
 102         ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
 103         if (ret)
 104                 return ret;
 105
 106         tmp &= ~SDHCI_CDNS_HRS04_WR;
 107         writel(tmp, reg);
 108
 109         return 0;
 110 }
 111
 112 static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
 113                                 const void *fdt, int nodeoffset)
 114 {
 115         const fdt32_t *prop;
 116         int ret, i;
 117
 118         for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
 119                 prop = fdt_getprop(fdt, nodeoffset,
 120                                    sdhci_cdns_phy_cfgs[i].property, NULL);
 121                 if (!prop)
 122                         continue;
 123
 124                 ret = sdhci_cdns_write_phy_reg(plat,
 125                                                sdhci_cdns_phy_cfgs[i].addr,
 126                                                fdt32_to_cpu(*prop));
 127                 if (ret)
 128                         return ret;
 129         }
 130
 131         return 0;
 132 }
 133
 134 static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
 135 {
 136         struct mmc *mmc = host->mmc;
 137         struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
 138         unsigned int clock = mmc->clock;
 139         u32 mode, tmp;
 140
 141         /*
 142          * REVISIT:
 143          * The mode should be decided by MMC_TIMING_* like Linux, but
 144          * U-Boot does not support timing.  Use the clock frequency instead.
 145          */
 146         if (clock <= 26000000) {
 147                 mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
 148         } else if (clock <= 52000000) {
 149                 if (mmc->ddr_mode)
 150                         mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
 151                 else
 152                         mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
 153         } else {
 154                 if (mmc->ddr_mode)
 155                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
 156                 else
 157                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
 158         }
 159
 160         tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
 161         tmp &= ~SDHCI_CDNS_HRS06_MODE;
 162         tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
 163         writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
 164 }
 165
 166 static const struct sdhci_ops sdhci_cdns_ops = {
 167         .set_control_reg = sdhci_cdns_set_control_reg,
 168 };
 169
 170 static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
 171                                    unsigned int val)
 172 {
 173         void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
 174         u32 tmp;
 175         int i, ret;
 176
 177         if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
 178                 return -EINVAL;
 179
 180         tmp = readl(reg);
 181         tmp &= ~SDHCI_CDNS_HRS06_TUNE;
 182         tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
 183
 184         /*
 185          * Workaround for IP errata:
 186          * The IP6116 SD/eMMC PHY design has a timing issue on receive data
 187          * path. Send tune request twice.
 188          */
 189         for (i = 0; i < 2; i++) {
 190                 tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
 191                 writel(tmp, reg);
 192
 193                 ret = readl_poll_timeout(reg, tmp,
 194                                          !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 1);
 195                 if (ret)
 196                         return ret;
 197         }
 198
 199         return 0;
 200 }
 201
 202 static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
 203                                                     unsigned int opcode)
 204 {
 205         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 206         struct mmc *mmc = &plat->mmc;
 207         int cur_streak = 0;
 208         int max_streak = 0;
 209         int end_of_streak = 0;
 210         int i;
 211
 212         /*
 213          * This handler only implements the eMMC tuning that is specific to
 214          * this controller.  The tuning for SD timing should be handled by the
 215          * SDHCI core.
 216          */
 217         if (!IS_MMC(mmc))
 218                 return -ENOTSUPP;
 219
 220         if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
 221                 return -EINVAL;
 222
 223         for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
 224                 if (sdhci_cdns_set_tune_val(plat, i) ||
 225                     mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
 226                         cur_streak = 0;
 227                 } else { /* good */
 228                         cur_streak++;
 229                         if (cur_streak > max_streak) {
 230                                 max_streak = cur_streak;
 231                                 end_of_streak = i;
 232                         }
 233                 }
 234         }
 235
 236         if (!max_streak) {
 237                 dev_err(dev, "no tuning point found\n");
 238                 return -EIO;
 239         }
 240
 241         return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
 242 }
 243
 244 static struct dm_mmc_ops sdhci_cdns_mmc_ops;
 245
 246 static int sdhci_cdns_bind(struct udevice *dev)
 247 {
 248         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 249
 250         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 251 }
 252
 253 static int sdhci_cdns_probe(struct udevice *dev)
 254 {
 255         DECLARE_GLOBAL_DATA_PTR;
 256         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 257         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 258         struct sdhci_host *host = dev_get_priv(dev);
 259         fdt_addr_t base;
 260         int ret;
 261
 262         base = devfdt_get_addr(dev);
 263         if (base == FDT_ADDR_T_NONE)
 264                 return -EINVAL;
 265
 266         plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
 267         if (!plat->hrs_addr)
 268                 return -ENOMEM;
 269
 270         host->name = dev->name;
 271         host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
 272         host->ops = &sdhci_cdns_ops;
 273         host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
 274         sdhci_cdns_mmc_ops = sdhci_ops;
 275 #ifdef MMC_SUPPORTS_TUNING
 276         sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
 277 #endif
 278
 279         ret = mmc_of_parse(dev, &plat->cfg);
 280         if (ret)
 281                 return ret;
 282
 283         ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
 284         if (ret)
 285                 return ret;
 286
 287         host->mmc = &plat->mmc;
 288         host->mmc->dev = dev;
 289         ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
 290         if (ret)
 291                 return ret;
 292
 293         upriv->mmc = &plat->mmc;
 294         host->mmc->priv = host;
 295
 296         return sdhci_probe(dev);
 297 }
 298
 299 static const struct udevice_id sdhci_cdns_match[] = {
 300         { .compatible = "socionext,uniphier-sd4hc" },
 301         { .compatible = "cdns,sd4hc" },
 302         { /* sentinel */ }
 303 };
 304
 305 U_BOOT_DRIVER(sdhci_cdns) = {
 306         .name = "sdhci-cdns",
 307         .id = UCLASS_MMC,
 308         .of_match = sdhci_cdns_match,
 309         .bind = sdhci_cdns_bind,
 310         .probe = sdhci_cdns_probe,
 311         .priv_auto_alloc_size = sizeof(struct sdhci_host),
 312         .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
 313         .ops = &sdhci_cdns_mmc_ops,
 314 };