drivers/mmc/sdhci-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <dm/device_compat.h>
  10 #include <linux/bitfield.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/sizes.h>
  14 #include <linux/libfdt.h>
  15 #include <mmc.h>
  16 #include <sdhci.h>
  17
  18 /* HRS - Host Register Set (specific to Cadence) */
  19 #define SDHCI_CDNS_HRS04                0x10            /* PHY access port */
  20 #define   SDHCI_CDNS_HRS04_ACK                  BIT(26)
  21 #define   SDHCI_CDNS_HRS04_RD                   BIT(25)
  22 #define   SDHCI_CDNS_HRS04_WR                   BIT(24)
  23 #define   SDHCI_CDNS_HRS04_RDATA                GENMASK(23, 16)
  24 #define   SDHCI_CDNS_HRS04_WDATA                GENMASK(15, 8)
  25 #define   SDHCI_CDNS_HRS04_ADDR                 GENMASK(5, 0)
  26
  27 #define SDHCI_CDNS_HRS06                0x18            /* eMMC control */
  28 #define   SDHCI_CDNS_HRS06_TUNE_UP              BIT(15)
  29 #define   SDHCI_CDNS_HRS06_TUNE                 GENMASK(13, 8)
  30 #define   SDHCI_CDNS_HRS06_MODE                 GENMASK(2, 0)
  31 #define   SDHCI_CDNS_HRS06_MODE_SD              0x0
  32 #define   SDHCI_CDNS_HRS06_MODE_MMC_SDR         0x2
  33 #define   SDHCI_CDNS_HRS06_MODE_MMC_DDR         0x3
  34 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS200       0x4
  35 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400       0x5
  36 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES     0x6
  37
  38 /* SRS - Slot Register Set (SDHCI-compatible) */
  39 #define SDHCI_CDNS_SRS_BASE             0x200
  40
  41 /* PHY */
  42 #define SDHCI_CDNS_PHY_DLY_SD_HS        0x00
  43 #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT   0x01
  44 #define SDHCI_CDNS_PHY_DLY_UHS_SDR12    0x02
  45 #define SDHCI_CDNS_PHY_DLY_UHS_SDR25    0x03
  46 #define SDHCI_CDNS_PHY_DLY_UHS_SDR50    0x04
  47 #define SDHCI_CDNS_PHY_DLY_UHS_DDR50    0x05
  48 #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY  0x06
  49 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR     0x07
  50 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR     0x08
  51 #define SDHCI_CDNS_PHY_DLY_SDCLK        0x0b
  52 #define SDHCI_CDNS_PHY_DLY_HSMMC        0x0c
  53 #define SDHCI_CDNS_PHY_DLY_STROBE       0x0d
  54
  55 /*
  56  * The tuned val register is 6 bit-wide, but not the whole of the range is
  57  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
  58  * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
  59  */
  60 #define SDHCI_CDNS_MAX_TUNING_LOOP      40
  61
  62 struct sdhci_cdns_plat {
  63         struct mmc_config cfg;
  64         struct mmc mmc;
  65         void __iomem *hrs_addr;
  66 };
  67
  68 struct sdhci_cdns_phy_cfg {
  69         const char *property;
  70         u8 addr;
  71 };
  72
  73 static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  74         { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  75         { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  76         { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  77         { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  78         { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  79         { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  80         { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  81         { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  82         { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  83         { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  84         { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  85 };
  86
  87 static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
  88                                     u8 addr, u8 data)
  89 {
  90         void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
  91         u32 tmp;
  92         int ret;
  93
  94         tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
  95               FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
  96         writel(tmp, reg);
  97
  98         tmp |= SDHCI_CDNS_HRS04_WR;
  99         writel(tmp, reg);
 100
 101         ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
 102         if (ret)
 103                 return ret;
 104
 105         tmp &= ~SDHCI_CDNS_HRS04_WR;
 106         writel(tmp, reg);
 107
 108         return 0;
 109 }
 110
 111 static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
 112                                 const void *fdt, int nodeoffset)
 113 {
 114         const fdt32_t *prop;
 115         int ret, i;
 116
 117         for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
 118                 prop = fdt_getprop(fdt, nodeoffset,
 119                                    sdhci_cdns_phy_cfgs[i].property, NULL);
 120                 if (!prop)
 121                         continue;
 122
 123                 ret = sdhci_cdns_write_phy_reg(plat,
 124                                                sdhci_cdns_phy_cfgs[i].addr,
 125                                                fdt32_to_cpu(*prop));
 126                 if (ret)
 127                         return ret;
 128         }
 129
 130         return 0;
 131 }
 132
 133 static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
 134 {
 135         struct mmc *mmc = host->mmc;
 136         struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
 137         unsigned int clock = mmc->clock;
 138         u32 mode, tmp;
 139
 140         /*
 141          * REVISIT:
 142          * The mode should be decided by MMC_TIMING_* like Linux, but
 143          * U-Boot does not support timing.  Use the clock frequency instead.
 144          */
 145         if (clock <= 26000000) {
 146                 mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
 147         } else if (clock <= 52000000) {
 148                 if (mmc->ddr_mode)
 149                         mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
 150                 else
 151                         mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
 152         } else {
 153                 if (mmc->ddr_mode)
 154                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
 155                 else
 156                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
 157         }
 158
 159         tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
 160         tmp &= ~SDHCI_CDNS_HRS06_MODE;
 161         tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
 162         writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
 163 }
 164
 165 static const struct sdhci_ops sdhci_cdns_ops = {
 166         .set_control_reg = sdhci_cdns_set_control_reg,
 167 };
 168
 169 static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
 170                                    unsigned int val)
 171 {
 172         void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
 173         u32 tmp;
 174         int i, ret;
 175
 176         if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
 177                 return -EINVAL;
 178
 179         tmp = readl(reg);
 180         tmp &= ~SDHCI_CDNS_HRS06_TUNE;
 181         tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
 182
 183         /*
 184          * Workaround for IP errata:
 185          * The IP6116 SD/eMMC PHY design has a timing issue on receive data
 186          * path. Send tune request twice.
 187          */
 188         for (i = 0; i < 2; i++) {
 189                 tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
 190                 writel(tmp, reg);
 191
 192                 ret = readl_poll_timeout(reg, tmp,
 193                                          !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 1);
 194                 if (ret)
 195                         return ret;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
 202                                                     unsigned int opcode)
 203 {
 204         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 205         struct mmc *mmc = &plat->mmc;
 206         int cur_streak = 0;
 207         int max_streak = 0;
 208         int end_of_streak = 0;
 209         int i;
 210
 211         /*
 212          * This handler only implements the eMMC tuning that is specific to
 213          * this controller.  The tuning for SD timing should be handled by the
 214          * SDHCI core.
 215          */
 216         if (!IS_MMC(mmc))
 217                 return -ENOTSUPP;
 218
 219         if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
 220                 return -EINVAL;
 221
 222         for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
 223                 if (sdhci_cdns_set_tune_val(plat, i) ||
 224                     mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
 225                         cur_streak = 0;
 226                 } else { /* good */
 227                         cur_streak++;
 228                         if (cur_streak > max_streak) {
 229                                 max_streak = cur_streak;
 230                                 end_of_streak = i;
 231                         }
 232                 }
 233         }
 234
 235         if (!max_streak) {
 236                 dev_err(dev, "no tuning point found\n");
 237                 return -EIO;
 238         }
 239
 240         return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
 241 }
 242
 243 static struct dm_mmc_ops sdhci_cdns_mmc_ops;
 244
 245 static int sdhci_cdns_bind(struct udevice *dev)
 246 {
 247         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 248
 249         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 250 }
 251
 252 static int sdhci_cdns_probe(struct udevice *dev)
 253 {
 254         DECLARE_GLOBAL_DATA_PTR;
 255         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 256         struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
 257         struct sdhci_host *host = dev_get_priv(dev);
 258         fdt_addr_t base;
 259         int ret;
 260
 261         base = devfdt_get_addr(dev);
 262         if (base == FDT_ADDR_T_NONE)
 263                 return -EINVAL;
 264
 265         plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
 266         if (!plat->hrs_addr)
 267                 return -ENOMEM;
 268
 269         host->name = dev->name;
 270         host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
 271         host->ops = &sdhci_cdns_ops;
 272         host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
 273         sdhci_cdns_mmc_ops = sdhci_ops;
 274 #ifdef MMC_SUPPORTS_TUNING
 275         sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
 276 #endif
 277
 278         ret = mmc_of_parse(dev, &plat->cfg);
 279         if (ret)
 280                 return ret;
 281
 282         ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
 283         if (ret)
 284                 return ret;
 285
 286         host->mmc = &plat->mmc;
 287         host->mmc->dev = dev;
 288         ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
 289         if (ret)
 290                 return ret;
 291
 292         upriv->mmc = &plat->mmc;
 293         host->mmc->priv = host;
 294
 295         return sdhci_probe(dev);
 296 }
 297
 298 static const struct udevice_id sdhci_cdns_match[] = {
 299         { .compatible = "socionext,uniphier-sd4hc" },
 300         { .compatible = "cdns,sd4hc" },
 301         { /* sentinel */ }
 302 };
 303
 304 U_BOOT_DRIVER(sdhci_cdns) = {
 305         .name = "sdhci-cdns",
 306         .id = UCLASS_MMC,
 307         .of_match = sdhci_cdns_match,
 308         .bind = sdhci_cdns_bind,
 309         .probe = sdhci_cdns_probe,
 310         .priv_auto_alloc_size = sizeof(struct sdhci_host),
 311         .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
 312         .ops = &sdhci_cdns_mmc_ops,
 313 };