drivers/mmc/rockchip_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2013 Google, Inc
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <dt-structs.h>
  10 #include <dwmmc.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <mapmem.h>
  14 #include <pwrseq.h>
  15 #include <syscon.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch-rockchip/clock.h>
  18 #include <asm/arch-rockchip/periph.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21
  22 struct rockchip_mmc_plat {
  23 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  24         struct dtd_rockchip_rk3288_dw_mshc dtplat;
  25 #endif
  26         struct mmc_config cfg;
  27         struct mmc mmc;
  28 };
  29
  30 struct rockchip_dwmmc_priv {
  31         struct clk clk;
  32         struct dwmci_host host;
  33         int fifo_depth;
  34         bool fifo_mode;
  35         u32 minmax[2];
  36 };
  37
  38 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
  39 {
  40         struct udevice *dev = host->priv;
  41         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  42         int ret;
  43
  44         ret = clk_set_rate(&priv->clk, freq);
  45         if (ret < 0) {
  46                 debug("%s: err=%d\n", __func__, ret);
  47                 return ret;
  48         }
  49
  50         return freq;
  51 }
  52
  53 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
  54 {
  55 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  56         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  57         struct dwmci_host *host = &priv->host;
  58
  59         host->name = dev->name;
  60         host->ioaddr = dev_read_addr_ptr(dev);
  61         host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
  62         host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
  63         host->priv = dev;
  64
  65         /* use non-removeable as sdcard and emmc as judgement */
  66         if (dev_read_bool(dev, "non-removable"))
  67                 host->dev_index = 0;
  68         else
  69                 host->dev_index = 1;
  70
  71         priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
  72
  73         if (priv->fifo_depth < 0)
  74                 return -EINVAL;
  75         priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
  76
  77 #ifdef CONFIG_SPL_BUILD
  78         if (!priv->fifo_mode)
  79                 priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
  80 #endif
  81
  82         /*
  83          * 'clock-freq-min-max' is deprecated
  84          * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
  85          */
  86         if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
  87                 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
  88
  89                 if (val < 0)
  90                         return val;
  91
  92                 priv->minmax[0] = 400000;  /* 400 kHz */
  93                 priv->minmax[1] = val;
  94         } else {
  95                 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
  96                       __func__);
  97         }
  98 #endif
  99         return 0;
 100 }
 101
 102 static int rockchip_dwmmc_probe(struct udevice *dev)
 103 {
 104         struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
 105         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 106         struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 107         struct dwmci_host *host = &priv->host;
 108         struct udevice *pwr_dev __maybe_unused;
 109         int ret;
 110
 111 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 112         struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
 113
 114         host->name = dev->name;
 115         host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
 116         host->buswidth = dtplat->bus_width;
 117         host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
 118         host->priv = dev;
 119         host->dev_index = 0;
 120         priv->fifo_depth = dtplat->fifo_depth;
 121         priv->fifo_mode = 0;
 122         priv->minmax[0] = 400000;  /*  400 kHz */
 123         priv->minmax[1] = dtplat->max_frequency;
 124
 125         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
 126         if (ret < 0)
 127                 return ret;
 128 #else
 129         ret = clk_get_by_index(dev, 0, &priv->clk);
 130         if (ret < 0)
 131                 return ret;
 132 #endif
 133         host->fifoth_val = MSIZE(0x2) |
 134                 RX_WMARK(priv->fifo_depth / 2 - 1) |
 135                 TX_WMARK(priv->fifo_depth / 2);
 136
 137         host->fifo_mode = priv->fifo_mode;
 138
 139 #ifdef CONFIG_PWRSEQ
 140         /* Enable power if needed */
 141         ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
 142                                            &pwr_dev);
 143         if (!ret) {
 144                 ret = pwrseq_set_power(pwr_dev, true);
 145                 if (ret)
 146                         return ret;
 147         }
 148 #endif
 149         dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
 150         host->mmc = &plat->mmc;
 151         host->mmc->priv = &priv->host;
 152         host->mmc->dev = dev;
 153         upriv->mmc = host->mmc;
 154
 155         return dwmci_probe(dev);
 156 }
 157
 158 static int rockchip_dwmmc_bind(struct udevice *dev)
 159 {
 160         struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
 161
 162         return dwmci_bind(dev, &plat->mmc, &plat->cfg);
 163 }
 164
 165 static const struct udevice_id rockchip_dwmmc_ids[] = {
 166         { .compatible = "rockchip,rk2928-dw-mshc" },
 167         { .compatible = "rockchip,rk3288-dw-mshc" },
 168         { }
 169 };
 170
 171 U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
 172         .name           = "rockchip_rk3288_dw_mshc",
 173         .id             = UCLASS_MMC,
 174         .of_match       = rockchip_dwmmc_ids,
 175         .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
 176         .ops            = &dm_dwmci_ops,
 177         .bind           = rockchip_dwmmc_bind,
 178         .probe          = rockchip_dwmmc_probe,
 179         .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
 180         .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
 181 };
 182
 183 #ifdef CONFIG_PWRSEQ
 184 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
 185 {
 186         struct gpio_desc reset;
 187         int ret;
 188
 189         ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
 190         if (ret)
 191                 return ret;
 192         dm_gpio_set_value(&reset, 1);
 193         udelay(1);
 194         dm_gpio_set_value(&reset, 0);
 195         udelay(200);
 196
 197         return 0;
 198 }
 199
 200 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
 201         .set_power      = rockchip_dwmmc_pwrseq_set_power,
 202 };
 203
 204 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
 205         { .compatible = "mmc-pwrseq-emmc" },
 206         { }
 207 };
 208
 209 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
 210         .name           = "mmc_pwrseq_emmc",
 211         .id             = UCLASS_PWRSEQ,
 212         .of_match       = rockchip_dwmmc_pwrseq_ids,
 213         .ops            = &rockchip_dwmmc_pwrseq_ops,
 214 };
 215 #endif